GD32F350G8U6TR

GigaDevice Semiconductor Inc. GD32F350xx ARM® Cortex®-M4 32-bit MCU Datasheet GD32F350xx Table of Contents List of Figures ............................................................................................................................. 3 List of Tables ............................................................................................................................... 4 1 General description ......................................................................................................... 5 2 Device overview ............................................................................................................... 6 2.1 Device information .............................................................................................................................. 6 2.2 Block diagram ...................................................................................................................................... 7 2.3 Pinouts and pin assignment .............................................................................................................. 8 2.4 Memory map ...................................................................................................................................... 10 2.5 Clock tree ........................................................................................................................................... 10 2.6 Pin definitions .................................................................................................................................... 13 Functional description .................................................................................................. 22 3 3.1 ARM® Cortex®-M4 core .................................................................................................................... 22 3.2 On-chip memory................................................................................................................................ 22 3.3 Clock, reset and supply management ........................................................................................... 23 3.4 Boot modes ........................................................................................................................................ 23 3.5 Power saving modes ........................................................................................................................ 24 3.6 Analog to digital converter (ADC) ................................................................................................... 24 3.7 Digital to analog converter (DAC) ................................................................................................... 25 3.8 DMA .................................................................................................................................................... 25 3.9 General-purpose inputs/outputs (GPIOs) ...................................................................................... 25 3.10 Timers and PWM generation........................................................................................................... 26 3.11 Real time clock (RTC) ...................................................................................................................... 27 3.12 Inter-integrated circuit (I2C) ............................................................................................................. 27 3.13 Serial peripheral interface (SPI)...................................................................................................... 28 3.14 Universal synchronous asynchronous receiver transmitter (USART) ....................................... 28 3.15 Inter-IC sound (I2S) .......................................................................................................................... 28 3.16 HDMI CEC ......................................................................................................................................... 29 3.17 Universal serial bus on-the-go full-speed (USB OTG FS) .......................................................... 29 3.18 Touch sensing interface (TSI) ......................................................................................................... 29 3.19 Comparators (CMP) ......................................................................................................................... 30 3.20 Debug mode ...................................................................................................................................... 30 3.21 Package and operation temperature.............................................................................................. 30 Electrical characteristics .............................................................................................. 31 4 4.1 Absolute maximum ratings .............................................................................................................. 31 4.2 Recommended DC characteristics ................................................................................................. 31 4.3 Power consumption .......................................................................................................................... 32 4.4 EMC characteristics .......................................................................................................................... 33 4.5 Power supply supervisor characteristics ....................................................................................... 33 1 / 50 GD32F350xx 4.6 Electrical sensitivity........................................................................................................................... 34 4.7 External clock characteristics .......................................................................................................... 35 4.8 Internal clock characteristics ........................................................................................................... 35 4.9 PLL characteristics ........................................................................................................................... 36 4.10 Memory characteristics .................................................................................................................... 37 4.11 GPIO characteristics......................................................................................................................... 38 4.12 ADC characteristics .......................................................................................................................... 39 4.13 DAC characteristics .......................................................................................................................... 41 4.14 Comparators characteristics............................................................................................................ 42 4.15 I2C characteristics ............................................................................................................................ 43 4.16 SPI characteristics ............................................................................................................................ 43 4.17 USART characteristics ..................................................................................................................... 43 Package information ..................................................................................................... 44 5 5.1 QFN package outline dimensions .................................................................................................. 44 5.2 LQFP package outline dimensions ................................................................................................ 46 6 Ordering Information ..................................................................................................... 48 7 Revision History............................................................................................................. 49 2 / 50 GD32F350xx List of Figures Figure 1. GD32F350xx block diagram ...................................................................................................................... 7 Figure 2. GD32F350Rx LQFP64 pinouts ................................................................................................................. 8 Figure 3. GD32F350Cx LQFP48 pinouts ................................................................................................................. 8 Figure 4. GD32F350Kx QFN32 pinouts ................................................................................................................... 9 Figure 5. GD32F350Gx QFN28 pinouts ................................................................................................................... 9 Figure 6. GD32F350xx memory map ..................................................................................................................... 10 Figure 7. GD32F350xx clock tree............................................................................................................................ 12 Figure 8. QFN package outline ................................................................................................................................ 44 Figure 9. LQFP package outline .............................................................................................................................. 46 3 / 50 GD32F350xx List of Tables Table 1. GD32F350xx devices features and peripheral list ................................................................................... 6 Table 2. GD32F350xx pin definitions ...................................................................................................................... 13 Table 3. Port A alternate functions summary ........................................................................................................ 18 Table 4. Port B alternate functions summary ........................................................................................................ 19 Table 5. Port C alternate functions summary ........................................................................................................ 20 Table 6. Port D alternate functions summary ........................................................................................................ 20 Table 7. Port F alternate functions summary......................................................................................................... 21 Table 8. Absolute maximum ratings ........................................................................................................................ 31 Table 9. DC operating conditions ............................................................................................................................ 31 Table 10. Power consumption characteristics ....................................................................................................... 32 Table 11. EMS characteristics ................................................................................................................................. 33 Table 12. EMI characteristics................................................................................................................................... 33 Table 13 Power supply supervisor characteristics................................................................................................ 33 Table 14. ESD characteristics.................................................................................................................................. 34 Table 15. Static latch-up characteristics ................................................................................................................ 34 Table 16. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics ................. 35 Table 17. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ................... 35 Table 18. High speed internal clock (IRC8M) characteristics .............................................................................. 35 Table 19. High speed internal clock (IRC48M) characteristics ........................................................................... 36 Table 20. Low speed internal clock (IRC32K) characteristics ............................................................................. 36 Table 21. PLL characteristics ................................................................................................................................... 36 Table 22. Flash memory characteristics ................................................................................................................. 37 Table 23. I/O port characteristics ............................................................................................................................. 38 Table 24. ADC characteristics .................................................................................................................................. 39 Table 25. ADC RAIN max for fADC=40MHz ................................................................................................................. 39 Table 26. ADC dynamic accuracy at fADC = 28 MHz ............................................................................................. 40 Table 27. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 40 Table 28. ADC dynamic accuracy at fADC = 36 MHz ............................................................................................. 40 Table 29. ADC static accuracy at fADC = 14 MHz .................................................................................................. 40 Table 30. DAC characteristics ................................................................................................................................. 41 Table 31. CMP characteristics ................................................................................................................................. 42 Table 32. I2C characteristics .................................................................................................................................... 43 Table 33. SPI characteristics .................................................................................................................................... 43 Table 34. USART characteristics ............................................................................................................................ 43 Table 35. QFN package dimensions ....................................................................................................................... 45 Table 36. LQFP package dimensions ..................................................................................................................... 47 Table 37. Part ordering code for GD32F350xx devices ....................................................................................... 48 Table 38. Revision history......................................................................................................................................... 49 4 / 50 GD32F350xx 1 General description The GD32F350xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best costperformance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32F350xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 128 KB on-chip Flash memory and up to 16 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC, one 12-bit DAC and two comparators, up to five general-purpose 16-bit timers, a general-purpose 32-bit timer, a basic timer, a PWM advanced-control timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, a I2S, a HDMI-CEC, a TSI and an USB 2.0 OTG. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F350xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on. 5 / 50 GD32F350xx 2 Device overview 2.1 Device information Table 1. GD32F350xx devices features and peripheral list GD32F350xx Part Number G6 G8 K4 K6 K8 C4 C6 C8 CB R4 R6 R8 RB Code Area (KB) 16 32 64 16 32 64 16 32 64 64 16 32 64 64 Data Area (KB) 0 0 0 0 0 0 0 0 0 64 0 0 0 64 Total (KB) 16 32 64 16 32 64 16 32 64 128 16 32 64 128 4 6 8 4 6 8 4 6 8 16 4 8 16 16 32-bit GP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16-bit GP 5 5 5 5 5 5 5 5 5 5 5 5 5 5 16-bit Adv. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16-bit Basic 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SysTick 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 USART 1 2 2 1 2 2 1 2 2 2 1 2 2 2 I2C 1 1 2 1 1 2 1 1 2 2 1 1 2 2 SPI/I2S 1/1 1/1 2/1 1/1 1/1 2/1 1/1 1/1 2/1 2/1 1 1 2/1 2/1 USB 2.0 OTG 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HDMI CEC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIO 24 24 24 27 27 27 39 39 39 39 55 55 55 55 Capacitive Touch Channels 14 14 14 14 14 14 17 17 17 17 18 18 18 18 Analog Comparator 2 2 2 2 2 2 2 2 2 2 2 2 2 2 EXTI 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Units 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Channels (Ext.) 10 10 10 10 10 10 10 10 10 10 16 16 16 16 Channels (Int.) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Flash G4 ADC Connectivity Timers SRAM (KB) DAC Package QFN28 QFN32 LQFP48 LQFP64 6 / 50 GD32F350xx 2.2 Block diagram Figure 1. GD32F350xx block diagram LDO 1.2V TPIU SW AHB Matrix NVIC ICode DCode System ARM Cortex-M4 Processor Fmax: 108MHz AHB2: Fma x = 108MHz IBus GPIO Ports A, B, C, D, F SRAM Controller SRAM Flash Memory Controller Flash Memory POR/PDR LVD PLL USBFS Touch Sensing Interface DBus GP DMA 7chs AHB1: Fma x = 108MHz AHB to APB Bridge 2 CRC AHB to APB Bridge 1 RST/CLK Controller IRC28M 28MHz IRC48M 48MHz PMU EXTI FWDGT ADC HDMI-CEC TIMER0 TIMER14 APB1: Fmax = 54MHz CMP APB2: Fmax = 54MHz SYS Config Powered by V DD/VDDA RTC SPI0/I2S0 CMP0 IRC40K 40KHz WWDGT USART0 CMP1 HXTAL 4-32MHz IRC8M 8MHz Powered by LDO (1.2V) 12-bit SAR ADC Fmax: 108MHz I2C0 I2C1 CTC USART1 DAC TIMER15 12-bit DAC SPI1 TIMER16 TIMER5 TIMER1 TIMER2 TIMER13 7 / 50 GD32F350xx 2.3 Pinouts and pin assignment Figure 2. GD32F350Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PC12 PD2 PB3 PB4 PB6 PB5 PB7 BOOT0 PB8 PB9 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 PC13 2 47 PF6 PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT PF0-OSC_IN 4 45 PA12 5 44 PA11 PF1-OSC_OUT 6 43 PA10 7 42 PA9 NRST PC0 8 PC1 9 PC2 PC3 VSSA GigaDevice GD32F350Rx LQFP64 PF7 41 PA8 40 PC9 10 39 PC8 11 38 PC7 12 37 PC6 VDDA 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD VSS PB11 PB10 PB2 PB1 PB0 PC5 PA7 PC4 PA5 PA6 PA4 PF5 PF4 PA3 Figure 3. GD32F350Cx LQFP48 pinouts PA14 PA15 PB3 PB4 PB6 PB5 PB7 BOOT0 PB8 PB9 VSS VDD 48 47 46 45 44 43 42 41 40 39 38 37 VBAT 1 36 PF7 PF6 PC13 2 35 PC14-OSC32_IN 3 34 PA13 PC15-OSC32_OUT PF0-OSC_IN 4 33 PA12 5 32 PA11 PF1-OSC_OUT NRST VSSA 6 31 PA10 30 PA9 8 29 VDDA 9 28 PA8 PB15 PA0 10 27 PB14 PA1 PA2 11 26 PB13 12 25 PB12 GigaDevice GD32F350Cx LQFP48 7 13 14 15 16 17 18 19 20 21 22 23 24 VDD VSS PB11 PB10 PB2 PB1 PA7 PB0 PA6 PA5 PA4 PA3 8 / 50 GD32F350xx Figure 4. GD32F350Kx QFN32 pinouts 5 PA1 7 PA2 8 PA15 PB3 VDDA PA0 PB4 OSC_OUT/PF1 NRST 3 PB5 OSC_IN/PF0 2 PB6 1 PB7 BOOT0 PB8 VDD 32 31 30 29 28 27 26 25 24 PA14 23 PA13 22 PA12 21 PA11 20 PA10 GigaDevice GD32F350Kx QFN32 4 6 VSS, VSSA 19 PA9 18 PA8 17 VDD 9 10 11 12 13 14 15 16 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 Figure 5. GD32F350Gx QFN28 pinouts PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 1 28 27 26 25 24 23 22 21 PA13 20 PA12 GigaDevice GD32F350Gx QFN28 19 PA11 18 17 PA10 PA9 VSS,VSSA 16 VDD 15 9 10 11 12 13 14 PB1 OSC_IN/PF0 2 OSC_OUT/PF1 NRST 3 VDDA 5 PA0 6 PA1 7 4 8 PB0 PA7 PA6 PA5 PA4 PA3 PA2 9 / 50 GD32F350xx 2.4 Memory map Figure 6. GD32F350xx memory map Pre-defined Regions Bus ADDRESS Peripherals 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals External Device 0xA000 0000 - 0xDFFF FFFF Reserved External RAM 0x6000 0000 - 0x9FFF FFFF Reserved 0x5004 0000 - 0x5FFF FFFF Reserved 0x5000 0000 - 0x5003 FFFF USBFS 0x4800 1800 - 0x4FFF FFFF Reserved 0x4800 1400 - 0x4800 17FF GPIOF 0x4800 1000 - 0x4800 13FF Reserved 0x4800 0C00 - 0x4800 0FFF GPIOD 0x4800 0800 - 0x4800 0BFF GPIOC 0x4800 0400 - 0x4800 07FF GPIOB 0x4800 0000 - 0x4800 03FF GPIOA 0x4002 4400 - 0x47FF FFFF Reserved 0x4002 4000 - 0x4002 43FF TSI 0x4002 3400 - 0x4002 3FFF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF FMC 0x4002 1400 - 0x4002 1FFF Reserved 0x4002 1000 - 0x4002 13FF RCU 0x4002 0400 - 0x4002 0FFF Reserved 0x4002 0000 - 0x4002 03FF DMA 0x4001 8000 - 0x4001 FFFF Reserved 0x4001 5C00 - 0x4001 7FFF Reserved 0x4001 4C00 - 0x4001 5BFF Reserved 0x4001 4800 - 0x4001 4BFF TIMER16 0x4001 4400 - 0x4001 47FF TIMER15 0x4001 4000 - 0x4001 43FF TIMER14 0x4001 3C00 - 0x4001 3FFF Reserved 0x4001 3800 - 0x4001 3BFF USART0 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI0/I2S0 0x4001 2C00 - 0x4001 2FFF TIMER0 0x4001 2800 - 0x4001 2BFF Reserved 0x4001 2400 - 0x4001 27FF ADC 0x4001 0800 - 0x4001 23FF Reserved 0x4001 0400 - 0x4001 07FF EXTI AHB1 AHB2 AHB1 Peripherals APB2 10 / 50 GD32F350xx Pre-defined Regions Bus APB1 SRAM Code ADDRESS Peripherals 0x4001 0000 - 0x4001 03FF SYSCFG + CMP 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF CTC 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF CEC 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PMU 0x4000 6400 - 0x4000 6FFF Reserved 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF Reserved 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 4800 - 0x4000 53FF Reserved 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF Reserved 0x4000 3800 - 0x4000 3BFF SPI1 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIMER13 0x4000 1400 - 0x4000 1FFF Reserved 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0800 - 0x4000 0FFF Reserved 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2000 5000 - 0x3FFF FFFF Reserved 0x2000 0000 - 0x2000 4FFF SRAM 0x1FFF FC00 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF FBFF Option bytes 0x1FFF EC00 - 0x1FFF F7FF System memory 0x0810 0000 - 0x1FFF EBFF Reserved 0x0800 0000 - 0x080F FFFF Main Flash memory 0x0010 0000 - 0x07FF FFFF Reserved 0x0000 0000 - 0x000F FFFF Aliased to Flash or system memory 11 / 50 GD32F350xx 2.5 Clock tree Figure 7. GD32F350xx clock tree CTC CK_IRC48M CK_ CTC 48 MHz IRC48M 48 MHz CK48 MSEL CK_USBFS 1 USBFS Prescaler ÷1,1.5,2,2.5 3,3.5 ( to USBFS) 0 CK_ LXTAL ÷244 1 CK_ CEC ( to CEC) 0 CECSEL CK_I2S (to I2S) CK_FMC SCS[1:0] FMC enable ( by hardware) ( to FMC) HCLK CK_IRC8M 00 8 MHz IRC8M 0 /2 1 ×2,3,4 …,64 PLL CK_PLL 10 AHB enable CK_ SYS 108MHz max AHB Prescaler ÷1,2... 512 ( to AHB bus, Cortex-M4, SRAM, DMA) CK_ CST CK_ AHB ÷8 108MHz max ( to Cortex-M 4 SysTick) FCLK PLLMF PREDV PLLSEL PLLPRESEL CK_IRC48M 1 4- 32 MHz HXTAL Clock Monitor ÷1,2. ..16 0 01 CK_HXTAL /32 ( free running clock ) TIMER1,2,5,1 3 ÷[ apb1 prescaler/2] APB1 Prescaler ÷1,2,4,8,16 11 CK_TIMERx TIMERx enable to TIMER1,2,5,13 CK_ APB1 PCLK1 54 MHz max to APB1 peripherals Peripheral enable 32. 768 KHz LXTAL 01 CK_ RTC ( to RTC) 10 RTCSRC[1:0] 40 KHz IRC40K CK_F WDGT ( to F WDGT) TIMER0,14,1 5,16 ÷[apb2 prescaler/2] APB2 Prescaler ÷1,2,4,8,16 CK_TIMERx TIMERx enable to TIMER0,14,15,16 CK_ APB2 PCLK2 to APB2 peripherals 54 MHz max Peripheral enable CK_ OUT ÷1,2,4... 128 , CKOUTDIV 0 CK_IRC28M CK_IRC40K CK_ LXTAL CK_ SYS CK_IRC8M CK_ HXTAL /1,2 CK_PLL ADC Prescaler ÷2,3 ...9 1 CK_ ADC to ADC 0 28 MHz max ADCSEL 28 MHz IRC28M ÷ 1, 2 CK_IRC8M 11 CK_L XTAL 10 CK_ SYS 01 CK_ USART0 to USART0 00 Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator IRC8M: Internal 8M RC oscillators IRC48M: Internal 48M RC oscillators IRC32K: Internal 32K RC oscillator 12 / 50 GD32F350xx 2.6 Pin definitions Table 2. GD32F350xx pin definitions QFN28 Pin Type(1) 1 1 - - P 2 2 - - I/O 3 3 - - I/O 4 4 - - I/O I/O(2) Level QFN32 VBAT LQFP48 Pin Name LQFP64 Pins Default: VBAT PC13TAMPER- Default: PC13 Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1 RTC PC14OSC32IN PC15OSC32OUT Functions description Default: PC14 Additional: OSC32IN Default: PC15 Additional: OSC32OUT Default: PF0 PF0-OSCIN 5 5 2 2 I/O 5VT Alternate: CTC_SYNC Additional: OSCIN PF1- 6 3 3 I/O NRST 7 7 4 4 I/O Default: NRST PC0 8 - - - I/O Alternate: EVENTOUT OSCOUT 5VT Default: PF1 6 Additional: OSCOUT Default: PC0 Additional: ADC_IN10 Default: PC1 PC1 9 - - - I/O Alternate: EVENTOUT Additional: ADC_IN11 Default: PC2 PC2 10 - - - I/O Alternate: EVENTOUT Additional: ADC_IN12 Default: PC3 PC3 11 - - - I/O Alternate: EVENTOUT Additional: ADC_IN13 VSSA 12 8 0 0 P Default: VSSA VDDA 13 9 5 5 P Default: VDDA Default: PA0 PA0-WKUP 14 10 6 6 I/O Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0, TIMER1_ETI, CMP0_OUT, TSI_G0_IO0, I2C1_SCL Additional: ADC_IN0, CMP0_IM6, RTC_TAMP1, WKUP0 Default: PA1 PA1 15 11 7 7 I/O Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1, TSI_G0_IO1, I2C1_SDA, EVENTOUT Additional: ADC_IN1, CMP0_IP 13 / 50 GD32F350xx I/O(2) Level Pin Type(1) QFN28 QFN32 LQFP48 Pin Name LQFP64 Pins Functions description Default: PA2 PA2 16 12 8 8 Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2, I/O TIMER14_CH0 , CMP1_OUT,TSI_G0_IO2 Additional: ADC_IN2, CMP1_IM6 Default: PA3 PA3 17 13 9 9 Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3, I/O TIMER14_CH1, TSI_G0_IO3 Additional: ADC_IN3, CMP1_IP PF4 PF5 18 19 - - - I/O I/O 5VT 5VT Default: PF4 Alternate: EVENTOUT Default: PF5 Alternate: EVENTOUT Default: PA4 PA4 20 14 10 10 I/O Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, TSI_G1_IO0, SPI1_NSS Additional: ADC_IN4, CMP0_IM4, CMP1_IM4, DAC0_OUT Default: PA5 PA5 21 15 11 11 I/O Alternate: SPI0_SCK, I2S0_CK, CEC, TIMER1_CH0, TIMER1_ETI, TSI_G1_IO1 Additional: ADC_IN5, CMP0_IM5, CMP1_IM5 Default: PA6 PA6 22 16 12 12 I/O Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, CMP0_OUT, TSI_G1_IO2, EVENTOUT Additional: ADC_IN6 Default: PA7 Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, TIMER13_CH0, PA7 23 17 13 13 I/O TIMER0_CH0_ON, TIMER16_CH0, CMP1_OUT, TSI_G1_IO3, EVENTOUT Additional: ADC_IN7 Default: PC4 PC4 24 - - - I/O Alternate: EVENTOUT Additional: ADC_IN14 Default: PC5 PC5 25 - - - I/O Alternate: TSI_G2_IO0 Additional: ADC_IN15, WKUP4 Default: PB0 PB0 26 18 14 14 I/O Alternate: TIMER2_CH2, TIMER0_CH1_ON, TSI_G2_IO1, USART1_RX, EVENTOUT Additional: ADC_IN8 Default: PB1 PB1 27 19 15 15 I/O Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, TSI_G2_IO2, SPI1_SCK Additional: ADC_IN9 14 / 50 GD32F350xx I/O(2) Level QFN28 20 16 - QFN32 28 Pin Type(1) PB2 LQFP48 Pin Name LQFP64 Pins I/O 5VT Functions description Default: PB2 Alternate: TSI_G2_IO3 Default: PB10 PB10 29 21 - - I/O 5VT Alternate: I2C0_SCL(3),I2C1_SCL(4), CEC, TIMER1_CH2, TSITG, SPI1_IO2 Default: PB11 PB11 30 22 - - I/O 5VT Alternate: I2C0_SDA(3),I2C1_SDA(4), TIMER1_CH3, TSI_G5_IO0, EVENTOUT, SPI1_IO3 VSS 31 23 - - VDD 32 24 17 16 P Default: VSS P Default: VDD Default: PB12 PB12 33 25 - - I/O PB13 34 26 - - I/O (3) (4) 5VT Alternate: SPI0_NSS , SPI1_NSS , TIMER0_BKIN, TSI_G5_IO1, I2C1_SMBA, EVENTOUT 5VT Default: PB13 Alternate: SPI0_SCK(3), SPI1_SCK(4), TIMER0_CH0_ON, TSI_G5_IO2 Default: PB14 PB14 35 27 - - I/O 5VT Alternate: SPI0_MISO(3), SPI1_MISO(4), TIMER0_CH1_ON, TIMER14_CH0, TSI_G5_IO3 Default: PB15 Alternate: SPI0_MOSI(3), SPI1_MOSI(4), TIMER0_CH2_ON, PB15 36 28 - - I/O 5VT TIMER14_CH0_ON, TIMER14_CH1 Additional: RTC_REFIN, WKUP6 PC6 PC7 PC8 37 38 39 PC9 40 PA8 41 - - - I/O I/O I/O 5VT 5VT 5VT Default: PC6 Alternate: TIMER2_CH0, I2S0_MCK Default: PC7 Alternate: TIMER2_CH1 Default: PC8 Alternate: TIMER2_CH2 Default: PC9 - I/O 5VT 29 18 - I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX, Alternate: TIMER2_CH3 Default: PA8 EVENTOUT,USBFS_SOF,CTC_SYNC Default: PA9 PA9 42 30 19 17 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN, TSI_G3_IO0, I2C0_SCL,USBFS_VBUS Default: PA10 PA10 43 31 20 18 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN, TSI_G3_IO1, I2C0_SDA, USBFS_ID Default: PA11 PA11 44 32 21 19 I/O 5VT Alternate: USART0_CTS, TIMER0_CH3, CMP0_OUT, TSI_G3_IO2, EVENTOUT, SPI1_IO2 15 / 50 GD32F350xx I/O(2) Level Pin Type(1) QFN28 QFN32 LQFP48 Pin Name LQFP64 Pins Functions description Additional: USBFS_DM Default: PA12 PA12 45 33 22 20 I/O 5VT Alternate: USART0_RTS, TIMER0_ETI, CMP1_OUT, TSI_G3_IO3, EVENTOUT, SPI1_IO3 Additional: USBFS_DP PA13 46 34 23 21 I/O 5VT PF6 47 35 - - I/O 5VT PF7 48 36 - - I/O 5VT PA14 49 37 24 22 I/O 5VT Default: PA13 Alternate: IFRP_OUT, SWDIO, SPI1_MISO Default: PF6 Alternate: I2C0_SCL(3), I2C1_SCL(4) Default: PF7 Alternate: I2C0_SDA(3), I2C1_SDA(4) Default: PA14 Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI Default: PA15 PA15 50 38 25 23 I/O 5VT Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), TIMER1_CH0, TIMER1_ETI, SPI1_NSS, EVENTOUT PC10 51 - - - I/O 5VT Default: PC10 PC11 52 - - - I/O 5VT Default: PC11 PC12 53 - - - I/O 5VT Default: PC12 PD2 54 - - - I/O 5VT PB3 55 I/O 5VT Alternate: SPI0_SCK, I2S0_CK, TIMER1_CH1, TSI_G4_IO0, Default: PD2 Alternate: TIMER2_ETI Default: PB3 39 26 24 EVENTOUT Default: PB4 PB4 56 40 27 25 I/O 5VT Alternate: SPI0_MISO,I2S0_MCK, TIMER2_CH0, TSI_G4_IO1, EVENTOUT Default: PB5 PB5 57 41 28 26 I/O 5VT Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BKIN, TIMER2_CH1 Additional:WKUP5 PB6 58 42 29 27 I/O 5VT PB7 59 43 30 28 I/O 5VT BOOT0 60 44 31 1 I PB8 61 45 32 - I/O Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON, TSI_G4_IO2 Default: PB7 Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON,TSI_G4_IO3 Default: BOOT0 5VT Default: PB8 Alternate: I2C0_SCL, CEC, TIMER15_CH0, TSITG Default: PB9 PB9 62 46 - - I/O VSS 63 47 0 0 P 5VT Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0, EVENTOUT, I2S0_MCK Default: VSS 16 / 50 GD32F350xx QFN28 Pin Type(1) 64 48 1 - P I/O(2) Level QFN32 VDD LQFP48 Pin Name LQFP64 Pins Functions description Default: VDD Notes: 1. Type: I = input, O = output, P = power. 2. I/O Level: 5VT = 5 V tolerant. 3. This feature is available on GD32F350x4 devices only. 4. This feature is available on GD32F350x8 and GD32F350x6 devices only. 17 / 50 GD32F350xx Table 3. Port A alternate functions summary Pin Name AF0 AF1 AF2 USART0_CTS(1) PA0 (2) USART1_CTS AF3 AF4 TSI_G0_IO0 I2C1_SCL TIMER1_CH1 TSI_G0_IO1 I2C1_SDA TIMER1_CH2 TSI_G0_IO2 TIMER1_CH3 TSI_G0_IO3 AF5 AF6 AF7 TIMER1_CH0,TIMER1_ CMP0_OUT ETI USART0_RTS(1) PA1 EVENTOUT PA2 TIMER14_CH0 PA3 TIMER14_CH1 USART1_RTS(2) USART0_TX(1) CMP1_OUT USART1_TX(2) USART0_RX(1) USART1_RX(2) SPI0_NSS/ USART0_CK(1) I2S0_WS USART1_CK(2) PA4 TSI_G1_IO0 TIMER13_CH0 SPI1_NSS TIMER1_CH0, SPI0_SCK/ PA5 CEC TIMER1_ TSI_G1_IO1 I2S0_CK ETI SPI0_MISO/ PA6 TIMER2_CH0 TIMER0_BKIN TSI_G1_IO2 TIMER2_CH1 TIMER0_CH0_ON TSI_G1_IO3 TIMER15_CH0 EVENTOUT CMP0_OUT TIMER13_CH0 TIMER16_CH0 EVENTOUT CMP1_OUT CTC_SYNC I2S0_MCK SPI0_MOSI/ PA7 I2S0_SD PA8 CK_OUT USART0_CK TIMER0_CH0 EVENTOUT USART1_TX USBFS_SOF PA9 TIMER14_BKIN USART0_TX TIMER0_CH1 TSI_G3_IO0 I2C0_SCL USBFS_VBUS PA10 TIMER16_BKIN USART0_RX TIMER0_CH2 TSI_G3_IO1 I2C0_SDA USBFS_ID PA11 EVENTOUT USART0_CTS TIMER0_CH3 TSI_G3_IO2 SPI1_IO2 CMP0_OUT PA12 EVENTOUT USART0_RTS TIMER0_ETI TSI_G3_IO3 SPI1_IO3 CMP1_OUT PA13 SWDIO IFRP_OUT PA14 SWCLK SPI1_MISO USART0_TX(1) SPI1_MOSI USART1_TX(2) TIMER1_CH0, SPI0_NSS/ USART0_RX(1) I2S0_WS USART1_RX(2) PA15 TIMER1_ EVENTOUT SPI1_NSS ETI 1. This feature is available on GD32F350x4 devices only. 2. This feature is available on GD32F350xB, GD32F350x8 and GD32F350x6 devices only. 18 / 50 GD32F350xx Table 4. Port B alternate functions summary Pin AF0 AF1 AF2 AF3 AF4 PB0 EVENTOUT TIMER2_CH2 TIMER0_CH1_ON TSI_G2_IO1 USART1_RX PB1 TIMER13_CH0 TIMER2_CH3 TIMER0_CH2_ON TSI_G2_IO2 Name PB2 AF5 AF6 SPI1_SCK TSI_G2_IO3 SPI0_SCK / PB3 EVENTOUT TIMER1_CH1 TSI_G4_IO0 TIMER2_CH0 EVENTOUT TSI_G4_IO1 TIMER2_CH1 TIMER15_BKIN I2C0_SMBA I2S0_CK SPI0_MISO / PB4 I2S0_MCK SPI0_MOSI / PB5 I2S0_SD PB6 USART0_TX I2C0_SCL TIMER15_CH0_ON TSI_G4_IO2 PB7 USART0_RX I2C0_SDA TIMER16_CH0_ON TSI_G4_IO3 PB8 CEC I2C0_SCL TIMER15_CH0 TSITG PB9 IFRP_OUT I2C0_SDA TIMER16_CH0 EVENTOUT PB10 CEC TIMER1_CH2 TSITG SPI1_IO2 PB11 EVENTOUT TIMER1_CH3 TSI_G5_IO0 SPI1_IO3 TIMER0_BKIN TSI_G5_IO1 TIMER0_CH0_ON TSI_G5_IO2 TIMER14_CH0 TIMER0_CH1_ON TSI_G5_IO3 TIMER14_CH1 TIMER0_CH2_ON TIMER14_CH0_ON I2S0_MCK I2C0_SCL(1), I2C1_SCL(2) I2C0_SDA(1), I2C1_SDA(2) SPI0_NSS(1) PB12 EVENTOUT I2C1_SMBA SPI1_NSS(2) SPI0_SCK(1) PB13 SPI1_SCK(2) SPI0_MISO(1) PB14 SPI1_MISO(2) SPI0_MOSI(1) PB15 SPI1_MOSI(2) 1. This feature is available on GD32F350x4 devices only. 2. This feature is available on GD32F350xB, GD32F350x8 and GD32F350x6 devices only. 19 / 50 GD32F350xx Table 5. Port C alternate functions summary Pin Name AF0 PC0 EVENTOUT PC1 EVENTOUT PC2 EVENTOUT PC3 EVENTOUT PC4 EVENTOUT PC5 TSI_G2_IO0 PC6 TIMER2_CH0 PC7 TIMER2_CH1 PC8 TIMER2_CH2 PC9 TIMER2_CH3 AF1 AF2 AF3 AF4 AF5 AF6 I2S0_MCK PC10 PC11 PC12 PC13 PC14 PC15 Table 6. Port D alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 PD0 PD1 PD2 TIMER2_ETI PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 20 / 50 GD32F350xx Table 7. Port F alternate functions summary Pin Name PF0 AF0 AF1 AF2 AF3 AF4 AF5 AF6 CTC_SYNC PF1 PF2 PF3 PF4 EVENTOUT PF5 EVENTOUT PF6 PF7 I2C0_SCL(1) I2C1_SCL(2) I2C0_SDA(1) I2C1_SDA(2) PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 1. This feature is available on GD32F350x4 devices only. 2. This feature is available on GD32F350xB, GD32F350x8 and GD32F350x6 devices only. 21 / 50 GD32F350xx 3 Functional description 3.1 ARM® Cortex®-M4 core The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts. 32-bit ARM® Cortex®-M4 processor core  Up to 108 MHz operation frequency  Single-cycle multiplication and hardware divider  Integrated DSP instructions  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Memory Protection Unit (MPU)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 128 Kbytes of Flash memory  Up to 16 Kbytes of SRAM with hardware parity checking The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash and 16 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Figure 7. GD32F350xx memory map shows the memory map of the GD32F350xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 22 / 50 GD32F350xx 3.3 Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator  Internal 48 MHz RC oscillator  Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB and two APB domains is 108 MHz. See Figure 8 for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main Flash memory (default)  Boot from system memory  Boot from on-chip SRAM In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 in device mode. 23 / 50 GD32F350xx 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC8M is selected as the system clock.  Standby mode In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin. 3.6 Analog to digital converter (ADC)  12-bit SAR ADC's conversion rate is up to 2.6MSPS  12-bit, 10-bit, 8-bit or 6-bit configurable resolution  Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit  Input voltage range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor One 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for battery voltage (VBAT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the general-purpose level 0 timers (TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The 24 / 50 GD32F350xx temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value. 3.7 Digital to analog converter (DAC)  12-bit DAC converter of independent output channel  8-bit or 12-bit mode in conjunction with the DMA controller The 12-bit buffered DAC channel is used to generate variable analog outputs. The DAC is designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+. 3.8 DMA  7 channel DMA controller  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC and I2S The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9 General-purpose inputs/outputs (GPIOs)  Up to 55 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)  Analog input/output configurable  Alternate function input/output configurable There are up to 55 general purpose I/O pins (GPIO) in GD32F350xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 25 / 50 GD32F350xx 3.10 Timers and PWM generation  One 16-bit advanced-control timer (TM0), one 32-bit general-purpose timer (TM1), five 16-bit general-purpose timers (TM2, TM13 ~ TM16), and one 16-bit basic timer (TM5)  Up to 4 independent channels of PWM, output compare or input capture for each generalpurpose timer (GPTM) and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Independent watchdog and window watchdog) The advanced-control timer (TM0) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features. The general-purpose timer (GPTM) can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM1 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TM13 ~ TM16 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TM5, is mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F350xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It 26 / 50 GD32F350xx features: 3.11  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.  Calendar with subsecond, seconds, minutes, hours, week day, date, year and month automatically correction  Alarm function with wake up from deep-sleep and standby mode capability  On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy. The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator. 3.12 Inter-integrated circuit (I2C)  Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode, 400 kHz of the fast mode and 1 MHz of the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 27 / 50 GD32F350xx 3.13 Serial peripheral interface (SPI)  Up to two SPI interfaces with a frequency of up to 30 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14 Universal synchronous asynchronous receiver transmitter (USART)  Up to two USARTs with operating frequency up to 10.5 MBits/s  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication. 3.15 Inter-IC sound (I2S)  One I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with SPI1  Support either master or slave mode The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F350xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error. 28 / 50 GD32F350xx 3.16 HDMI CEC  Hardware support Consumer Electronics Control (CEC) protocol (HDMI standard rev1.4) The CEC protocol provides high-level control functions between the audiovisual products linked with HDMI cables. GD32F350xx contain a HDMI-CEC controller which has an independent clock domain and can wake up the MCU from deep-sleep mode on data reception. 3.17 Universal serial bus on-the-go full-speed (USB OTG FS)  One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s  Internal 48 MHz oscillator (IRC48M) support crystal-less operation  Internal main PLL for USB CLK compliantly  Internal USB OTG FS PHY support The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator (IRC48M) in automatic trimming mode that allows crystal-less operation. 3.18 Touch sensing interface (TSI)  Supports up to 18 external electrodes by the sensing channels distributed over 6 analog I/O groups  Programmable charging frequency and I/O pins  Capability to wake up the MCU from power saving modes Capacitive sensing technology can be used for the detection of a finger (or any conductive object) presence near an electrode. The capacitive variation of the electrode introduced by the finger can be measured by charging and detecting the voltage across the sampling capacitor. GD32F350xx contain a hardware touch sensing interface (TSI) and only requires few external components to operate. The sensing channels are distributed over 6 analog I/O groups including: Group1 (PA0 ~ PA3), Group2 (PA4 ~ PA7), Group3 (PC5, PB0 ~ PB2), Group4 (PA9 ~ PA12), Group5 (PB3, PB4, PB6,PA7) and Group6 (PB11 ~ PB14), 29 / 50 GD32F350xx 3.19 Comparators (CMP)  Two fast rail-to-rail low-power comparators with software configurable  Programmable reference voltage (internal, external I/O or DAC output pin) Two Comparators (CMP) are implemented within the devices. Both comparators can wake up from deep-sleep mode to generate interrupts and breaks for the timers and also can be combined as a window comparator. The internal voltage reference is also connected to ADC_IN17 input channel of the ADC. 3.20 Debug mode  Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.21 Package and operation temperature  LQFP64 (GD32F350Rx), LQFP48 (GD32F350Cx), QFN32 (GD32F350Kx) and QFN28 (GD32F350Gx)  Operation temperature range: -40°C to +85°C (industrial level) 30 / 50 GD32F350xx 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 8. Absolute maximum ratings Symbol Min Max Unit VDD External voltage range VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V Input voltage on 5V tolerant pin VSS - 0.3 VDD + 4.0 V Input voltage on other I/O VSS - 0.3 4.0 V Variations between different VDD power pins — 50 mV Variations between different ground pins — 50 mV IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C Storage temperature range -55 +150 °C Maximum junction temperature — 125 °C VIN |ΔVDDx| |VSSX −VSS| TSTG TJ 4.2 Parameter Recommended DC characteristics Table 9. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V 31 / 50 GD32F350xx 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 10. Power consumption characteristics Symbol Parameter Conditions Min Typ — 25.12 — mA — 19.04 — mA -— 19.86 — mA — 15.14 — mA — 13.22 — mA — 6.30 — mA — 117.06 — μA — 91.98 — μA VDD=VDDA=3.3V, LSE off, LSI on, RTC on — 7.83 — μA VDD=VDDA=3.3V, LSE off, LSI on, RTC off — 7.54 — μA VDD=VDDA=3.3V, LSE off, LSI off, RTC off — 6.85 — μA — 1.74 — μA — 1.59 — μA — 1.38 — μA — 1.07 — μA — 0.92 — μA — 0.72 — μA VDD=VDDA=3.3V, HSE=8MHz, System Max Unit clock=108 MHz, All peripherals enabled VDD=VDDA=3.3V, HSE=8MHz, System clock Supply current =108 MHz, All peripherals disabled (Run mode) VDD=VDDA=3.3V, HSE=8MHz, System clock =84 MHz, All peripherals enabled VDD=VDDA=3.3V, HSE=8MHz, System Clock =84 MHz, All peripherals disabled VDD=VDDA=3.3V, HSE=8MHz, CPU clock off, System clock =108 MHz, All peripherals IDD Supply current enabled (Sleep mode) VDD=VDDA=3.3V, HSE=8MHz, CPU clock off, System clock =108 MHz, All peripherals disabled VDD=VDDA=3.3V, Regulator in run mode, Supply current LSI on, RTC on, All GPIOs analog mode (Deep-Sleep VDD=VDDA=3.3V, Regulator in low power mode) under drive, LSI on, RTC on, All GPIOs analog mode Supply current (Standby mode) VDD not available, VBAT=3.6 V, LSE on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.3 V, LSE on with external crystal, RTC on, Higher driving VDD not available, VBAT=2.6 V, LSE on with IBAT Battery supply external crystal, RTC on, Higher driving current VDD not available, VBAT=3.6 V, LSE on with external crystal, RTC on, Lower driving VDD not available, VBAT=3.3 V, LSE on with external crystal, RTC on, Lower driving VDD not available, VBAT=2.6 V, LSE on with external crystal, RTC on, Lower driving 32 / 50 GD32F350xx 4.4 EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 11. EMS characteristics Symbol VESD Parameter Conditions Voltage applied to all device pins to VDD = 3.3 V, TA = +25 °C induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB Level/Class induce a functional disturbance through 100 pF on VDD and VSS pins 3B VDD = 3.3 V, TA = +25 °C 4A conforms to IEC 61000-4-4 EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 12. EMI characteristics Symbol Parameter Tested Conditions frequency band Peak level 72M 0.1 to 2 MHz