GigaDevice Semiconductor Inc.
GD32E103xx
ARM® Cortex™-M4 32-bit MCU
Datasheet
GD32E103xx Datasheet
Table of Contents
Table of Contents................................................................................................................... 1
List of Figures ........................................................................................................................ 3
List of Tables .......................................................................................................................... 4
1. General description ................................................................................................. 5
2. Device overview ....................................................................................................... 6
2.1.
Device information ...................................................................................................... 6
2.2.
Block diagram .............................................................................................................. 7
2.3.
Pinouts and pin assignment ....................................................................................... 8
2.4.
Memory map .............................................................................................................. 10
2.5.
Clock tree ................................................................................................................... 14
2.6.
Pin definitions ............................................................................................................ 14
2.6.1.
GD32E103Vx LQFP100 pin definitions .............................................................................. 14
2.6.2.
GD32E103Rx LQFP64 pin definitions ............................................................................... 21
2.6.3.
GD32E103Cx LQFP48 pin definitions ............................................................................... 25
2.6.4.
GD32E103Tx QFN36 pin definitions.................................................................................. 28
3. Functional description .......................................................................................... 31
3.1.
ARM® Cortex™-M4 core ............................................................................................ 31
3.2.
On-chip memory ........................................................................................................ 31
3.3.
Clock, reset and supply management ...................................................................... 32
3.4.
Boot modes ................................................................................................................ 32
3.5.
Power saving modes ................................................................................................. 33
3.6.
Analog to digital converter (ADC) ............................................................................ 33
3.7.
Digital to analog converter (DAC) ............................................................................. 34
3.8.
DMA ............................................................................................................................ 34
3.9.
General-purpose inputs/outputs (GPIOs) ................................................................ 34
3.10.
Timers and PWM generation ................................................................................. 35
3.11.
Real time clock (RTC) ............................................................................................ 36
3.12.
Inter-integrated circuit (I2C) .................................................................................. 36
3.13.
Serial peripheral interface (SPI) ............................................................................ 36
3.14.
Universal synchronous asynchronous receiver transmitter (USART) ............... 37
3.15.
Inter-IC sound (I2S) ................................................................................................ 37
1
GD32E103xx Datasheet
3.16.
Universal serial bus full-speed interface (USBFS) ............................................... 37
3.17.
Controller area network (CAN) .............................................................................. 38
3.18.
External memory controller (EXMC) ..................................................................... 38
3.19.
Debug mode ........................................................................................................... 38
3.20.
Package and operation temperature ..................................................................... 39
4. Electrical characteristics....................................................................................... 40
4.1.
Absolute maximum ratings ....................................................................................... 40
4.2.
Recommended DC characteristics ........................................................................... 40
4.3.
Power consumption .................................................................................................. 40
4.4.
EMC characteristics .................................................................................................. 42
4.5.
Power supply supervisor characteristics ................................................................ 43
4.6.
Electrical sensitivity .................................................................................................. 44
4.7.
External clock characteristics .................................................................................. 44
4.8.
Internal clock characteristics ................................................................................... 46
4.9.
PLL characteristics.................................................................................................... 47
4.10.
Memory characteristics ......................................................................................... 47
4.11.
GPIO characteristics .............................................................................................. 47
4.12.
ADC characteristics ............................................................................................... 49
4.13.
DAC characteristics ............................................................................................... 50
4.14.
I2C characteristics ................................................................................................. 51
4.15.
SPI characteristics ................................................................................................. 51
5. Package information.............................................................................................. 53
5.1.
QFN package outline dimensions ............................................................................ 53
5.2.
LQFP package outline dimensions........................................................................... 53
6. Ordering information ............................................................................................. 56
7. Revision history ..................................................................................................... 57
2
GD32E103xx Datasheet
List of Figures
Figure 2-1.GD32E103xx block diagram ..................................................................................................7
Figure 2-2. GD32E103Vx LQFP100 pinouts ...........................................................................................8
Figure 2-3. GD32E103Rx LQFP64 pinouts .............................................................................................9
Figure 2-3. GD32E103Cx LQFP48 pinouts .............................................................................................9
Figure 2-3. GD32E103Tx QFN36 pinouts ............................................................................................. 10
Figure 2-5. GD32E103xx clock tree ...................................................................................................... 14
Figure 5-1. QFN package outline .......................................................................................................... 53
Figure 5-1. LQFP package outline ........................................................................................................ 53
3
GD32E103xx Datasheet
List of Tables
Table 2-1.GD32E103xx devices features and peripheral list .................................................................6
Table 2-2. GD32E103xx memory map .................................................................................................. 10
Table 2-3. GD32E103Vx LQFP100 pin definitions ................................................................................ 14
Table 4-1. Absolute maximum ratings ................................................................................................. 40
Table 4-2. DC operating conditions...................................................................................................... 40
Table 4-3. Power consumption characteristics ................................................................................... 40
Table 4-4. EMS characteristics ............................................................................................................. 42
Table 4-5. EMI characteristics .............................................................................................................. 42
Table 4-6. Power supply supervisor characteristics ........................................................................... 43
Table 4-7. ESD characteristics ............................................................................................................. 44
Table 4-8. Static latch-up characteristics............................................................................................. 44
Table 4-9. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics ... 44
Table 5-1. QFN package dimensions ................................................................................................... 53
Table 5-2. LQFP package dimensions.................................................................................................. 54
Table 6-1. Part ordering code for GD32E103xx devices ...................................................................... 56
Table 7-1. Revision history ................................................................................................................... 57
4
GD32E103xx Datasheet
1.
General description
The GD32E103xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit
general-purpose microcontroller based on the ARM® Cortex™-M4 RISC core with best
cost-performance ratio in terms of enhanced processing capacity, reduced power
consumption and peripheral set. The Cortex™-M4 core features implements a full set of
DSP instructions to address digital signal control markets that demand an efficient,
easy-to-use blend of control and signal processing capabilities. It also provides powerful
trace technology for enhanced application security and advanced debug support.
The GD32E103xx device incorporates the ARM® Cortex®-M4 32-bit processor core
operating at 120 MHz frequency with Flash accesses zero wait states to obtain maximum
efficiency. It provides up to 128 KB on-chip Flash memory and 32 KB SRAM memory. An
extensive range of enhanced I/Os and peripherals connected to two APB buses. The
devices offer up to two 12-bit 3 MSPS ADCs, a 12-bit DAC, up to ten general 16-bit timers,
two 16-bit PWM advanced timers, and two 16-bit basic timers, as well as standard and
advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two
UARTs, two I2Ss, an USBFS and two CANs.
The device operates from a 1.8 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make GD32E103xx devices suitable for a wide range of interconnection
and advanced applications, especially in areas such as industrial control, motor drives,
consumer and handheld equipment, human machine interface, security and alarm systems,
POS, automotive navigation, IoT and so on.
5
GD32E103xx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1.GD32E103xx devices features and peripheral list
GD32E103xx
Timers
Part Number
T8
TB
C8
CB
R8
RB
V8
VB
Flash (KB)
64
128
64
128
64
128
64
128
SRAM (KB)
20
32
20
32
20
32
20
32
General
4
4
10
10
10
10
10
10
timer(16-bit)
(1-4)
(1-4)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
(1-4,8-13)
Advanced
1
1
1
1
2
2
2
2
timer(16-bit)
(0)
(0)
(0)
(0)
(0,7)
(0,7)
(0,7)
(0,7)
SysTick
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
(5,6)
Watchdog
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
2
2
3
3
3
3
3
3
(0-1)
(0-1)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
(0-2)
0
0
0
0
2
2
2
2
(3-4)
(3-4)
(3-4)
(3-4)
Basic timer(16-bit)
USART
Connectivity
UART
I2C
SPI
CAN
1
2
2
2
2
2
2
(0)
(0)
(0-1)
(0-1)
(0-1)
(0-1)
(0-1)
(0-1)
1/0
1/0
3/2
3/2
3/2
3/2
3/2
3/2
(0/-)
(0/-)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
(0-2)/(1-2)
2xFD
2xFD
2xFD
2xFD
2xFD
2xFD
2xFD 2xFD
1
1
1
1
1
1
1
1
GPIO
26
26
37
37
51
51
80
80
EXMC
0
0
0
0
0
0
1
1
EXTI
16
16
16
16
16
16
16
16
Units
2
2
2
2
2
2
2
2
Channels
10
10
10
10
16
16
16
16
USBFS
ADC
1
Package
QFN36
LQFP48
LQFP64
LQFP100
6
GD32E103xx Datasheet
2.2.
Block diagram
Figure 2-1.GD32E103xx block diagram
SW/JTAG
TPIU
NVIC
ICode DCode System
ARM Cortex-M4
Processor
Fmax:120MHz
POR/ PDR
Flash
Memory
Controller
Ibus
Flash
Memory
PLL
F max : 120MHz
Dbus
FMC
Master
Master
Slave
Slave
EXMC
CRC
LDO
1.2V
RCU
AHB Peripherals
Slave
AHB Matrix
DMA 12 chs
USBFS
SRAM
Controller
AHB to APB
Bridge2
IRC
8MHz
SRAM
HXTAL
4-32MHz
AHB to APB
Bridge1
Slave
LVD
Interrput request
CAN0
USART0
Slave
12-bit
SAR ADC
Slave
SPI0
WWDGT
ADC0~1
TIMER1~3
EXTI
SPI1~2
GPIOA
USART1~2
GPIOB
I2C0
Powered By V DDA
GPIOE
APB1: Fmax = 60MHZ
GPIOD
APB2: Fmax = 120MHz
GPIOC
Powered By VDDA
I2C1
FWDGT
RTC
DAC
TIMER4~6
TIMER0
UART3~4
TIMER7
CAN1
TIMER8~10
TIMER
11~13
CTC
7
GD32E103xx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32E103Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32IN
7
70
69
PA10
8
68
PA9
PC15-OSC32OUT
9
67
PA8
VSS_5
10
66
PC9
VDD_5
11
65
PC8
64
PC7
63
PC6
14
62
PD15
OSCIN
12
GigaDevice GD32E103Vx
LQFP100
VDD_2
PA11
OSCOUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
8
GD32E103xx Datasheet
Figure 2-3. GD32E103Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PD2
PC12
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PC14-OSC32IN
3
46
PA13
PC15-OSC32OUT
PD0-OSCIN
4
45
PA12
5
44
PA11
PD1 OSCOUT
6
43
PA10
NRST
PC0
7
42
PA9
PC1
9
PC2
PC3
VSSA
GigaDevice GD32E103Rx
LQFP64
41
PA8
40
PC9
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PB3
VSS_1
PB4
VDD_1
PB2
PB11
PB1
PB10
PB0
PB5
PC5
PC4
PA7
PA6
PA5
PA4
VDD_4
PA3
VSS_4
Figure 2-4. GD32E103Cx LQFP48 pinouts
PA14
PA15
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
48 47 46 45 44 43 42 41 40 39 38 37
1
36
VDD_2
PC13-TAMPER-RTC
2
35
VSS_2
PC14-OSC32IN
3
34
PA13
PC15-OSC32OUT
PD0-OSCIN
4
33
PA12
5
32
PA11
PD1-OSCOUT
NRST
VSSA
6
31
PA10
30
PA9
8
29
VDDA
9
28
PA8
PB15
PA0-WKUP
10
27
PB14
PA1
PA2
11
26
PB13
12
25
PB12
VBAT
GigaDevice GD32E103Cx
LQFP48
7
13 14 15 16 17 18 19 20 21 22 23 24
VSS_1
VDD_1
PB11
PB10
PB2
PB1
PA7
PB0
PA6
PA5
PA4
PA3
9
GD32E103xx Datasheet
Figure 2-5. GD32E103Tx QFN36 pinouts
PA14
PA15
PB3
PB4
36 35 34 33 32 31 30 29 28
1
27
2
26
VDD_2
3
25
PA13
24
5 GigaDevice GD32E103Tx 23
QFN36
6
22
7
21
PA12
PA9
8
PA8
4
VDDA
PA0-WKUP
PA1
20
9
19
10 11 12 13 14 15 16 17 18
PA2
VSS_2
PA11
PA10
VDD_1
VSS_1
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
2.4.
PB5
OSCOUT/PD1
NRST
VSSA
PB6
OSCIN/PD0
PB7
BOOT0
VSS_3
VDD_3
Memory map
Table 2-2. GD32E103xx memory map
Pre-defined
regions
Bus
External
device
AHB3
Address
Peripherals
0xA000 0000 - 0xA000 0FFF
EXMC - SWREG
0x9000 0000 - 0x9FFF FFFF
Reserved
0x7000 0000 - 0x8FFF FFFF
Reserved
External RAM
EXMC 0x6000 0000 - 0x63FF FFFF
NOR/PSRAM/SRA
M
Peripheral
AHB1
0x5000 0000 - 0x5003 FFFF
USBFS
0x4008 0000 - 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
Reserved
0x4002 BC00 - 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Reserved
0x4002 A000 - 0x4002 AFFF
Reserved
0x4002 8000 - 0x4002 9FFF
Reserved
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
Reserved
0x4002 6000 - 0x4002 63FF
Reserved
0x4002 5000 - 0x4002 5FFF
Reserved
10
GD32E103xx Datasheet
Pre-defined
regions
Bus
APB2
Address
Peripherals
0x4002 4000 - 0x4002 4FFF
Reserved
0x4002 3C00 - 0x4002 3FFF
Reserved
0x4002 3800 - 0x4002 3BFF
Reserved
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
Reserved
0x4002 2400 - 0x4002 27FF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1C00 - 0x4002 1FFF
Reserved
0x4002 1800 - 0x4002 1BFF
Reserved
0x4002 1400 - 0x4002 17FF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0C00 - 0x4002 0FFF
Reserved
0x4002 0800 - 0x4002 0BFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA1
0x4002 0000 - 0x4002 03FF
DMA0
0x4001 8400 - 0x4001 FFFF
Reserved
0x4001 8000 - 0x4001 83FF
Reserved
0x4001 7C00 - 0x4001 7FFF
Reserved
0x4001 7800 - 0x4001 7BFF
Reserved
0x4001 7400 - 0x4001 77FF
Reserved
0x4001 7000 - 0x4001 73FF
Reserved
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
Reserved
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
Reserved
0x4001 5400 - 0x4001 57FF
TIMER10
0x4001 5000 - 0x4001 53FF
TIMER9
0x4001 4C00 - 0x4001 4FFF
TIMER8
0x4001 4800 - 0x4001 4BFF
Reserved
0x4001 4400 - 0x4001 47FF
Reserved
0x4001 4000 - 0x4001 43FF
Reserved
0x4001 3C00 - 0x4001 3FFF
Reserved
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
TIMER7
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
11
GD32E103xx Datasheet
Pre-defined
regions
Bus
Address
Peripherals
0x4001 2000 - 0x4001 23FF
Reserved
0x4001 1C00 - 0x4001 1FFF
Reserved
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 C800 - 0x4000 CBFF
CTC
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
Reserved
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
CAN1
0x4000 6400 - 0x4000 67FF
CAN0
0x4000 6000 - 0x4000 63FF
APB1
CAN SRAM 1K
bytes
0x4000 5C00 - 0x4000 5FFF
Reserved
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIMER13
12
GD32E103xx Datasheet
Pre-defined
regions
SRAM
Bus
AHB
Address
Peripherals
0x4000 1C00 - 0x4000 1FFF
TIMER12
0x4000 1800 - 0x4000 1BFF
TIMER11
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x4000 0800 - 0x4000 0BFF
TIMER3
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x2007 0000 - 0x3FFF FFFF
Reserved
0x2006 0000 - 0x2006 FFFF
Reserved
0x2003 0000 - 0x2005 FFFF
Reserved
0x2002 0000 - 0x2002 FFFF
Reserved
0x2001 C000 - 0x2001 FFFF
0x2001 8000 - 0x2001 BFFF
0x2000 5000 - 0x2001 7FFF
SRAM
0x2000 0000 - 0x2000 4FFF
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF F000 - 0x1FFF F7FF
0x1FFF C010 - 0x1FFF EFFF
0x1FFF C000 - 0x1FFF C00F
Boot loader
0x1FFF B000 - 0x1FFF BFFF
Code
AHB
0x1FFF 7A10 - 0x1FFF AFFF
Reserved
0x1FFF 7800 - 0x1FFF 7A0F
Reserved
0x1FFF 0000 - 0x1FFF 77FF
Reserved
0x1FFE C010 - 0x1FFE FFFF
Reserved
0x1FFE C000 - 0x1FFE C00F
Reserved
0x1001 0000 - 0x1FFE BFFF
Reserved
0x1000 0000 - 0x1000 FFFF
Reserved
0x083C 0000 - 0x0FFF FFFF
Reserved
0x0830 0000 - 0x083B FFFF
Reserved
0x0810 0000 - 0x082F FFFF
0x0802 0000 - 0x080F FFFF
Main Flash
0x0800 0000 - 0x0801 FFFF
0x0030 0000 - 0x07FF FFFF
Reserved
0x0010 0000 - 0x002F FFFF
0x0002 0000 - 0x000F FFFF
Aliased to Main
Flash or Boot loader
0x0000 0000 - 0x0001 FFFF
13
GD32E103xx Datasheet
2.5.
Clock tree
Figure 2-6. GD32E103xx clock tree
CTC
CK_IRC48M
CK_CTC
48 MHz
IRC48M
48 MHz
CK48MSEL
USBFS
Prescaler
1,1.5,2,2.5
3,3.5,4
1
SCS[1:0]
CK_IRC8M
8 MHz
IRC8M
0
1
×2,3,4
…,31
PLL
CK_PLL
PLLPRESEL
1
4-32 MHz
HXTAL
0
PLLSEL
PREDV0
0
1
CK_USBFS
0
(to USBFS)
00
/2
CK_IRC48M
1
CK_AHB
120 MHz max
CK_EXMC
EXMC enable
(by hardware)
(to EXMC)
HCLK
01
PLLMF
/1,2,3…
15,16
AHB
Prescaler
÷1,2...512
CK_SYS
120 MHz max
10
AHB enable
(to AHB bus,Cortex-M4,SRAM,DMA,FMC)
CK_CST
Clock
Monitor
÷8
(to Cortex-M4 SysTick)
FCLK
PREDV0SEL
(free running clock)
CK_HXTAL
APB1
Prescaler
÷1,2,4,8,16
CK_APB1
PCLK1
to APB1 peripherals
60 MHz max
Peripheral enable
×8,9,10…,
14,16,20
PLL1
TIMER1,2,3,4,5,6,
11,12,13 if(APB1
prescale =1)x1
else x 2
CK_PLL1
×8,9,10…,
14,16,20
PLL2
PREDV1
0
CK_PLL2
x2
CK_I2S
1
APB2
Prescaler
÷1,2,4,8,16
CK_RTC
01
(to RTC)
10
RTCSRC[1:0]
40 KHz
IRC40K
CK_OUT0
00xx
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
TIMER0,7,8,9,10
if(APB2 prescale
=1)x1
else x 2
ADC
Prescaler
÷2,4,6,8,12,1
6
CK_FWDGT
(to FWDGT)
CK_APB2
PCLK2
to APB2 peripherals
120 MHz max
Peripheral enable
I2S1/2SEL
PLL2MF
11
32.768 KHz
LXTAL
to TIMER1,2,3,4,
5,6,11,12,13
PLL1MF
/1,2,3…
15,16
/128
CK_TIMERx
TIMERx
enable
ADC
Prescaler
÷3,5,7,9
CK_TIMERx
TIMERx
enable
to
TIMER0,7,8,9,10
ADCPSC[3]
0
1
CK_ADCx to ADC0,1
40 MHz max
NO CLK
CK_SYS
CK_IRC8M
CK_HXTAL
/2
CK_PLL
CK_PLL1
/2
CK_PLL2
CK_HXTAL
CK_PLL2
CK_IRC48M
/8
CK_IRC48M
CKOUT0SEL[3:0]
Legend:
HXTAL: 4 to 32 MHz High Speed crystal oscillator
LXTAL: 32,768 Hz Low Speed crystal oscillator
IRC8M: Internal 8 MHz RC oscillator
IRC40K: Internal 40 KHz RC oscillator
IRC48M: Internal 48 MHz RC oscillator
2.6.
Pin definitions
2.6.1.
GD32E103Vx LQFP100 pin definitions
Table 2-3. GD32E103Vx LQFP100 pin definitions
Pin Name Pins
Pin
Type
(1)
I/O
Level(2)
Functions description
14
GD32E103xx Datasheet
Pin Name Pins
Pin
Type
(1)
I/O
Functions description
Level(2)
PE2
1
I/O
5VT
PE3
2
I/O
5VT
PE4
3
I/O
5VT
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate: TRACED1, EXMC_A20
Default: PE5
PE5
4
I/O
5VT
Alternate: TRACED2, EXMC_A21
Remap: TIMER8_CH0
Default: PE6
PE6
5
I/O
5VT
Alternate:TRACED3, EXMC_A22
Remap:TIMER8_CH1
VBAT
6
P
-
7
I/O
-
8
I/O
-
9
I/O
-
VSS_5
10
P
-
Default: VSS_5
VDD_5
11
P
-
Default: VDD_5
OSCIN
12
I
-
OSCOUT
13
O
-
NRST
14
I/O
-
PC0
15
I/O
-
PC1
16
I/O
-
PC2
17
I/O
-
PC3
18
I/O
-
VSSA
19
P
-
Default: VSSA
VREF-
20
P
-
Default: VREF-
VREF+
21
P
-
Default: VREF+
VDDA
22
P
-
Default: VDDA
PC13TAMPERRTC
PC14OSC32IN
PC15OSC32O
UT
Default: VBAT
Default: PC13
Alternate: RTC_TAMPER
Default: PC14
Alternate:OSC32IN
Default: PC15
Alternate:OSC32OUT
Default: OSCIN
Remap:PD0
Default: OSCOUT
Remap:PD1
Default: NRST
Default: PC0
Alternate: ADC01_IN10
Default: PC1
Alternate: ADC01_IN11
Default: PC2
Alternate: ADC01_IN12
Default: PC3
Alternate: ADC01_IN13
15
GD32E103xx Datasheet
Pin Name Pins
PA0-WKU
P
Pin
Type
(1)
I/O
Functions description
Level(2)
Default: PA0
23
I/O
-
Alternate: WKUP, USART1_CTS, ADC01_IN0,
TIMER1_CH0_ETI, TIMER4_CH0, TIMER7_ETI
Default: PA1
PA1
24
I/O
-
Alternate: USART1_RTS, ADC01_IN1, TIMER4_CH1,
TIMER1_CH1
Default: PA2
PA2
25
I/O
-
Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2,
TIMER8_CH0, TIMER1_CH2, SPI0_IO2
Default: PA3
PA3
26
I/O
-
Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3,
TIMER1_CH3, TIMER8_CH1, SPI0_IO3
VSS_4
27
P
-
Default: VSS_4
VDD_4
28
P
-
Default: VDD_4
Default: PA4
PA4
29
I/O
-
Alternate: SPI0_NSS, USART1_CK, DAC_OUT0,
ADC01_IN4
Remap:SPI2_NSS, I2S2_WS
PA5
30
I/O
-
Default: PA5
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
31
I/O
-
Alternate: SPI0_MISO, TIMER7_BKIN, ADC01_IN6,
TIMER2_CH0, TIMER12_CH0
Remap:TIMER0_BKIN
Default: PA7
PA7
32
I/O
-
Alternate: SPI0_MOSI,TIMER7_CH0_ON, ADC01_IN7,
TIMER2_CH1, TIMER13_CH0
Remap:TIMER0_CH0_ON
PC4
33
I/O
-
PC5
34
I/O
-
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
35
I/O
-
Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
Remap:TIMER0_CH1_ON
Default: PB1
PB1
36
I/O
-
Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
Remap:TIMER0_CH2_ON
PB2
37
I/O
5VT
Default: PB2, BOOT1
16
GD32E103xx Datasheet
Pin Name Pins
Pin
Type
(1)
I/O
Functions description
Level(2)
Default: PE7
PE7
38
I/O
5VT
Alternate: EXMC_D4
Remap: TIMER0_ETI
Default: PE8
PE8
39
I/O
5VT
Alternate: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
PE9
40
I/O
5VT
Alternate: EXMC_D6
Remap:TIMER0_CH0
Default: PE10
PE10
41
I/O
5VT
Alternate: EXMC_D7
Remap:TIMER0_CH1_ON
Default: PE11
PE11
42
I/O
5VT
Alternate: EXMC_D8
Remap:TIMER0_CH1
Default: PE12
PE12
43
I/O
5VT
Alternate: EXMC_D9
Remap:TIMER0_CH2_ON
Default: PE13
PE13
44
I/O
5VT
Alternate: EXMC_D10
Remap:TIMER0_CH2
Default: PE14
PE14
45
I/O
5VT
Alternate: EXMC_D11
Remap:TIMER0_CH3
Default: PE15
PE15
46
I/O
5VT
Alternate: EXMC_D12
Remap:TIMER0_BKIN
Default: PB10
PB10
47
I/O
5VT
Alternate:I2C1_SCL, USART2_TX
Remap: TIMER1_CH2
Default: PB11
PB11
48
I/O
5VT
Alternate:I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
49
P
-
Default:VSS_1
VDD_1
50
P
-
Default:VDD_1
Default: PB12
PB12
51
I/O
5VT
Alternate:SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK,
TIMER0_BKIN, CAN1_RX
Default: PB13
PB13
52
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, USART2_CTS,
TIMER0_CH0_ON, CAN1_TX, I2C1_TXFRAME
17
GD32E103xx Datasheet
Pin Name Pins
Pin
Type
(1)
I/O
Functions description
Level(2)
Default: PB14
PB14
53
I/O
5VT
Alternate:SPI1_MISO, USART2_RTS, TIMER0_CH1_ON,
TIMER11_CH0
Default: PB15
PB15
54
I/O
5VT
Alternate:SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON,
TIMER11_CH11
Default: PD8
PD8
55
I/O
5VT
Alternate: EXMC_D13
Remap:USART2_TX
Default: PD9
PD9
56
I/O
5VT
Alternate: EXMC_D14
Remap:USART2_RX
Default: PD10
PD10
57
I/O
5VT
Alternate: EXMC_D15
Remap:USART2_CK
Default: PD11
PD11
58
I/O
5VT
Alternate: EXMC_A16
Remap:USART2_CTS
Default: PD12
PD12
59
I/O
5VT
Alternate: EXMC_A17
Remap:TIMER3_CH0, USART2_RTS
Default: PD13
PD13
60
I/O
5VT
Alternate: EXMC_A18
Remap:TIMER3_CH1
Default: PD14
PD14
61
I/O
5VT
Alternate: EXMC_D0
Remap:TIMER3_CH2
Default: PD15
PD15
62
I/O
5VT
Alternate: EXMC_D1
Remap:TIMER3_CH3, CTC_SYNC
Default: PC6
PC6
63
I/O
5VT
Alternate:I2S1_MCK, TIMER7_CH0
Remap:TIMER2_CH0
Default: PC7
PC7
64
I/O
5VT
Alternate:I2S2_MCK, TIMER7_CH1
Remap:TIMER2_CH1
Default: PC8
PC8
65
I/O
5VT
Alternate:TIMER7_CH2
Remap:TIMER2_CH2
18
GD32E103xx Datasheet
Pin Name Pins
Pin
Type
(1)
I/O
Functions description
Level(2)
Default: PC9
PC9
66
I/O
5VT
Alternate:TIMER7_CH3
Remap:TIMER2_CH3
Default: PA8
PA8
67
I/O
5VT
Alternate:USART0_CK, TIMER0_CH0, CK_OUT0, VCORE,
USBFS_SOF, CTC_SYNC
PA9
68
I/O
5VT
PA10
69
I/O
5VT
Default: PA9
Alternate:USART0_TX, TIMER0_CH1, USBFS_VBUS
Default: PA10
Alternate:USART0_RX, TIMER0_CH2, USBFS_ID, V1REF
Default: PA11
PA11
70
I/O
5VT
Alternate:USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
71
I/O
5VT
Alternate:USART0_RTS, CAN0_TX, USBFS_DP,
TIMER0_ETI
Default: JTMS, SWDIO
PA13
72
I/O
5VT
NC
73
-
-
-
VSS_2
74
P
-
Default: VSS_2
VDD_2
75
P
-
Default: VDD_2
PA14
76
I/O
5VT
PA15
77
I/O
5VT
Remap: PA13
Default: JTCK, SWCLK
Remap:PA14
Default: JTDI
Alternate:SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0_ETI, TIMER1_ETI, PA15, SPI0_NSS
Default: PC10
PC10
78
I/O
5VT
Alternate:UART3_TX
Remap:USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
79
I/O
5VT
Alternate:UART3_RX
Remap:USART2_RX, SPI2_MISO
Default: PC12
PC12
80
I/O
5VT
Alternate:UART4_TX
Remap:USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
81
I/O
5VT
Alternate:EXMC_D2
Remap: OSCIN, CAN0_RX
Default: PD1
PD1
82
I/O
5VT
Alternate:EXMC_D3
Remap: OSCOUT, CAN0_TX
19
GD32E103xx Datasheet
Pin Name Pins
PD2
83
Pin
Type
I/O
(1)
I/O
Functions description
Level(2)
5VT
Default: PD2
Alternate:TIMER2_ETI, UART4_RX
Default: PD3
PD3
84
I/O
5VT
Alternate: EXMC_CLK
Remap:USART1_CTS
Default:PD4
PD4
85
I/O
5VT
Alternate: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
86
I/O
5VT
Alternate: EXMC_NWE
Remap:USART1_TX
Default: PD6
PD6
87
I/O
5VT
Alternate: EXMC_NWAIT
Remap:USART1_RX
Default:PD7
PD7
88
I/O
5VT
Alternate:EXMC_NE0
Remap:USART1_CK
Default: JTDO
PB3
89
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap:TIMER1_CH1, PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
90
I/O
5VT
Alternate:SPI2_MISO, I2C0_TXFRAME
Remap:TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
91
I/O
-
Alternate:I2C0_SMBA, SPI2_MOSI, I2S2_SD
Remap:TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
92
I/O
5VT
Alternate:I2C0_SCL, TIMER3_CH0
Remap:USART0_TX, CAN1_TX, SPI0_IO2
Default: PB7
PB7
93
I/O
5VT
Alternate: I2C0_SDA, TIMER3_CH1, EXMC_NL(NADV)
Remap:USART0_RX, SPI0_IO3
BOOT0
94
I
-
Default: BOOT0
Default: PB8
PB8
95
I/O
5VT
Alternate:TIMER3_CH2, TIMER9_CH0
Remap:I2C0_SCL, CAN0_RX
Default: PB9
PB9
96
I/O
5VT
Alternate:TIMER3_CH3, TIMER10_CH0
Remap:I2C0_SDA, CAN0_TX
PE0
97
I/O
5VT
Default:PE0
Alternate:TIMER3_ETI, EXMC_NBL0
20
GD32E103xx Datasheet
Pin Name Pins
Pin
Type
I/O
(1)
Functions description
Level(2)
Default: PE1
PE1
98
I/O
5VT
VSS_3
99
P
-
Default: VSS_3
VDD_3
100
P
-
Default: VDD_3
Alternate:EXMC_NBL1
Notes:
2.6.2.
1.
Type: I= input, O = output, P = power.
2.
I/O Level: 5VT = 5V tolerant.
3.
Functions are available in GD32E103xx devices.
GD32E103Rx LQFP64 pin definitions
Pin
I/O
Pin Name
Pins
VBAT
1
P
-
2
I/O
-
3
I/O
-
4
I/O
-
OSCIN
5
I
-
OSCOUT
6
O
-
NRST
7
I/O
-
PC0
8
I/O
-
PC1
9
I/O
-
PC2
10
I/O
-
PC3
11
I/O
-
VSSA
12
P
-
Default: VSSA
VREF-
-
P
-
Default: VREF-
VREF+
-
P
-
Default: VREF+
VDDA
13
P
-
Default: VDDA
14
I/O
-
Type
(1)
PC13TAMPERRTC
PC14OSC32IN
PC15OSC32OU
T
PA0-WKU
P
Functions description
Level(2)
Default: VBAT
Default: PC13
Alternate: RTC_TAMPER
Default: PC14
Alternate:OSC32IN
Default: PC15
Alternate:OSC32OUT
Default: OSCIN
Remap:PD0
Default: OSCOUT
Remap:PD1
Default: NRST
Default: PC0
Alternate: ADC01_IN10
Default: PC1
Alternate: ADC01_IN11
Default: PC2
Alternate: ADC01_IN12
Default: PC3
Alternate: ADC01_IN13
Default: PA0
Alternate: WKUP, USART1_CTS, ADC01_IN0,
21
GD32E103xx Datasheet
Pin Name
Pins
Pin
Type
(1)
I/O
Functions description
Level(2)
TIMER1_CH0_ETI, TIMER4_CH0, TIMER7_ETI
Default: PA1
PA1
15
I/O
-
Alternate: USART1_RTS, ADC01_IN1, TIMER4_CH1,
TIMER1_CH1
Default: PA2
PA2
16
I/O
-
Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2,
TIMER8_CH0, TIMER1_CH2, SPI0_IO2
Default: PA3
PA3
17
I/O
-
Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3,
TIMER1_CH3, TIMER8_CH1, SPI0_IO3
VSS_4
18
P
-
Default: VSS_4
VDD_4
19
P
-
Default: VDD_4
Default: PA4
PA4
20
I/O
-
Alternate: SPI0_NSS, USART1_CK, DAC_OUT0,
ADC01_IN4
Remap:SPI2_NSS, I2S2_WS
PA5
21
I/O
-
Default: PA5
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
22
I/O
-
Alternate: SPI0_MISO, TIMER7_BKIN, ADC01_IN6,
TIMER2_CH0, TIMER12_CH0
Remap:TIMER0_BKIN
Default: PA7
PA7
23
I/O
-
Alternate: SPI0_MOSI,TIMER7_CH0_ON, ADC01_IN7,
TIMER2_CH1, TIMER13_CH0
Remap:TIMER0_CH0_ON
PC4
24
I/O
-
PC5
25
I/O
-
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
26
I/O
-
Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
Remap:TIMER0_CH1_ON
Default: PB1
PB1
27
I/O
-
Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
Remap:TIMER0_CH2_ON
PB2
28
I/O
5VT
Default: PB2, BOOT1
Default: PB10
PB10
29
I/O
5VT
Alternate:I2C1_SCL, USART2_TX
Remap: TIMER1_CH2
PB11
30
I/O
5VT
Default: PB11
22
GD32E103xx Datasheet
Pin Name
Pins
Pin
Type
(1)
I/O
Functions description
Level(2)
Alternate:I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
31
P
-
Default:VSS_1
VDD_1
32
P
-
Default:VDD_1
Default: PB12
PB12
33
I/O
5VT
Alternate:SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK,
TIMER0_BKIN, CAN1_RX
Default: PB13
PB13
34
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, USART2_CTS,
TIMER0_CH0_ON, CAN1_TX, I2C1_TXFRAME
Default: PB14
PB14
35
I/O
5VT
Alternate:SPI1_MISO, USART2_RTS, TIMER0_CH1_ON,
TIMER11_CH0
Default: PB15
PB15
36
I/O
5VT
Alternate:SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON,
TIMER11_CH11
Default: PC6
PC6
37
I/O
5VT
Alternate:I2S1_MCK, TIMER7_CH0
Remap:TIMER2_CH0
Default: PC7
PC7
38
I/O
5VT
Alternate:I2S2_MCK, TIMER7_CH1
Remap:TIMER2_CH1
Default: PC8
PC8
39
I/O
5VT
Alternate:TIMER7_CH2
Remap:TIMER2_CH2
Default: PC9
PC9
40
I/O
5VT
Alternate:TIMER7_CH3
Remap:TIMER2_CH3
Default: PA8
PA8
41
I/O
5VT
Alternate:USART0_CK, TIMER0_CH0, CK_OUT0, VCORE,
USBFS_SOF, CTC_SYNC
PA9
42
I/O
5VT
PA10
43
I/O
5VT
Default: PA9
Alternate:USART0_TX, TIMER0_CH1, USBFS_VBUS
Default: PA10
Alternate:USART0_RX, TIMER0_CH2, USBFS_ID, V1REF
Default: PA11
PA11
44
I/O
5VT
Alternate:USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
45
I/O
5VT
Alternate:USART0_RTS, CAN0_TX, USBFS_DP,
TIMER0_ETI
23
GD32E103xx Datasheet
Pin
I/O
Pin Name
Pins
PA13
46
I/O
5VT
VSS_2
47
P
-
Default: VSS_2
VDD_2
48
P
-
Default: VDD_2
PA14
49
I/O
5VT
Type
(1)
Functions description
Level(2)
Default: JTMS, SWDIO
Remap: PA13
Default: JTCK, SWCLK
Remap:PA14
Default: JTDI
PA15
50
I/O
5VT
Alternate:SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0_ETI, TIMER1_ETI, PA15, SPI0_NSS
Default: PC10
PC10
51
I/O
5VT
Alternate:UART3_TX
Remap:USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
52
I/O
5VT
Alternate:UART3_RX
Remap:USART2_RX, SPI2_MISO
Default: PC12
PC12
53
I/O
5VT
Alternate:UART4_TX
Remap:USART2_CK, SPI2_MOSI, I2S2_SD
PD2
54
I/O
5VT
Default: PD2
Alternate:TIMER2_ETI, UART4_RX
Default: JTDO
PB3
55
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap:TIMER1_CH1, PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
56
I/O
5VT
Alternate:SPI2_MISO, I2C0_TXFRAME
Remap:TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
57
I/O
-
Alternate:I2C0_SMBA, SPI2_MOSI, I2S2_SD
Remap:TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
58
I/O
5VT
Alternate:I2C0_SCL, TIMER3_CH0
Remap:USART0_TX, CAN1_TX, SPI0_IO2
Default: PB7
PB7
59
I/O
5VT
Alternate: I2C0_SDA, TIMER3_CH1
Remap:USART0_RX, SPI0_IO3
BOOT0
60
I
-
Default: BOOT0
Default: PB8
PB8
61
I/O
5VT
Alternate:TIMER3_CH2, TIMER9_CH0
Remap:I2C0_SCL, CAN0_RX
PB9
62
I/O
5VT
Default: PB9
Alternate:TIMER3_CH3, TIMER10_CH0
24
GD32E103xx Datasheet
Pin Name
Pin
Pins
Type
I/O
(1)
Functions description
Level(2)
Remap:I2C0_SDA, CAN0_TX
VSS_3
63
P
-
Default: VSS_3
VDD_3
64
P
-
Default: VDD_3
Notes:
2.6.3.
1.
Type: I= input, O = output, P = power.
2.
I/O Level:5VT = 5V tolerant.
3.
Functions are available in GD32E103xx devices.
GD32E103Cx LQFP48 pin definitions
Pin
I/O
Pin Name
Pins
VBAT
1
P
-
2
I/O
-
3
I/O
-
4
I/O
-
OSCIN
5
I
-
OSCOUT
6
O
-
NRST
7
I/O
-
Default: NRST
VSSA
8
P
-
Default: VSSA
VDDA
9
P
-
Default: VDDA
(1)
Type
PC13TAMPERRTC
PC14OSC32IN
PC15OSC32OUT
Functions description
Level(2)
Default: VBAT
Default: PC13
Alternate: RTC_TAMPER
Default: PC14
Alternate:OSC32IN
Default: PC15
Alternate:OSC32OUT
Default: OSCIN
Remap:PD0
Default: OSCOUT
Remap:PD1
Default: PA0
PA0-WKUP
10
I/O
-
Alternate: WKUP, USART1_CTS, ADC01_IN0,
TIMER1_CH0_ETI, TIMER4_CH0, TIMER7_ETI
Default: PA1
PA1
11
I/O
-
Alternate: USART1_RTS, ADC01_IN1, TIMER4_CH1,
TIMER1_CH1
Default: PA2
PA2
12
I/O
-
Alternate: USART1_TX, TIMER4_CH2, ADC01_IN2,
TIMER8_CH0, TIMER1_CH2, SPI0_IO2
Default: PA3
PA3
13
I/O
-
Alternate: USART1_RX, TIMER4_CH3, ADC01_IN3,
TIMER1_CH3, TIMER8_CH1, SPI0_IO3
PA4
14
I/O
-
Default: PA4
Alternate: SPI0_NSS, USART1_CK, DAC_OUT0,
25
GD32E103xx Datasheet
Pin Name
Pins
Pin
(1)
Type
I/O
Functions description
Level(2)
ADC01_IN4
Remap:SPI2_NSS, I2S2_WS
PA5
15
I/O
-
Default: PA5
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
16
I/O
-
Alternate: SPI0_MISO, TIMER7_BKIN, ADC01_IN6,
TIMER2_CH0, TIMER12_CH0
Remap:TIMER0_BKIN
Default: PA7
PA7
17
I/O
-
Alternate: SPI0_MOSI,TIMER7_CH0_ON, ADC01_IN7,
TIMER2_CH1, TIMER13_CH0
Remap:TIMER0_CH0_ON
Default: PB0
PB0
18
I/O
-
Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
Remap:TIMER0_CH1_ON
Default: PB1
PB1
19
I/O
-
Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
Remap:TIMER0_CH2_ON
PB2
20
I/O
5VT
Default: PB2, BOOT1
Default: PB10
PB10
21
I/O
5VT
Alternate:I2C1_SCL, USART2_TX
Remap: TIMER1_CH2
Default: PB11
PB11
22
I/O
5VT
Alternate:I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
23
P
-
Default:VSS_1
VDD_1
24
P
-
Default:VDD_1
Default: PB12
PB12
25
I/O
5VT
Alternate:SPI1_NSS, I2S1_WS, I2C1_SMBA,
USART2_CK,
TIMER0_BKIN, CAN1_RX
Default: PB13
PB13
26
I/O
5VT
Alternate: SPI1_SCK, I2S1_CK, USART2_CTS,
TIMER0_CH0_ON, CAN1_TX, I2C1_TXFRAME
Default: PB14
PB14
27
I/O
5VT
Alternate:SPI1_MISO, USART2_RTS,
TIMER0_CH1_ON, TIMER11_CH0
Default: PB15
PB15
28
I/O
5VT
Alternate:SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON,
TIMER11_CH11
PA8
29
I/O
5VT
Default: PA8
Alternate:USART0_CK, TIMER0_CH0, CK_OUT0,
26
GD32E103xx Datasheet
Pin Name
Pins
Pin
(1)
Type
I/O
Functions description
Level(2)
VCORE, USBFS_SOF, CTC_SYNC
PA9
30
I/O
5VT
Default: PA9
Alternate:USART0_TX, TIMER0_CH1, USBFS_VBUS
Default: PA10
PA10
31
I/O
5VT
Alternate:USART0_RX, TIMER0_CH2, USBFS_ID,
V1REF
Default: PA11
PA11
32
I/O
5VT
Alternate:USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
33
I/O
5VT
Alternate:USART0_RTS, CAN0_TX, USBFS_DP,
TIMER0_ETI
Default: JTMS, SWDIO
PA13
34
I/O
5VT
VSS_2
35
P
-
Default: VSS_2
VDD_2
36
P
-
Default: VDD_2
PA14
37
I/O
5VT
Remap: PA13
Default: JTCK, SWCLK
Remap:PA14
Default: JTDI
PA15
38
I/O
5VT
Alternate:SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0_ETI, TIMER1_ETI, PA15,
SPI0_NSS
Default: JTDO
PB3
39
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap:TIMER1_CH1, PB3, TRACESWO, SPI0_SCK
Default: NJTRST
PB4
40
I/O
5VT
Alternate:SPI2_MISO, I2C0_TXFRAME
Remap:TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
41
I/O
-
Alternate:I2C0_SMBA, SPI2_MOSI, I2S2_SD
Remap:TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
42
I/O
5VT
Alternate:I2C0_SCL, TIMER3_CH0
Remap:USART0_TX, CAN1_TX, SPI0_IO2
Default: PB7
PB7
43
I/O
5VT
Alternate: I2C0_SDA, TIMER3_CH1
Remap:USART0_RX, SPI0_IO3
BOOT0
44
I
-
Default: BOOT0
Default: PB8
PB8
45
I/O
5VT
Alternate:TIMER3_CH2, TIMER9_CH0
Remap:I2C0_SCL, CAN0_RX
27
GD32E103xx Datasheet
Pin Name
Pin
Pins
I/O
(1)
Functions description
Level(2)
Type
Default: PB9
PB9
46
I/O
5VT
Alternate:TIMER3_CH3, TIMER10_CH0
Remap:I2C0_SDA, CAN0_TX
VSS_3
47
P
-
Default: VSS_3
VDD_3
48
P
-
Default: VDD_3
Notes:
2.6.4.
1.
Type: I= input, O = output, P = power.
2.
I/O Level:5VT = 5V tolerant.
3.
Functions are available in GD32E103xx devices.
GD32E103Tx QFN36 pin definitions
Pin
I/O
Pin Name
Pins
OSCIN
2
I
-
OSCOUT
3
O
-
NRST
4
I/O
-
Default: NRST
VSSA
5
P
-
Default: VSSA
VDDA
6
P
-
Default: VDDA
PA0-WKUP
7
I/O
-
(1)
Type
Functions description
Level(2)
Default: OSCIN
Remap:PD0
Default: OSCOUT
Remap:PD1
Default: PA0
Alternate: WKUP, USART1_CTS, ADC01_IN0,
TIMER1_CH0_ETI, TIMER4_CH0, TIMER7_ETI
Default: PA1
PA1
8
I/O
-
Alternate: USART1_RTS, ADC01_IN1,
TIMER4_CH1, TIMER1_CH1
Default: PA2
PA2
9
I/O
-
Alternate: USART1_TX, TIMER4_CH2,
ADC01_IN2, TIMER8_CH0, TIMER1_CH2,
SPI0_IO2
Default: PA3
PA3
10
I/O
-
Alternate: USART1_RX, TIMER4_CH3,
ADC01_IN3, TIMER1_CH3, TIMER8_CH1,
SPI0_IO3
Default: PA4
PA4
11
I/O
-
Alternate: SPI0_NSS, USART1_CK, DAC_OUT0,
ADC01_IN4
PA5
12
I/O
-
PA6
13
I/O
-
Default: PA5
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
28
GD32E103xx Datasheet
Pin Name
Pins
Pin
(1)
Type
I/O
Functions description
Level(2)
Alternate: SPI0_MISO, TIMER7_BKIN,
ADC01_IN6, TIMER2_CH0, TIMER12_CH0
Remap:TIMER0_BKIN
Default: PA7
PA7
14
I/O
-
Alternate: SPI0_MOSI,TIMER7_CH0_ON,
ADC01_IN7, TIMER2_CH1, TIMER13_CH0
Remap:TIMER0_CH0_ON
Default: PB0
PB0
15
I/O
-
Alternate: ADC01_IN8, TIMER2_CH2,
TIMER7_CH1_ON
Remap:TIMER0_CH1_ON
Default: PB1
PB1
16
I/O
-
Alternate: ADC01_IN9, TIMER2_CH3,
TIMER7_CH2_ON
Remap:TIMER0_CH2_ON
PB2
17
I/O
5VT
Default: PB2, BOOT1
VSS_1
18
P
-
Default:VSS_1
VDD_1
19
P
-
Default:VDD_1
PA8
20
I/O
5VT
Default: PA8
Alternate:USART0_CK, TIMER0_CH0, CK_OUT0,
VCORE, USBFS_SOF, CTC_SYNC
Default: PA9
PA9
21
I/O
5VT
Alternate:USART0_TX, TIMER0_CH1,
USBFS_VBUS
Default: PA10
PA10
22
I/O
5VT
Alternate:USART0_RX, TIMER0_CH2, USBFS_ID,
V1REF
Default: PA11
PA11
23
I/O
5VT
Alternate:USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
24
I/O
5VT
Alternate:USART0_RTS, CAN0_TX, USBFS_DP,
TIMER0_ETI
Default: JTMS, SWDIO
PA13
25
I/O
5VT
VSS_2
26
P
-
Default: VSS_2
VDD_2
27
P
-
Default: VDD_2
PA14
28
I/O
5VT
PA15
29
I/O
5VT
Remap: PA13
Default: JTCK, SWCLK
Remap:PA14
Default: JTDI
Remap: TIMER1_CH0_ETI, TIMER1_ETI, PA15,
29
GD32E103xx Datasheet
Pin Name
Pins
Pin
(1)
Type
I/O
Functions description
Level(2)
SPI0_NSS
Default: JTDO
PB3
30
I/O
5VT
Remap:TIMER1_CH1, PB3, TRACESWO,
SPI0_SCK
Default: NJTRST
PB4
31
I/O
5VT
Alternate:I2C0_TXFRAME
Remap:TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
32
I/O
-
Alternate:I2C0_SMBA
Remap:TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
33
I/O
5VT
Alternate:I2C0_SCL, TIMER3_CH0
Remap:USART0_TX, CAN1_TX, SPI0_IO2
Default: PB7
PB7
34
I/O
5VT
Alternate: I2C0_SDA, TIMER3_CH1
Remap:USART0_RX, SPI0_IO3
BOOT0
35
I
-
Default: BOOT0
VSS_3
36
P
-
Default: VSS_3
VDD_3
1
P
-
Default: VDD_3
Notes:
1.
Type: I= input, O = output, P = power.
2.
I/O Level: 5VT = 5V tolerant.
3.
Functions are available in GD32E103xx devices.
30
GD32E103xx Datasheet
3.
Functional description
3.1.
ARM® Cortex™-M4 core
The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP
instructions which allow efficient signal processing and complex algorithm execution. It
brings an efficient, easy-to-use blend of control and signal processing capabilities to meet
the digital signal control markets demand. The processor is highly configurable enabling a
wide range of implementations from those requiring floating point operations, memory
protection and powerful trace technology to cost sensitive devices requiring minimal area,
while delivering outstanding computational performance and an advanced system response
to interrupts.
32-bit ARM® Cortex®-M4 processor core
Up to 120 MHz operation frequency
Single-cycle multiplication and hardware divider
Floating Point Unit (FPU)
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
3.2.
On-chip memory
Up to 128 Kbytes of Flash memory
Up to 32 KB of SRAM
The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 128 Kbytes of inner Flash at most,
which includes code Flash that available for storing programs and data, and accessed (R/W)
at CPU clock speed with zero wait states. An extra data Flash is also included for storing
data mainly. Table 2-2. GD32E103xx memory map shows the memory of the
31
GD32E103xx Datasheet
GD32E103xx series of devices, including Flash, SRAM, peripheral, and other pre-defined
regions.
3.3.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
1.8 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include internal RC oscillator and external crystal oscillator, high speed and low speed two
types. Several prescalers allow the frequency configuration of the AHB and two APB
domains. The maximum frequency of the two AHB domains are 120 MHz. The maximum
frequency of the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz. See
Figure 2-6. GD32E103xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the
processor core and peripheral IP components. Power-on reset (POR) and power-down reset
(PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The
device remains in reset mode when VDD is below a specified threshold. The embedded low
voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and
generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 1.8 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 1.8 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32.768 KHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM
In default condition, boot from main Flash memory is selected. The boot loader is located in
the internal boot ROM memory (system memory). It is used to reprogram the Flash memory
by using USART0 (PA9 and PA10).
32
GD32E103xx Datasheet
3.5.
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM
and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up
the system from the deep-sleep mode including the 16 external lines, the RTC alarm,
the LVD output, and USB wakeup. When exiting the deep-sleep mode, the IRC8M is
selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except
Backup Registers) are lost. There are four wakeup sources for the standby mode,
including the external reset from NRST pin, the RTC, the FWDG reset, and the rising
edge on WKUP pin.
3.6.
Analog to digital converter (ADC)
12-bit SAR ADC's conversion rate is up to 3 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VREF- to VREF+ (2.4 to 3.6 V)
Temperature sensor
Up to two 12-bit 3 MSPS multi-channel ADCs are integrated in the device. It has a total of 18
multiplexed channels: 16 external channels, 1 channel for internal temperature sensor
(VSENSE), 1 channel for internal reference voltage (VREFINT). The input voltage range is from
VREF- to VREF+. An on-chip hardware oversampling scheme improves performance while
off-loading the related computational burden from the CPU. An analog watchdog block can
be used to detect the channels, which are required to remain within a specific threshold
window. A configurable channel management block can be used to perform conversions in
single, continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMERx)
and the advanced timers (TIMER0 and TIMER7) with internal connection. The temperature
sensor can be used to generate a voltage that varies linearly with temperature. It is internally
33
GD32E103xx Datasheet
connected to the ADC_IN16 input channel which is used to convert the sensor output voltage
in a digital value.
3.7.
Digital to analog converter (DAC)
12-bit DAC with independent output channels
8-bit or 12-bit mode in conjunction with the DMA controller
The 12-bit buffered DAC is used to generate variable analog outputs. The DAC channels can
be triggered by the timer or EXTI with DMA support. In dual DAC channel operation,
conversions could be done independently or simultaneously. The maximum output value of
the DAC is VREF+.
3.8.
DMA
7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S
The flexible general-purpose DMA controllers provide a hardware method of transferring
data between peripherals and/or memory without intervention from the CPU, thereby freeing
up bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.9.
General-purpose inputs/outputs (GPIOs)
Up to 80 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 80 general purpose I/O pins (GPIO) in GD32E103xx, named PA0 ~ PA15,
PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15 and PE0 ~ PE15 to implement logic input/output
functions. Each of the GPIO ports has related control and configuration registers to satisfy
the requirements of specific applications. The external interrupts on the GPIO pins of the
device have related control and configuration registers in the Interrupt/event controller (EXTI).
The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum
flexibility on the package pins. Each of the GPIO pins can be configured by software as
output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as
peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current capable except for analog inputs.
34
GD32E103xx Datasheet
3.10.
Timers and PWM generation
Two 16-bit advanced timer (TIMER0 & TIMER7), ten 16-bit general timers (TIMER1 ~
TIMER4, TIMER8 ~ TIMER13), and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general
timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for
output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)
The advanced timer (TIMER0 & TIMER7) can be used as a three-phase PWM multiplexed
on 6 channels. It has complementary PWM outputs with programmable dead-time
generation. It can also be used as a complete general timer. The 4 independent channels
can be used for input capture, output compare, PWM generation (edge-aligned or
center-aligned counting modes) and single pulse mode output. If configured as a general
16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with
external signals or to interconnect with other general timers together which have the same
architecture and features.
The general timer, can be used for a variety of purposes including general time, input signal
pulse width measurement or output waveform generation such as a single pulse generation
or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 ~
TIMER4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER8 ~
TIMER13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general
timer also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TIMER5 &TIMER6, are mainly used for DAC trigger generation.
They can also be used as a simple 16-bit time base.
The GD32E103xx have two watchdog peripherals, free watchdog timer and window
watchdog timer. They offer a combination of high safety level, flexibility of use and timing
accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is
clocked from an independent 40 KHz internal RC and as it operates independently of the
main clock, it can operate in deep-sleep and standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free-running timer for
application timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early wakeup interrupt capability and the counter can be frozen in
debug mode.
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GD32E103xx Datasheet
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It
features:
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
3.11.
Real time clock (RTC)
32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
The real time clock is an independent timer which provides a set of continuously running
counters which can be used with suitable software to provide a clock calendar function, and
provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit
programmable counter for long-term measurement using the compare register to generate
an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.
3.12.
Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency
up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides several data transfer rates: up to 100 KHz of standard
mode, up to 400 KHz of the fast mode and up to 1 MHz of the fast mode plus. The I2C
module also has an arbitration detect function to prevent the situation where more than one
master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also
provided in I2C interface to perform packet error checking for I2C data.
3.13.
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 30 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
Quad-SPI configuration available in master mode (only in SPI0)
36
GD32E103xx Datasheet
SPI TI mode and NSS pulse mode supported
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including
simplex synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking.
3.14.
Universal synchronous asynchronous receiver transmitter
(USART)
Up to three USARTs and two UARTs with operating frequency up to 7.5MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface
The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data
exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232
standard communication. The USART/UART includes a programmable baud rate generator
which is capable of dividing the system clock to produce a dedicated clock for the USART
transmitter and receiver. The USART/UART also supports DMA function for high speed data
communication except UART4.
3.15.
Inter-IC sound (I2S)
Two I2S bus interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32E103xx contain two I2S-bus interfaces that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and
SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported.
3.16.
Universal serial bus full-speed interface (USBFS)
One full-speed USB Interface with frequency up to 12 Mbit/s
Internal 48 MHz oscillator support crystal-less operation
Internal main PLL for USB CLK compliantly
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device
controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction
37
GD32E103xx Datasheet
formatting is performed by the hardware, including CRC generation and checking. It supports
device modes. Transaction formatting is performed by the hardware, including CRC
generation and checking. The status of a completed USB transfer or error condition is
indicated by status registers. An interrupt is also generated if enabled. The required precise
48 MHz clock which can be generated from the internal main PLL (the clock source must use
an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode
that allows crystal-less operation.
3.17.
Controller area network (CAN)
Two CAN interface supports the CAN protocols version 2.0A, 2.0B, ISO11891-1:2015
and BOSCH CAN FD specification with communication frequency up to 1 Mbit/s of
classic frames and 6 Mbit/s of FD frames
Internal main PLL for CAN CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus.
The CAN protocol has been used extensively in industrial automation and automotive
applications. It can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and
two FIFOs of three message deep for reception. It also provides 28 scalable/configurable
identifier filter banks for selecting the incoming messages needed and discarding the others.
3.18.
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It is
divided in to several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
execution from external memory. The EXMC also can be configured to interface with the
most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system
cost and complexity.
3.19.
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The ARM®SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
38
GD32E103xx Datasheet
3.20.
Package and operation temperature
LQFP100 (GD32E103Vx), LQFP64 (GD32E103Rx) and LQFP48 (GD32E103Cx)
QFN36 (GD32E103Tx)
Operation temperature range: -40°C to +85°C (industrial level)
39
GD32E103xx Datasheet
4.
Electrical characteristics
4.1.
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without
permanently damaging the device. Note that the device is not guaranteed to operate
properly at the maximum ratings. Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4-1. Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
VDD
External voltage range
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5V tolerant pin
VSS - 0.3
VDD + 4.0
V
Input voltage on other I/O
VSS - 0.3
4.0
V
Maximum current for GPIO pins
—
25
mA
Injected current on 5V tolerant pin
—
±5
mA
Injected current on other I/O
—
±5
mA
∑IINJ
Injected current on all I/O
—
±25
mA
TA
Operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
IIO
IINJ
4.2.
Recommended DC characteristics
Table 4-2. DC operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Supply voltage
—
1.71
3.3
3.6
V
1.71
3.3
3.6
Analog supply voltage
VDDA
ADC not used
Analog supply voltage
—
ADC used
VBAT
4.3.
Battery supply voltage
—
V
2.4
3.3
3.6
1.71
-
3.6
V
Power consumption
The power measurements specified in the tables represent that code with data executing
from on-chip Flash with the following specifications.
Table 4-3. Power consumption characteristics
40
GD32E103xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD=VDDA=3.3V, HXTAL=25MHz, System
—
28.6
—
mA
—
14.9
—
mA
—
24.5
—
mA
—
13.0
—
mA
—
1.6
—
mA
—
1.2
—
mA
—
1.2
—
mA
—
1.0
—
mA
—
20.8
—
mA
—
7.0
—
mA
—
18.7
—
mA
—
6.5
—
mA
—
1.4
—
mA
—
0.9
—
mA
—
1.1
—
mA
—
0.9
—
mA
—
60
uA
48
uA
clock=120 MHz, All peripherals enabled
VDD=VDDA=3.3V, HXTAL=25MHz, System
clock =120 MHz, All peripherals disabled
VDD=VDDA=3.3V, HXTAL=25MHz, System
clock=108 MHz, All peripherals enabled
VDD=VDDA=3.3V, HXTAL=25MHz, System
Supply current
clock =108 MHz, All peripherals disabled
(Run mode)
VDD=VDDA=3.3V, HXTAL=4MHz, System
clock =4MHz, All peripherals enabled
VDD=VDDA=3.3V, HXTAL=4MHz, System
clock =4MHz, All peripherals disabled
VDD=VDDA=3.3V, HXTAL=2MHz, System
clock =2MHz, All peripherals enabled
VDD=VDDA=3.3V, HXTAL=2MHz, System
Clock =2 MHz, All peripherals disabled
VDD=VDDA=3.3V, HXTAL=25MHz, System
Clock =120 MHz, CPU clock off, All
peripherals enabled
VDD=VDDA=3.3V, HXTAL=25MHz, System
Clock =120 MHz, CPU clock off, All
peripherals disabled
IDD
VDD=VDDA=3.3V, HXTAL=25MHz, System
Clock =108 MHz, CPU clock off, All
peripherals enabled
VDD=VDDA=3.3V, HXTAL=25MHz, System
Clock =108 MHz, CPU clock off, All
Supply current
peripherals disabled
(Sleep mode)
VDD=VDDA=3.3V, HXTAL=4MHz, System
Clock =4 MHz, CPU clock off, All
peripherals enabled
VDD=VDDA=3.3V, HXTAL=4MHz, System
Clock =4 MHz, CPU clock off, All
peripherals disabled
VDD=VDDA=3.3V, HXTAL=2MHz, System
Clock =2 MHz, CPU clock off, All
peripherals enabled
VDD=VDDA=3.3V, HXTAL=2MHz, System
Clock =2 MHz, CPU clock off, All
peripherals disabled
Supply current
(Deep-Sleep
mode)
VDD=VDDA=3.3V, Regulator in run mode, All
GPIOs analog mode
VDD=VDDA=3.3V, Regulator in low power
mode, All GPIOs analog mode
41
GD32E103xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD=VDDA=3.3V, LDO off, IRC40K on, RTC
—
2.2
—
μA
—
2.0
—
uA
—
1.5
—
uA
—
1.5
—
μA
—
0.8
—
μA
on
Supply current VDD=VDDA=3.3V, LDO off, IRC40K on, RTC
(Standby mode)
off
VDD=VDDA=3.3V, LDO off, IRC40K off, RTC
off
VDD not available, VBAT=3.3V, LDO off,
Battery supply
IBAT
current (Backup
mode)
4.4.
LXTAL High drv , RTC on
VDD not available, VBAT=3.3V, LDO off,
LXTAL Low drv , RTC on
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the Table 4-4. EMS characteristics, based on the EMS levels and classes
compliant with IEC 61000 series standard.
Table 4-4. EMS characteristics
Symbol
VESD
Parameter
Conditions
Voltage applied to all device pins to
VDD = 3.3 V, TA = +25 °C
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VFTB
induce a functional disturbance through
100 pF on VDD and VSS pins
Level/Class
3B
VDD= 3.3 V, TA = +25 °C
4A
conforms to IEC 61000-4-4
EMI (Electromagnetic Interference) emission testing result is given in the Table 4-5. EMI
characteristics, compliant with IEC 61967-2 standard which specifies the test board and
the pin loading.
Table 4-5. EMI characteristics
Symbol
Parameter
Conditions
Peak level
frequency band
Unit
56M
72M
108M
0.1 to 2 MHz
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