74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 3 — 15 February 2019
Product data sheet
1. General description
The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches
featuring separate D-type inputs with bus hold (74LVCH16373A-Q100 only) for each latch and
3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable
(OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When
disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices
in mixed 3.3 V and 5 V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true outputs.
When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are
transparent, that is, the latch outputs change each time its corresponding D-input changes. The
latches store the information that was present at the D-inputs one set-up time (tsu) preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at
the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the
OE input does not affect the state of the latches. Bus hold on the data inputs eliminates the need
for external pull-up resistors to hold unused inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
•
•
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16373A-Q100 only)
High-impedance when VCC = 0 V
Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
• CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
74LVC16373ADGG-Q100
Temperature range Name
Description
Version
-40 °C to +125 °C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
-40 °C to +125 °C
TSSOP48 [1] plastic thin shrink small outline package;
48 leads; body width 4.4 mm;
lead pitch 0.4 mm
SOT480-1
74LVCH16373ADGG-Q100
74LVC16373ADGV-Q100
74LVCH16373ADGV-Q100
[1]
Also known as TVSOP48.
4. Functional diagram
1
1OE
24
1LE
1OE
2OE
2OE
47
1D0
1Q0
2
46
1D1
1Q1
3
44
1D2
1Q2
5
43
1D3
1Q3
6
41
1D4
1Q4
8
40
1D5
1Q5
9
38
1D6
1Q6
11
37
1D7
1Q7
12
36
2D0
2Q0
13
35
2D1
2Q1
14
2LE
1D0
1D1
1D2
1D3
33
2D2
2Q2
16
32
2D3
2Q3
17
30
2D4
2Q4
19
29
2D5
2Q5
20
27
2D6
2Q6
22
26
2D7
2Q7
23
1LE
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2LE
2D7
48
Fig. 1.
25
1EN
C3
24
2EN
25
C4
47
44
5
43
6
41
8
40
9
38
11
37
12
36
4D
35
13
2
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1Q0
Q
IEC logic symbol
2D0
LATCH
1
LE
3
mgu770
Fig. 2.
D
2
1
3D
46
mgu768
Logic symbol
1D0
1
48
D
2Q0
Q
LATCH
9
LE
LE
1LE
2LE
1OE
2OE
to 7 other channels
LE
to 7 other channels
mgu769
Fig. 3.
Logic diagram
74LVC_LVCH16373A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
2 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
VCC
data input
to internal circuit
mgu771
Fig. 4.
Bus hold circuit
5. Pinning information
5.1. Pinning
74LVC16373A-Q100
74LVCH16373A-Q100
1OE
1
48 1LE
1Q0
2
47 1D0
1Q1
3
46 1D1
GND
4
45 GND
1Q2
5
44 1D2
1Q3
6
43 1D3
VCC
7
42 VCC
1Q4
8
41 1D4
1Q5
9
40 1D5
GND 10
39 GND
1Q6 11
38 1D6
1Q7 12
37 1D7
2Q0 13
36 2D0
2Q1 14
35 2D1
GND 15
34 GND
2Q2 16
33 2D2
2Q3 17
32 2D3
VCC 18
31 VCC
2Q4 19
30 2D4
2Q5 20
29 2D5
GND 21
28 GND
2Q6 22
27 2D6
2Q7 23
26 2D7
2OE 24
25 2LE
aaa-013005
Fig. 5.
Pin configuration SOT362-1 (TSSOP48) and SOT480-1 (TSSOP48)
74LVC_LVCH16373A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
3 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1OE, 2OE
1, 24
output enable input (active LOW)
1LE, 2LE
48, 25
latch enable input (active HIGH)
GND
4, 10, 15, 21, 28, 34, 39, 45
ground (0 V)
VCC
7, 18, 31, 42
supply voltage
1Q0 to 1Q7
2, 3, 5, 6, 8, 9, 11, 12
data output
2Q0 to 2Q7
13, 14, 16, 17, 19, 20, 22, 23
data output
1D0 to 1D7
47, 46, 44, 43, 41, 40, 38, 37
data input
2D0 to 2D7
36, 35, 33, 32, 30, 29, 27, 26
data input
6. Functional description
Table 3. Function table
Per section of eight bits.
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition
Z = high-impedance OFF-state
Operating modes
Input
Internal latch
Output
nQ0 to nQ7
nOE
nLE
nDn
Enable and read register
(transparent mode)
L
H
L
L
L
L
H
H
H
H
Latch and read register
L
L
l
L
L
L
L
h
H
H
Latch register and disable outputs H
L
l
L
Z
H
L
h
H
Z
74LVC_LVCH16373A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
4 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
-0.5
+6.5
V
-50
-
-0.5
+6.5
V
-
±50
mA
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO > VCC or VO < 0
VO
output voltage
output HIGH or LOW state
[2]
-0.5
VCC + 0.5
V
output 3-state
[2]
-0.5
+6.5
V
-
±50
mA
VI < 0
[1]
IO
output current
ICC
supply current
-
100
mA
IGND
ground current
-100
-
mA
Tstg
storage temperature
-65
+150
°C
Ptot
total power dissipation
-
500
mW
[1]
[2]
[3]
VO = 0 V to VCC
mA
Tamb = -40 °C to +125 °C
[3]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
Above 60 °C, the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC
1.65
-
3.6
V
1.2
-
3.6
V
0
-
5.5
V
output HIGH or LOW state
0
-
VCC
V
output 3-state
0
-
5.5
V
°C
supply voltage
functional
VI
input voltage
VO
output voltage
Tamb
ambient temperature
in free air
-40
-
+125
Δt/ΔV
input transition rise and fall rate
VCC = 1.2 V to 2.7 V
0
-
20
ns/V
VCC = 2.7 V to 3.6 V
0
-
10
ns/V
74LVC_LVCH16373A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
5 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
Conditions
-40 °C to +85 °C
VCC = 1.2 V
VCC = 1.65 V to 1.95 V
-40 °C to +125 °C
Unit
Min
Typ [1]
Max
Min
Max
1.08
-
-
1.08
-
V
0.65VCC
-
-
0.65VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 1.2 V
-
-
0.12
-
0.12
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC - 0.2
-
-
VCC - 0.3
-
V
IO = -4 mA; VCC = 1.65 V
1.2
-
-
1.05
-
V
IO = -8 mA; VCC = 2.3 V
1.8
-
-
1.65
-
V
IO = -12 mA; VCC = 2.7 V
2.2
-
-
2.05
-
V
IO = -18 mA; VCC = 3.0 V
2.4
-
-
2.25
-
V
IO = -24 mA; VCC = 3.0 V
2.2
-
-
2.0
-
V
-
-
0.2
-
0.3
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
-
0.65
V
IO = 8 mA; VCC = 2.3 V
-
-
0.6
-
0.8
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
VI = VIH or VIL
HIGH-level
output voltage
IO = -100 μA;
VCC = 1.65 V to 3.6 V
VI = VIH or VIL
LOW-level
output voltage
IO = 100 μA;
VCC = 1.65 V to 3.6 V
0.35VCC V
II
input leakage VCC = 3.6 V;
current
VI = 5.5 V or GND
[2]
-
±0.1
±5
-
±20
μA
IOZ
OFF-state
VI = VIH or VIL; VCC = 3.6 V;
output current VO = 5.5 V or GND
[2]
-
±0.1
±5
-
±20
μA
IOFF
power-off
leakage
current
-
±0.1
±10
-
±20
μA
ICC
supply current VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.1
20
-
80
μA
ΔICC
additional
per input pin;
supply current VCC = 2.7 V to 3.6 V;
VI = VCC - 0.6 V; IO = 0 A
-
5
500
-
5000
μA
CI
input
capacitance
-
5.0
-
-
-
pF
74LVC_LVCH16373A_Q100
Product data sheet
VCC = 0 V; VI or VO = 5.5 V
VCC = 0 V to 3.6 V;
VI = GND to VCC
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
6 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
Typ [1]
Max
Min
Max
10
-
-
10
-
μA
30
-
-
25
-
μA
75
-
-
60
-
μA
-10
-
-
-10
-
μA
-30
-
-
-25
-
μA
-75
-
-
-60
-
μA
200
-
-
200
-
μA
300
-
-
300
-
μA
500
-
-
500
-
μA
-200
-
-
-200
-
μA
VCC = 2.7 V
-300
-
-
-300
-
μA
VCC = 3.6 V
-500
-
-
-500
-
μA
[3] [4]
VCC = 3.0; VI = 0.8 V
IBHH
VCC = 1.65; VI = 1.07 V
bus hold
HIGH current V = 2.3; V = 1.7 V
CC
I
[3] [4]
VCC = 3.0; VI = 2.0 V
IBHLO
IBHHO
[1]
[2]
[3]
[4]
[5]
bus hold LOW VCC = 1.95 V
overdrive
VCC = 2.7 V
current
VCC = 3.6 V
[3] [5]
VCC = 1.95 V
[3] [5]
bus hold
HIGH
overdrive
current
Unit
Min
bus hold LOW VCC = 1.65; VI = 0.58 V
current
VCC = 2.3; VI = 0.7 V
IBHL
-40 °C to +125 °C
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
Valid for data inputs (74LVCH16373A-Q100) only; control inputs do not have a bus hold circuit.
The specified sustaining current at the data inputs holds the input below the specified VI level.
The specified overdrive current at the data input forces the data input to the opposite logic input state.
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 10.
Symbol Parameter
tpd
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
-
12
-
-
-
ns
VCC = 1.65 V to 1.95 V
1.5
5.4
11.4
1.5
13.2
ns
VCC = 2.3 V to 2.7 V
1.0
2.9
5.7
1.0
6.6
ns
VCC = 2.7 V
1.5
2.9
4.9
1.5
6.5
ns
VCC = 3.0 V to 3.6 V
1.0
2.4
4.4
1.0
5.5
ns
-
14
-
-
-
ns
VCC = 1.65 V to 1.95 V
2.0
6.4
12.4
2.0
14.4
ns
VCC = 2.3 V to 2.7 V
1.5
3.4
6.1
1.5
7.1
ns
VCC = 2.7 V
1.5
3.0
5.3
1.5
7.0
ns
VCC = 3.0 V to 3.6 V
1.5
2.9
4.8
1.5
6.0
ns
-
18
-
-
-
ns
VCC = 1.65 V to 1.95 V
1.5
5.5
12.4
1.5
14.3
ns
VCC = 2.3 V to 2.7 V
1.0
3.1
6.6
1.0
7.6
ns
VCC = 2.7 V
1.5
3.3
5.7
1.5
7.5
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
4.9
1.0
6.5
ns
propagation delay Dn to Qn; see Fig. 6
[2]
VCC = 1.2 V
LE to Qn; see Fig. 7
VCC = 1.2 V
ten
enable time
OE to Qn; see Fig. 8
VCC = 1.2 V
74LVC_LVCH16373A_Q100
Product data sheet
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
7 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
Min
tdis
disable time
OE to Qn; see Fig. 8
pulse width
tsu
set-up time
th
hold time
Max
-
11
-
-
-
ns
2.8
4.5
9.1
2.8
10.5
ns
VCC = 2.3 V to 2.7 V
1.0
2.5
5.1
1.0
6.0
ns
VCC = 2.7 V
1.5
3.3
6.3
1.5
8.0
ns
VCC = 3.0 V to 3.6 V
1.5
3.1
5.4
1.5
7.0
ns
VCC = 1.65 V to 1.95 V
5.0
-
-
5.0
-
ns
VCC = 2.3 V to 2.7 V
4.0
-
-
4.0
-
ns
VCC = 2.7 V
3.0
-
-
3.0
-
ns
VCC = 3.0 V to 3.6 V
3.0
2.0
-
3.0
-
ns
VCC = 1.65 V to 1.95 V
3.0
-
-
3.0
-
ns
VCC = 2.3 V to 2.7 V
2.5
-
-
2.5
-
ns
VCC = 2.7 V
2.0
-
-
2.0
-
ns
VCC = 3.0 V to 3.6 V
2.0
1.0
-
2.0
-
ns
VCC = 1.65 V to 1.95 V
2.5
-
-
2.5
-
ns
VCC = 2.3 V to 2.7 V
2.0
-
-
2.0
-
ns
VCC = 2.7 V
0.9
-
-
0.9
-
ns
VCC = 3.0 V to 3.6 V
+0.9
-1.0
-
+0.9
-
ns
-
-
1.0
-
1.5
ns
VCC = 1.65 V to 1.95 V
-
10.8
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
13.0
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
15.0
-
-
-
pF
LE HIGH; see Fig. 7
Dn to LE; see Fig. 9
Dn to LE; see Fig. 9
output skew time
VCC = 3.0 V to 3.6 V
[3]
CPD
power dissipation
capacitance
per input; VI = GND to VCC
[4]
[3]
[4]
Min
VCC = 1.65 V to 1.95 V
tsk(o)
[1]
[2]
Max
[2]
VCC = 1.2 V
tW
Typ [1]
-40 °C to +125 °C Unit
Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
CPD is used to determine the dynamic power dissipation (PD in μW).
2
2
PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
2
Σ(CL × VCC × fo) = sum of the outputs
74LVC_LVCH16373A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
8 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
10.1. Waveforms and test circuit
VI
LE input
VM
t PHL
t PLH
VOH
t PHL
t PLH
VM
Qn output
VOH
VM
VOL
VM
VOL
mgu773
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that
occur with the output load.
mgu772
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that
occur with the output load.
Fig. 6.
VM
tW
VM
GND
Qn output
VM
GND
VI
Dn input
VM
Fig. 7.
Input (Dn) to output (Qn) propagation delays
Latch enable input (LE) pulse width, and the
latch enable input to output (Qn) propagation
delays
VI
OE input
VM
VM
GND
t PLZ
t PZL
VCC
Qn output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
VOH
Qn output
HIGH-to-OFF
OFF-to-HIGH
VY
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
mgu775
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 8.
3-state enable and disable times
VI
VM
Dn input
GND
t su
th
t su
th
VI
VM
LE input
GND
mgu774
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 9.
Data set-up and hold times for the Dn input to the LE input
74LVC_LVCH16373A_Q100
Product data sheet
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Nexperia B.V. 2019. All rights reserved
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Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
Table 8. Measurement points
Supply voltage
Input
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Output
VCC
VI
VM
VM
VX
VY
1.2 V
VCC
0.5 × VCC
0.5 × VCC
VOL + 0.15 V
VOH - 0.15 V
1.65 V to 1.95 V
VCC
0.5 × VCC
0.5 × VCC
VOL + 0.15 V
VOH - 0.15 V
2.3 V to 2.7 V
VCC
0.5 × VCC
0.5 × VCC
VOL + 0.15 V
VOH - 0.15 V
2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH - 0.3 V
3.0 V to 3.6 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH - 0.3 V
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
tf
tr
tr
VI
tf
90 %
positive
pulse
VM
VM
10 %
0V
tW
VEXT
VCC
G
VI
RL
VO
DUT
RT
CL
RL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 10. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
≤ 2 ns
30 pF
1 kΩ
open
2 × VCC
GND
1.65 V to 1.95 V
VCC
≤ 2 ns
30 pF
1 kΩ
open
2 × VCC
GND
2.3 V to 2.7 V
VCC
≤ 2 ns
30 pF
500 Ω
open
2 × VCC
GND
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
74LVC_LVCH16373A_Q100
Product data sheet
Load
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
10 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
11. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
HE
y
A
Z
48
25
Q
A2
A1
(A3)
pin 1 index
A
θ
Lp
1
L
24
bp
e
detail X
w
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
Unit
mm
max
nom
min
A
1.2
A1
A2
0.15 1.05
0.05 0.85
A3
0.25
bp
c
D(1)
E(2)
0.28
0.2
12.6
6.2
0.17
0.1
12.4
6.0
e
HE
0.5
8.3
7.9
L
1
Lp
Q
0.8
0.50
0.4
0.35
v
w
0.25 0.08
y
0.1
Z
θ
0.8
8°
0.4
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
Outline
version
SOT362-1
References
IEC
JEDEC
JEITA
sot362-1_po
European
projection
Issue date
03-02-19
13-08-05
MO-153
Fig. 11. Package outline SOT362-1 (TSSOP48)
74LVC_LVCH16373A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
11 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads;
body width 4.4 mm; lead pitch 0.4 mm
SOT480-1
E
D
A
X
c
y
HE
v M A
Z
25
48
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
detail X
1
24
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.85
0.25
0.23
0.13
0.20
0.09
9.8
9.6
4.5
4.3
0.4
6.6
6.2
1
0.7
0.5
0.4
0.3
0.2
0.07
0.08
0.4
0.1
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT480-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig. 12. Package outline SOT480-1 (TSSOP48)
74LVC_LVCH16373A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
12 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date
74LVC_LVCH16373A_Q100 v.3 20190215
Modifications:
•
•
•
•
Product data sheet
Product data sheet
-
74LVC_LVCH16373A_Q100 v.2
Product data sheet
-
74LVC_LVCH16373A_Q100 v.1
74LVC16373ADL-Q100 and 74LVCH16373ADL-Q100 removed.
74LVC_LVCH16373A_Q100 v.1 20140624
74LVC_LVCH16373A_Q100
Change notice Supersedes
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Type numbers 74LVC16373ADGV-Q100 and 74LVCH16373ADGV-Q100 added.
74LVC_LVCH16373A_Q100 v.2 20140710
Modifications:
Data sheet status
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
-
©
Nexperia B.V. 2019. All rights reserved
13 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
14. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
This document contains data from
the preliminary specification.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Product [short]
data sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
74LVC_LVCH16373A_Q100
Product data sheet
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©
Nexperia B.V. 2019. All rights reserved
14 / 15
Nexperia
74LVC16373A-Q100;
74LVCH16373A-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description............................................................. 4
6. Functional description................................................. 4
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................6
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 9
11. Package outline........................................................ 11
12. Abbreviations............................................................ 13
13. Revision history........................................................13
14. Legal information......................................................14
©
Nexperia B.V. 2019. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 15 February 2019
74LVC_LVCH16373A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 February 2019
©
Nexperia B.V. 2019. All rights reserved
15 / 15
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