74LVC8T595PWJ

74LVC8T595 Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 1 — 9 May 2017 1 Product data sheet General description The 74LVC8T595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 5.5 V making the device suitable for translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins MR, SHCP, STCP, OE, DS and Q7S are referenced to VCC(A) and pins Qn are referenced to VCC(B). The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when VCC(A) is at GND level, the Qn outputs are in the high-impedance OFF-state. 2 Features and benefits • Wide supply voltage range: – VCC(A): 1.1 V to 5.5 V – VCC(B): 1.1 V to 5.5 V • High noise immunity • Complies with JEDEC standards: – JESD8-12A (1.1 V to 1.3 V) – JESD8-11A (1.4 V to 1.6 V) – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8C (3.0 V to 3.6 V) – JESD12-6 (4.5 V to 5.5 V) • ESD protection: – HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4000V – CDM JESD22-C101E exceeds 1000 V • Suspend mode • Latch-up performance exceeds 100 mA per JESD 78 Class II • ±24 mA output drive (VCC(A) = VCC(B) = 3.0 V) • Inputs accept voltages up to 5.5 V • IOFF circuitry provides partial Power-down mode operation • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC8T595PW -40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVC8T595BQ -40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 4 Functional diagram VCC(A) 16 17 SHCP STCP Q7S Q0 Q1 19 Q2 DS Q3 Q4 Q5 Q5 Q7 MR 15 14 2 19 DS 16 SHCP 15 MR 8-STAGE SHIFT REGISTER 3 4 5 Q7S 17 STCP 18 OE 8-BIT STORAGE REGISTER 6 7 8 3-STATE OUTPUTS VCC(B) 9 OE 18 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 6 3 4 aaa-026283 Figure 1. Logic symbol 74LVC8T595 Product data sheet 14 5 7 8 9 aaa-026284 Figure 2. Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 2 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state VCC(A) STAGE 0 DS D STAGES 1 TO 6 Q D STAGE 7 Q D FF0 Q Q7S FF7 CP R CP R SHCP MR D Q D FF8 Q FF15 CP CP STCP OE VCC(B) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 aaa-026285 Figure 3.  Logic diagram SHCP DS STCP MR OE Z-state Q0 Z-state Q1 Z-state Q6 Z-state Q7 Q7S mna556 Figure 4.  Timing diagram 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 3 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 5 Pinning information 5.1 Pinning VCC(B) 1 terminal 1 index area 74LVC8T595 20 VCC(A) 74LVC8T595 Q0 2 19 DS Q1 3 18 OE Q2 4 17 STCP VCC(B) 1 20 VCC(A) Q0 2 19 DS Q1 3 18 OE Q3 5 16 SHCP 6 15 MR 17 STCP Q3 5 16 SHCP Q5 7 Q4 6 15 MR Q5 7 14 Q7S Q6 8 Q6 8 13 GND Q7 9 Q7 9 12 GND GND 10 11 GND 14 Q7S GND(1) 13 GND 12 GND GND 11 4 GND 10 Q2 Q4 aaa-026287 Transparent top view aaa-026286 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Figure 5. Pin configuration SOT360-1 (TSSOP20) Figure 6. Pin configuration SOT764-1 (DHVQFN20) 5.2 Pin description Table 2. Pin description Symbol Pin Description VCC(B) 1 supply voltage B (Qn outputs) Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 3, 4, 5, 6, 7, 8, 9 data output GND 10, 11, 12, 13 ground (0 V) Q7S 14 serial data output MR 15 master reset input (active LOW) SHCP 16 shift register clock input STCP 17 storage register clock input OE 18 output enable input (active LOW) DS 19 serial data input VCC(A) 20 supply voltage A (MR, SHCP, STCP, OE, DS inputs and Q7S output) 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 4 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 6 Functional description Table 3. Function table Supply voltage [1] Input Output Function VCC(A), VCC(B) SHCP STCP OE MR DS Q7S Qn 1.2 V to 5.5 V X X L L X L NC a LOW-state on MR only affects the shift register 1.2 V to 5.5 V X ↑ L L X L L empty shift register loaded into storage register 1.2 V to 5.5 V X X H L X L Z shift register clear; parallel outputs in highimpedance OFF-state 1.2 V to 5.5 V ↑ X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). 1.2 V to 5.5 V X ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages 1.2 V to 5.5 V ↑ ↑ L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages X X X X X X Z suspend mode GND [1] [2] [2] H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. When VCC(A) is at GND level, the device goes into suspend mode. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 5 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) Min Max Unit supply voltage A -0.5 +6.5 V VCC(B) supply voltage B -0.5 +6.5 V IIK input clamping current -50 - -0.5 +6.5 VI input voltage IOK output clamping current VO output voltage Conditions VI < 0 V [1] VO < 0 V -50 - -0.5 VCCO + 0.5 V Suspend or 3-state mode [1] -0.5 +6.5 V [2] - ±50 mA - 100 mA -100 - mA -65 +150 °C - 500 mW Active mode output current VO = 0 V to VCCO ICC supply current ICC(A) or ICC(B) IGND ground current Tstg storage temperature [1] [2] [3] [4] total power dissipation V [1] [2] [3] IO Ptot mA Tamb = -40 °C to +125 °C [4] mA The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output. VCCO + 0.5 V should not exceed 6.5 V For TSSOP20 package: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN20 package: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC(A) Min Max supply voltage A 1.1 5.5 V VCC(B) supply voltage B 1.1 5.5 V VI input voltage 0 5.5 V 0 VCCO V 0 5.5 V -40 +125 °C VCC(A) = 1.1 V to 1.3 V - 20 ns/V VCC(A) = 1.4 V to 1.95 V - 20 ns/V VCC(A) = 2.3 V to 2.7 V - 20 ns/V VCC(A) = 3 V to 3.6 V - 10 ns/V VCC(A) = 4.5 V to 5.5 V - 5 ns/V VO Conditions Active mode output voltage Suspend or 3-state mode Tamb ambient temperature Δt/ΔV input transition rise and fall rate [1] [1] Unit VCCO is the supply voltage associated with the output. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 6 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9 Static characteristics Table 6. Typical static characteristics at Tamb = 25 °C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL input leakage current MR, SHCP, STCP, OE and DS inputs; OFF-state output current Qn outputs; VO = 0 V or VCC(B) VOL II IOZ IOFF power-off leakage current Min Typ Max [1] - 1.09 - V [1] - 0.07 - V - - ±1 μA VCC(B) = 1.1 V to 5.5 V - - ±1 μA suspend mode; VCC(A) = 0 V; VCC(B) = 5.5 V - - ±1 μA - - ±1 μA - - ±1 μA - 3 - pF IO = -3 mA; VCCO = 1.2 V IO = 3 mA; VCCO = 1.2 V Unit VI = 0 V to 5.5 V; VCC(A) = 1.1 V to 5.5 V [1] inputs, Q7S output; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.1 V to 5.5 V Qn outputs; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.1 V to 5.5 V CI input capacitance MR, SHCP, STCP, OE and DS inputs; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V [1] VCCO is the supply voltage associated with the output. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 7 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH Conditions -40 °C to +85 °C Min Max Min Max Unit HIGH-level VCC(A) = 1.1 V to 1.3 V 0.65VCC(A) - 0.65VCC(A) - V input voltage VCC(A) = 1.4 V to 1.6 V 0.65VCC(A) - 0.65VCC(A) - V VCC(A) = 1.65 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCC(A) = 2.3 V to 2.7 V 1.7 - 1.7 - V VCC(A) = 3.0 V to 3.6 V 2.0 - 2.0 - V VCC(A) = 4.5 V to 5.5 V 0.7VCC(A) - 0.7VCC(A) - V LOW-level VCC(A) = 1.1 V to 1.3 V - 0.35VCC(A) - 0.35VCC(A) V input voltage VCC(A) = 1.4 V to 1.6 V - 0.35VCC(A) - 0.35VCC(A) V VCC(A) = 1.65 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V VCC(A) = 3.0 V to 3.6 V - 0.8 - 0.8 V VCC(A) = 4.5 V to 5.5 V - 0.3VCC(A) - VCCO - 0.1 - VCCO - 0.1 - V IO = -2 mA; VCCO = 1.1 V 0.825 - 0.825 - V IO = -6 mA; VCCO = 1.4 V 1.0 - 1.0 - V IO = -8 mA; VCCO = 1.65 V 1.2 - 1.2 - V IO = -12 mA; VCCO = 2.3 V 1.9 - 1.9 - V IO = -24 mA; VCCO = 3.0 V 2.4 - 2.4 - V IO = -24 mA; VCCO = 4.5 V 3.85 - 3.85 - V 3.8 - 3.8 - V IO = 100 μA; VCCO = 1.1 V to 4.5 V - 0.1 - 0.1 V IO = 2 mA; VCCO = 1.1 V - 0.275 - 0.275 V IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V IO = 24 mA; VCCO = 4.5 V - 0.50 - 0.50 V IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V HIGH-level output voltage LOW-level output voltage 74LVC8T595 Product data sheet 0.3VCC(A) V [1] VI = VIH IO = -100 μA; VCCO = 1.1 V to 4.5 V IO = -32 mA; VCCO = 4.5 V VOL -40 °C to +125 °C [1] VI = VIL All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 8 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter II IOZ -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max - ±2 - ±10 μA VCC(B) = 1.1 V to 5.5 V - ±2 - ±10 μA suspend mode; VCC(A) = 0 V; VCC(B) = 5.5 V - ±2 - ±10 μA - ±2 - ±10 μA - ±2 - ±10 μA VCC(A), VCC(B) = 1.1 V to 5.5 V - 2 - 5 μA VCC(A) = 5.5 V; VCC(B) = 0 V - 2 - 5 μA VCC(A) = 0 V; VCC(B) = 5.5 V -1 - -2 - μA VCC(A), VCC(B) = 1.1 V to 5.5 V - 9 - 24 μA VCC(B) = 5.5 V; VCC(A) = 0 V - 9 - 24 μA VCC(B) = 0 V; VCC(A) = 5.5 V -1 - -2 - μA MR, SHCP, STCP, OE inputs; one input at VCC(A) - 0.6 V; DS input at VCC(A) or GND; Qn = open - 50 - 75 μA DS input at VCC(A) - 0.6 V; Qn = open - 50 - 75 μA input leakage VI = 0 V to 5.5 V; current VCC(A) = 1.1 V to 5.5 V OFF-state Qn outputs; VO = 0 V or VCC(B) output current IOFF Conditions power-off inputs, Q7S output; leakage VI or VO = 0 V to 5.5 V; current VCC(A) = 0 V; VCC(B) = 1.1 V to 5.5 V Qn outputs; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.1 V to 5.5 V ICC supply current VCC(A) domain; VI = 0 V or VCC(A); IO = 0 A VCC(B) domain; VI = 0 V or VCC(A); IO = 0 A ΔICC [1] additional per input; supply current VCC(A), VCC(B) = 3.0 V to 5.5 V VCCO is the supply voltage associated with the output. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 9 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 10 Dynamic characteristics Table 8. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1] [2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter CPD [1] [2] Conditions VCC(A) and VCC(B) Unit 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V power dissipation inputs 31 31 32 33 36 43 pF capacitance outputs 105 104 103 101 99 98 pF CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL × VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of the outputs. fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13; for waveforms see Figure 7 up to Figure 12. Symbol Parameter Conditions VCC(A) 1.2 V ± 0.1 V Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V Min Typ Max Min Typ Max Min Typ Max 5.8 21.3 38.9 4.5 14.2 20.9 3.7 10.9 16.7 ns 14.7 ns Tamb = +25 °C; VCC(B) = 1.1 V to 5.5V [1] tpd propagation delay SHCP to Q7S tPHL HIGH to LOW MR to Q7S 5.9 22.7 42.1 4.5 14.8 18.9 3.7 11.2 SHCP, STCP 6.9 1.9 - 3.5 1.4 - 2.6 1.1 - ns MR LOW 12.4 3.5 - 5.6 2.1 - 3.9 1.5 - ns DS to SHCP 3.0 1.1 - 2.6 0.5 - 2.3 0.3 - ns MR to STCP 15.5 7.2 - 7.9 4.0 - 5.5 2.8 - ns SHCP to 13.5 5.4 - 6.5 3.0 - 4.9 2.1 - ns propagation delay tW pulse width HIGH or LOW tsu set-up time STCP th hold time DS to SHCP 3.0 ±0.4 - 2.0 ±0.2 - 1.5 ±0.1 - ns trec recovery time MR to SHCP 2.0 -0.4 - 1.5 -0.2 - 1.3 -0.2 - ns fmax maximum frequency SHCP 45 73 - 75 99 - 90 120 - MHz [1] tpd is the same as tPHL, tPLH. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 10 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 10. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13; for waveforms see Figure 7 up to Figure 12. Symbol Parameter Conditions VCC(A) 2.5 V ± 0.2 V Unit 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Typ Max Min Typ Max Min Typ Max 2.7 7.3 11.5 2.3 5.6 9.1 1.9 4.1 6.6 ns Tamb = +25 °C; VCC(B) = 1.1 V to 5.5V [1] tpd propagation delay SHCP to Q7S tPHL HIGH to LOW MR to Q7S 2.9 7.4 10.0 2.4 5.7 7.9 2.1 4.4 6.1 ns SHCP, STCP 1.6 0.7 - 1.4 0.6 - 1.0 0.5 - ns MR LOW 2.5 1.0 - 1.6 0.8 - 1.4 0.6 - ns DS to SHCP 1.9 0.2 - 1.5 0.1 - 1.1 0.1 - ns MR to STCP 3.2 1.7 - 2.4 1.3 - 2.2 1.1 - ns SHCP to 2.8 1.2 - 1.9 0.9 - 1.4 0.6 - ns propagation delay tW pulse width HIGH or LOW tsu set-up time STCP th hold time DS to SHCP 1.5 ±0.1 - 1.0 ±0.1 - 1.0 ±0.1 - ns trec recovery time MR to SHCP 1.0 -0.1 - 1.0 -0.1 - 1.0 -0.1 - ns fmax maximum frequency SHCP 135 160 - 175 194 - 195 250 - MHz [1] tpd is the same as tPHL, tPLH. Table 11. Dynamic characteristics for temperature +25 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13; for waveforms see Figure 7 up to Figure 12. Symbol Parameter Conditions VCC(B) 1.2 V ± 0.1 V Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V Min Typ Max Min Typ Max Min Typ Max VCC(A) = 1.2 V ± 0.1 V tpd propagation delay STCP to Qn 6.2 23.7 46.4 5.3 19.1 35.4 4.8 16.9 31.6 ns tdis disable time OE to Qn 3.6 12.7 25.1 3.0 9.7 15.6 3.1 9.0 14.4 ns ten enable time OE to Qn 5.8 20.9 40.0 4.6 15.1 26.2 3.9 12.6 21.7 ns fmax maximum frequency STCP 35 69 - 45 88 - 45 110 - tsk(o) output skew time - - 3.0 - - 2.3 - - 1.9 74LVC8T595 Product data sheet Q0 to Q7 [2] All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 MHz ns © Nexperia B.V. 2017. All rights reserved. 11 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter Conditions VCC(B) 1.2 V ± 0.1 V Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V Min Typ Max Min Typ Max Min Typ Max VCC(A) = 1.5 V ± 0.1 V tpd propagation delay STCP to Qn 5.7 20.2 32.1 4.9 15.5 23.3 4.3 13.3 20.0 ns tdis disable time OE to Qn 3.4 11.4 20.1 2.8 8.3 13.2 2.8 7.6 11.7 ns ten enable time OE to Qn 5.5 19.9 38.7 4.2 13.9 24.1 3.6 11.3 19.3 ns fmax maximum frequency STCP 45 73 - 70 95 - 90 120 - - - 2.7 - - 2.0 - - 1.7 tsk(o) output skew time [2] Q0 to Q7 MHz ns VCC(A) = 1.8 V ± 0.15 V tpd propagation delay STCP to Qn 5.4 18.7 30.3 4.5 14.0 21.4 4 11.8 18.3 ns tdis disable time OE to Qn 3.2 10.8 19.4 2.6 7.8 12.6 2.6 7.0 11.0 ns ten enable time OE to Qn 5.4 19.4 38.1 4.1 13.4 23.7 3.5 10.7 18.7 ns fmax maximum frequency STCP 45 75 - 70 98 - 90 125 - - - 2.7 - - 2.0 - - 1.6 tsk(o) output skew time [2] Q0 to Q7 MHz ns VCC(A) = 2.5 V ± 0.2 V tpd propagation delay STCP to Qn 5.1 17.3 28.3 4.2 12.6 19.5 3.6 10.4 16.3 ns tdis disable time OE to Qn 3.0 10.3 18.8 2.4 7.2 11.9 2.4 6.4 10.3 ns ten enable time OE to Qn 5.3 18.9 37.7 4.1 13.0 23.3 3.4 10.2 18.1 ns fmax maximum frequency STCP 45 76 - 70 100 - 90 128 - - - 2.6 - - 2.0 - - 1.6 tsk(o) output skew time [2] Q0 to Q7 MHz ns VCC(A) = 3.3 V ± 0.3 V tpd propagation delay STCP to Qn 4.9 16.7 27.6 4.0 12.0 18.7 3.4 9.8 15.4 ns tdis disable time OE to Qn 3.0 10.0 18.4 2.3 6.9 11.4 2.3 6.1 10.0 ns ten enable time OE to Qn 5.3 18.8 37.6 4.1 12.9 23.0 3.4 10.1 18.0 ns fmax maximum frequency STCP 45 76 - 70 101 - 90 130 - - - 2.6 - - 2.0 - - 1.6 tsk(o) output skew time [2] Q0 to Q7 MHz ns VCC(A) = 5.0 V ± 0.5 V tpd propagation delay STCP to Qn 4.8 16.1 27.5 3.9 11.4 18.0 3.3 9.2 14.8 ns tdis disable time OE to Qn 2.8 9.6 19.4 2.2 6.6 11.3 2.3 5.9 9.6 ten enable time OE to Qn 5.4 18.7 38.3 4.1 12.8 23.1 3.4 10.1 18.3 ns fmax maximum frequency STCP 45 77 - 70 102 - 90 132 - - - 2.7 - - 2.0 - - 1.6 tsk(o) [1] [2] output skew time Q0 to Q7 [2] ns MHz ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 12 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 12. Dynamic characteristics for temperature +25 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13; for waveforms see Figure 7 up to Figure 12. Symbol Parameter Conditions VCC(B) 2.5 V ± 0.2 V Unit 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Typ Max Min Typ Max Min Typ Max VCC(A) = 1.2 V ± 0.1 V tpd propagation delay STCP to Qn 4.2 14.5 27.9 3.8 13.4 26.3 3.5 12.4 24.9 ns tdis disable time OE to Qn 2.6 7.4 12.0 2.9 7.7 12.4 2.4 6.6 11.3 ns ten enable time OE to Qn 3.3 10.1 16.8 2.9 9.2 15.8 2.7 8.9 15.9 ns fmax maximum frequency STCP 45 131 - 45 139 - 45 144 - tsk(o) output skew time - - 1.4 - - 1.2 - - 1.0 [2] Q0 to Q7 MHz ns VCC(A) = 1.5 V ± 0.1 V tpd propagation delay STCP to Qn 3.7 10.9 16.2 3.3 9.7 14.5 3.0 8.7 13.0 ns tdis disable time OE to Qn 2.2 6.0 9.2 2.6 6.2 9.4 2.1 5.0 8.1 ten enable time OE to Qn 2.9 8.6 14.1 2.6 7.5 12.1 2.4 6.7 10.6 ns fmax maximum frequency STCP 130 144 - 130 187 - 130 224 - tsk(o) output skew time - - 1.2 - - 1.0 - - 0.7 [2] Q0 to Q7 ns MHz ns VCC(A) = 1.8 V ± 0.15 V tpd propagation delay STCP to Qn 3.4 9.4 14.4 3.0 8.2 12.6 2.7 7.2 10.9 ns tdis disable time OE to Qn 2.0 5.3 8.3 2.4 5.5 8.5 1.9 4.3 7.2 ns ten enable time OE to Qn 2.7 8.0 13.3 2.4 6.7 11.1 2.2 5.8 9.4 ns fmax maximum frequency STCP 130 151 - 165 197 - 205 237 - tsk(o) output skew time - - 1.2 - - 0.9 - - 0.7 ns [2] Q0 to Q7 MHz VCC(A) = 2.5 V ± 0.2 V tpd propagation delay STCP to Qn 3.0 7.9 12.4 2.6 6.7 10.5 2.3 5.7 8.8 ns tdis disable time OE to Qn 1.9 4.6 7.5 2.2 4.8 7.5 1.7 3.5 6.0 ns ten enable time OE to Qn 2.7 7.4 12.6 2.3 6.0 10.2 2.0 4.9 8.2 ns fmax maximum frequency STCP 130 156 - 165 210 - 215 252 - tsk(o) output skew time - - 1.2 - - 0.9 - - 0.7 ns [2] Q0 to Q7 MHz VCC(A) = 3.3 V ± 0.3 V tpd propagation delay STCP to Qn 2.8 7.3 11.5 2.4 6.1 9.6 2.1 5.0 7.9 ns tdis disable time OE to Qn 1.8 4.4 7.1 2.1 4.5 7.1 1.6 3.2 5.5 ns ten enable time OE to Qn 2.6 7.2 12.3 2.3 5.8 10.0 2.0 4.6 7.8 ns fmax maximum frequency STCP 130 159 - 165 213 - 215 255 - tsk(o) output skew time - - 1.2 - - 0.9 - - 0.7 74LVC8T595 Product data sheet Q0 to Q7 [2] All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 MHz ns © Nexperia B.V. 2017. All rights reserved. 13 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter Conditions VCC(B) 2.5 V ± 0.2 V Unit 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Typ Max Min Typ Max Min Typ Max VCC(A) = 5.0 V ± 0.5 V tpd propagation delay STCP to Qn 2.7 6.8 10.9 2.3 5.5 8.9 1.8 4.4 7.2 ns tdis disable time OE to Qn 1.7 4.1 6.8 2.0 4.3 6.7 1.4 2.9 5.1 ns ten enable time OE to Qn 2.7 7.2 12.4 2.3 5.8 10.0 2.0 4.6 7.7 ns fmax maximum frequency STCP 130 159 - 165 213 - 215 254 - - - 1.1 - - 0.9 - - 0.7 tsk(o) [1] [2] output skew time Q0 to Q7 [2] MHz ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 14 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 13. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13; for waveforms see Figure 7 up to Figure 12. Symbol Parameter Conditions VCC(A) Unit 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max Min Max 3.4 42.1 2.7 22.1 2.1 17.7 1.5 12.4 1.3 9.8 1.0 7.2 ns Tamb = -40 °C to +85 °C; VCC(B) = 1.1 V to 5.5V [1] tpd propagation delay SHCP to Q7S tPHL HIGH to LOW MR to Q7S 3.6 43.6 2.7 20.2 2.2 16.0 1.7 11.0 1.4 8.7 1.3 6.6 ns SHCP, STCP 7.8 - 4.8 - 3.3 - 2.0 - 1.7 - 1.3 - ns MR LOW 12.8 - 6.2 - 4.4 - 2.8 - 2.3 - 1.4 - ns DS to SHCP 4.5 - 3.0 - 2.6 - 2.3 - 1.9 - 1.5 - ns MR to STCP 16.5 - 9.1 - 6.1 - 3.6 - 2.9 - 2.3 - ns SHCP to 13.5 - 7.7 - 5.4 - 3.2 - 2.3 - 1.8 - ns propagation delay tW pulse width HIGH or LOW tsu set-up time STCP th hold time DS to SHCP 3.0 - 2.0 - 1.5 - 1.5 - 1.0 - 1.0 - ns trec recovery time MR to SHCP 2.2 - 1.7 - 1.5 - 1.2 - 1.2 - 1.2 - ns fmax maximum frequency SHCP 40 - 70 - 90 - 130 - 160 - 175 - MHz 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 15 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter Conditions VCC(A) Unit 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max Min Max 3.4 42.1 2.7 22.7 2.1 18.3 1.5 12.9 1.3 10.3 1.0 7.6 ns Tamb = -40 °C to +125 °C; VCC(B) = 1.1 V to 5.5V [1] tpd propagation delay SHCP to Q7S tPHL HIGH to LOW MR to Q7S 3.6 44.3 2.7 21.0 2.2 16.7 1.7 11.5 1.4 9.1 1.3 7.0 ns SHCP, STCP 8.4 - 5.3 - 3.8 - 2.5 - 1.9 - 1.4 - ns MR LOW 13.3 - 6.9 - 5.2 - 3.1 - 2.4 - 1.6 - ns DS to SHCP 4.5 - 3.0 - 2.6 - 2.3 - 1.9 - 1.5 - ns MR to STCP 16.5 - 9.5 - 6.8 - 4.2 - 3.1 - 2.4 - ns SHCP to 14.2 - 8.0 - 6.2 - 3.6 - 2.3 - 1.8 - ns propagation delay tW pulse width HIGH or LOW tsu set-up time STCP th hold time DS to SHCP 3.5 - 2.5 - 2.0 - 2.0 - 1.5 - 1.2 - ns trec recovery time MR to SHCP 2.4 - 1.9 - 1.7 - 1.4 - 1.4 - 1.4 - ns fmax maximum frequency SHCP 40 - 70 - 85 - 120 - 150 - 170 - MHz [1] tpd is the same as tPHL, tPLH. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 16 / 33 74LVC8T595 Nexperia Table 14. Dynamic characteristics for temperature range -40 °C to +85 °C Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13; for waveforms see Figure 7 up to Figure 12. Symbol Parameter Conditions VCC(B) Unit 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.2 V ± 0.1 V tpd propagation delay STCP to Qn 3.8 48.3 3.2 36.7 2.8 33.0 2.4 29.2 2.2 27.7 2.0 26.0 ns tdis disable time OE to Qn 2.1 26.6 1.8 17.2 1.8 15.8 1.5 13.1 1.8 13.4 1.4 12.3 ns ten enable time OE to Qn 3.5 42.1 2.7 27.0 2.2 22.6 1.9 18.0 1.7 17.0 1.6 17.2 ns fmax maximum frequency STCP 30 - 40 - 40 - 40 - 40 - 40 - tsk(o) output skew time - 3.5 - 2.5 - 2.0 - 1.5 - 1.2 - 1.0 ns Q0 to Q7 [2] MHz VCC(A) = 1.5 V ± 0.1 V tpd propagation delay STCP to Qn 3.5 34.2 2.9 25.6 2.5 22.4 2.1 18.5 1.9 16.8 1.7 15.1 ns tdis disable time OE to Qn 2.0 21.6 1.7 14.8 1.7 13.1 1.3 10.3 1.6 10.4 1.3 9.0 ns ten enable time OE to Qn 3.3 38.9 2.6 25.0 2.1 20.3 1.7 15.1 1.5 13.2 1.4 11.7 ns fmax maximum frequency STCP 40 - 65 - 80 - 105 - 105 - 105 - tsk(o) output skew time - 3.1 - 2.2 - 1.8 - 1.3 - 1.0 - 0.8 ns Q0 to Q7 [2] MHz VCC(A) = 1.8 V ± 0.15 V tpd propagation delay STCP to Qn 3.3 31.8 2.7 23.4 2.3 20.4 1.9 16.4 1.7 14.5 1.5 12.8 ns tdis disable time OE to Qn 1.9 20.9 1.5 14.2 1.6 12.4 1.2 9.4 1.4 9.4 1.1 8.0 ns ten enable time OE to Qn 3.3 38.6 2.4 24.5 2.0 19.7 1.6 14.4 1.4 12.1 1.3 10.5 ns fmax maximum frequency STCP 40 - 65 - 80 - 120 - 145 - 155 - tsk(o) output skew time - 3.1 - 2.2 - 1.8 - 1.2 - 1.0 - 0.8 74LVC8T595 Product data sheet Q0 to Q7 [2] All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 MHz ns © Nexperia B.V. 2017. All rights reserved. 17 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter Conditions VCC(B) Unit 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max Min Max VCC(A) = 2.5 V ± 0.2 V tpd propagation delay STCP to Qn 3.1 29.6 2.5 21.2 2.1 18.1 1.7 14.0 1.5 12.1 1.3 10.2 ns tdis disable time OE to Qn 1.8 20.2 1.4 13.2 1.4 11.6 1.1 8.5 1.3 8.3 1.0 6.6 ns ten enable time OE to Qn 3.2 37.7 2.4 24.0 2.0 19.1 1.5 13.5 1.3 11.1 1.2 9.0 ns fmax maximum frequency STCP 40 - 65 - 80 - 120 - 145 - 180 - - 3.1 - 2.2 - 1.8 - 1.2 - 1.0 - 0.7 ns tsk(o) output skew time Q0 to Q7 [2] MHz VCC(A) = 3.3 V ± 0.3 V tpd propagation delay STCP to Qn 3.0 29.1 2.4 20.3 2.0 17.2 1.6 13.0 1.4 11.0 1.2 9.1 ns tdis disable time OE to Qn 1.7 19.7 1.3 13.0 1.4 11.2 1.0 8.1 1.3 7.9 0.9 6.0 ns ten enable time OE to Qn 3.2 38.1 2.4 23.7 2.0 19.0 1.5 13.3 1.3 10.7 1.2 8.5 ns fmax maximum frequency STCP 40 - 65 - 80 - 120 - 145 - 190 - - 3.0 - 2.2 - 1.8 - 1.2 - 1.0 - 0.7 ns tsk(o) output skew time Q0 to Q7 [2] MHz VCC(A) = 5.0 V ± 0.5 V tpd propagation delay STCP to Qn 2.9 29.1 2.3 19.6 1.9 16.3 1.5 12.2 1.3 10.2 1.1 8.2 ns tdis disable time OE to Qn 1.6 20.6 1.3 12.6 1.3 10.9 0.9 7.7 1.2 7.5 0.8 5.6 ns ten enable time OE to Qn 3.3 38.9 2.5 23.8 2.0 19.1 1.6 13.3 1.4 10.6 1.2 8.3 ns fmax maximum frequency STCP 40 - 65 - 80 - 120 - 145 - 190 - - 3.0 - 2.2 - 1.7 - 1.2 - 0.9 - 0.7 tsk(o) [1] [2] output skew time Q0 to Q7 [2] MHz ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 18 / 33 74LVC8T595 Nexperia Table 15. Dynamic characteristics for temperature range -40 °C to +125 °C Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13; for waveforms see Figure 7 up to Figure 12. Symbol Parameter Conditions VCC(B) Unit 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.1 V to 1.3 V tpd propagation delay STCP to Qn 3.8 48.3 3.2 37.4 2.8 34.0 2.4 30.4 2.2 28.6 2.0 27.0 ns tdis disable time OE to Qn 2.1 27.6 1.8 18.0 1.8 16.5 1.5 13.7 1.8 14.1 1.4 12.8 ns ten enable time OE to Qn 3.5 42.1 2.7 27.6 2.2 23.2 1.9 18.6 1.7 17.8 1.6 18.0 ns fmax maximum frequency STCP 30 - 40 - 40 - 40 - 40 - 40 - tsk(o) output skew time - 3.6 - 2.6 - 2.1 - 1.5 - 1.3 - 1.0 ns Q0 to Q7 [2] MHz VCC(A) = 1.4 V to 1.6 V tpd propagation delay STCP to Qn 3.5 34.4 2.9 26.3 2.5 23.3 2.1 19.6 1.9 17.7 1.7 16.1 ns tdis disable time OE to Qn 2.0 22.7 1.7 15.7 1.7 14.0 1.3 11.0 1.6 11.0 1.3 9.5 ns ten enable time OE to Qn 3.3 38.9 2.6 25.5 2.1 20.8 1.7 15.8 1.5 13.8 1.4 12.3 ns fmax maximum frequency STCP 40 - 65 - 75 - 95 - 95 - 95 - tsk(o) output skew time - 3.1 - 2.2 - 1.8 - 1.3 - 1.0 - 0.8 ns Q0 to Q7 [2] MHz VCC(A) = 1.65 V to 1.95 V tpd propagation delay STCP to Qn 3.3 32.1 2.7 24.1 2.3 21.1 1.9 17.3 1.7 15.3 1.5 13.6 ns tdis disable time OE to Qn 1.9 21.9 1.5 14.9 1.6 13.2 1.2 10.1 1.4 10.0 1.1 8.4 ns ten enable time OE to Qn 3.3 38.6 2.4 24.8 2.0 20.3 1.6 14.9 1.4 12.7 1.3 11.0 ns fmax maximum frequency STCP 40 - 65 - 75 - 105 - 140 - 140 - tsk(o) output skew time - 3.1 - 2.2 - 1.8 - 1.2 - 1.0 - 0.8 74LVC8T595 Product data sheet Q0 to Q7 [2] All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 MHz ns © Nexperia B.V. 2017. All rights reserved. 19 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Symbol Parameter Conditions VCC(B) Unit 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max Min Max VCC(A) = 2.3 V to 2.7 V tpd propagation delay STCP to Qn 3.1 29.7 2.5 21.8 2.1 18.8 1.7 14.7 1.5 12.7 1.3 10.8 ns tdis disable time OE to Qn 1.8 21.2 1.4 14.2 1.4 12.4 1.1 9.1 1.3 8.8 1.0 7.0 ns ten enable time OE to Qn 3.2 37.7 2.4 24.4 2.0 19.7 1.5 14.1 1.3 11.6 1.2 9.4 ns fmax maximum frequency STCP 40 - 65 - 75 - 105 - 140 - 175 - - 3.1 - 2.2 - 1.8 - 1.2 - 1.0 - 0.7 ns tsk(o) output skew time Q0 to Q7 [2] MHz VCC(A) = 3.0 V to 3.6 V tpd propagation delay STCP to Qn 3.0 29.1 2.4 20.8 2.0 17.7 1.6 13.5 1.4 11.6 1.2 9.6 ns tdis disable time OE to Qn 1.7 20.9 1.3 13.8 1.4 12.1 1.0 8.7 1.3 8.3 0.9 6.4 ns ten enable time OE to Qn 3.2 38.1 2.4 24.3 2.0 19.5 1.5 13.7 1.3 11.2 1.2 8.9 ns fmax maximum frequency STCP 40 - 65 - 75 - 105 - 140 - 175 - - 3.0 - 2.2 - 1.8 - 1.2 - 1.0 - 0.7 ns tsk(o) output skew time Q0 to Q7 [2] MHz VCC(A) = 4.5 V to 5.5 V tpd propagation delay STCP to Qn 2.9 29.1 2.3 20.0 1.9 16.7 1.5 12.7 1.3 10.6 1.1 9.0 ns tdis disable time OE to Qn 1.6 21.7 1.3 13.6 1.3 11.7 0.9 8.3 1.2 7.9 0.8 6.0 ns ten enable time OE to Qn 3.3 38.9 2.5 24.3 2.0 19.5 1.6 13.8 1.4 11.0 1.2 8.6 ns fmax maximum frequency STCP 40 - 65 - 75 - 105 - 140 - 175 - - 3.0 - 2.2 - 1.7 - 1.2 - 0.9 - 0.7 tsk(o) [1] [2] output skew time Q0 to Q7 [2] MHz ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 20 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 10.1 Waveforms and test circuit 1/fmax VI SHCP input VM GND tW t PHL t PLH VOH VM Q7S output VOL mna557 Measurement points are given in Table 16. VOL and VOH are typical output voltage levels that occur with the output load. Figure 7.  The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency VI SHCP input VM GND 1/fmax t su VI STCP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna558 Measurement points are given in Table 16. VOL and VOH are typical output voltage levels that occur with the output load. Figure 8.  The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 21 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI VM SHCP input GND t su t su th th VI VM DS input GND VOH VM Q7S output VOL mna560 Measurement points are given in Table 16. VOL and VOH are typical output voltage levels that occur with the output load. Figure 9.  The data set-up and hold times for the serial data input (DS) VI MR input GND VI STCP input VM tsu VM GND VOH Qn outputs VM VOL 001aaf571 Measurement points are given in Table 16. VOL and VOH are typical output voltage levels that occur with the output load. Figure 10.  The master reset (MR) to storage clock (STCP) set-up time 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 22 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI VM MR input GND tW t rec VI SHCP input VM GND t PHL VOH VM Q7S output VOL mna561 Measurement points are given in Table 16. VOL and VOH are typical output voltage levels that occur with the output load. Figure 11.  The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time VI VM OE input GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH tPZH VY VM GND outputs enabled outputs enabled outputs disabled 001aae821 Measurement points are given in Table 16. VOL and VOH are typical output voltage drops that occur with the output load. Figure 12.  3-state enable and disable times Table 16. Measurement points Supply voltage Input Output VCC(A), VCC(B) VM VM (Qn) VM (Q7S) VX VY 1.1 V to 1.6 V 0.5VCC(A) 0.5VCC(B) 0.5VCC(A) VOL + 0.1 V VOH - 0.1 V 1.65 V to 2.7 V 0.5VCC(A) 0.5VCC(B) 0.5VCC(A) VOL + 0.15 V VOH - 0.15 V 3.0 V to 5.5 V 0.5VCC(A) 0.5VCC(B) 0.5VCC(A) VOL + 0.3 V VOH - 0.3 V 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 23 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr VI tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI G RL VO DUT RT CL RL 001aae331 Test data is given in Table 17 . RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Figure 13.  Test circuit for measuring switching times Table 17. Test data Supply voltage Input VCC(A), VCC(B) VI Δt/ΔV 1.1 V to 5.5 V VCC(A) ≤ 1.0 ns/V [1] Load [1] VEXT CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 15 pF 2 kΩ open GND 2VCC(B) dV/dt ≥ 1.0 V/ns 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 24 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 10.2 Typical propagation delay characteristics tPHL (ns) aaa-024634 30 25 (1) 20 (2) tPLH (ns) aaa-024633 30 (1) 25 (2) 20 (3) (3) (4) 15 (4) (5) 15 (5) (6) (6) 10 10 5 5 0 0 5 10 15 20 25 30 CL (pF) 0 35 0 5 10 15 20 25 30 CL (pF) a. HIGH to LOW propagation delay (STCP to Qn) b. LOW to HIGH propagation delay (STCP to Qn) (1) VCC(B) = 1.2 V (2) VCC(B) = 1.5 V (3) VCC(B) = 1.8 V (4) VCC(B) = 2.5 V (5) VCC(B) = 3.3 V (6) VCC(B) = 5.0 V 35 Figure 14. Typical propagation delay versus load capacitance; VCC(A) = 1.2 V; Tamb = 25 °C tPHL (ns) aaa-024636 30 tPLH (ns) 25 aaa-024635 30 25 (1) (1) 20 20 (2) (2) 15 (3) 15 (3) (4) (5) (4) (5) 10 10 (6) (6) 5 0 5 0 5 10 15 20 25 30 CL (pF) 35 0 0 5 10 15 20 25 30 CL (pF) a. HIGH to LOW propagation delay (STCP to Qn) b. LOW to HIGH propagation delay (STCP to Qn) (1) VCC(B) = 1.2 V (4) VCC(B) = 2.5 V (2) VCC(B) = 1.5 V (5) VCC(B) = 3.3 V (3) VCC(B) = 1.8 V (6) VCC(B) = 5.0 V 35 Figure 15. Typical propagation delay versus load capacitance; VCC(A) = 1.5 V; Tamb = 25 °C 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 25 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state tPHL (ns) aaa-024638 30 tPLH (ns) 25 aaa-024637 30 25 (1) (1) 20 20 (2) (2) 15 15 (3) (4) (5) 10 (3) (4) (5) (6) 10 (6) 5 0 5 0 5 10 15 20 25 30 CL (pF) 0 35 0 5 10 15 20 25 30 CL (pF) a. HIGH to LOW propagation delay (STCP to Qn) b. LOW to HIGH propagation delay (STCP to Qn) (1) VCC(B) = 1.2 V (4) VCC(B) = 2.5 V (2) VCC(B) = 1.5 V (5) VCC(B) = 3.3 V (3) VCC(B) = 1.8 V (6) VCC(B) = 5.0 V 35 Figure 16. Typical propagation delay versus load capacitance; VCC(A) = 1.8 V; Tamb = 25 °C tPHL (ns) aaa-024640 30 tPLH (ns) 25 aaa-024639 30 25 20 (1) 20 (1) 15 (2) 15 (2) (3) (3) 10 10 (4) (4) (5) (5) (6) 5 0 0 5 10 15 20 25 30 CL (pF) (6) 5 35 0 0 5 10 15 20 25 30 CL (pF) a. HIGH to LOW propagation delay (STCP to Qn) b. LOW to HIGH propagation delay (STCP to Qn) (1) VCC(B) = 1.2 V (4) VCC(B) = 2.5 V (2) VCC(B) = 1.5 V (5) VCC(B) = 3.3 V (3) VCC(B) = 1.8 V (6) VCC(B) = 5.0 V 35 Figure 17. Typical propagation delay versus load capacitance; VCC(A) = 2.5 V; Tamb = 25 °C 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 26 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state tPHL (ns) aaa-024642 30 tPLH (ns) 25 aaa-024641 30 25 20 (1) 15 (2) 20 (1) 15 (2) (3) (3) 10 (4) (5) (6) 5 0 10 0 5 10 15 20 25 30 CL (pF) (4) (5) (6) 5 0 35 0 5 10 15 20 25 30 CL (pF) a. HIGH to LOW propagation delay (STCP to Qn) b. LOW to HIGH propagation delay (STCP to Qn) (1) VCC(B) = 1.2 V (4) VCC(B) = 2.5 V (2) VCC(B) = 1.5 V (5) VCC(B) = 3.3 V (3) VCC(B) = 1.8 V (6) VCC(B) = 5.0 V 35 Figure 18. Typical propagation delay versus load capacitance; VCC(A) = 3.3 V; Tamb = 25 °C tPHL (ns) aaa-024644 30 tPLH (ns) 25 25 20 20 (1) 15 (3) (6) 0 5 10 15 20 25 30 CL (pF) (2) (3) 10 (4) (5) 5 (1) 15 (2) 10 0 aaa-024643 30 (4) (5) (6) 5 35 0 0 5 10 15 20 25 30 CL (pF) a. HIGH to LOW propagation delay (STCP to Qn) b. LOW to HIGH propagation delay (STCP to Qn) (1) VCC(B) = 1.2 V (4) VCC(B) = 2.5 V (2) VCC(B) = 1.5 V (5) VCC(B) = 3.3 V (3) VCC(B) = 1.8 V (6) VCC(B) = 5.0 V 35 Figure 19. Typical propagation delay versus load capacitance; VCC(A) = 5 V; Tamb = 25 °C 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 27 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 11 Package outline TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm D SOT360-1 E A X c HE y v M A Z 11 20 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Figure 20. Package outline SOT360-1 (TSSOP20) 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 28 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm B D SOT764-1 A A A1 E c detail X terminal 1 index area terminal 1 index area e1 C e b 2 9 v w C A B C y1 C y L 1 10 Eh e 20 11 19 12 X Dh 0 2.5 5 mm scale Dimensions (mm are the original dimensions) Unit mm A(1) A1 b max 1.00 0.05 0.30 nom 0.90 0.02 0.25 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 L v 0.2 4.6 4.5 4.4 3.15 3.00 2.85 2.6 2.5 2.4 1.15 1.00 0.85 0.5 3.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT764-1 --- MO-241 --- sot764-1_po European projection Issue date 03-01-27 14-12-12 Figure 21. Package outline SOT764-1 (DHVQFN20) 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 29 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 12 Abbreviations Table 18. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model 13 Revision history Table 19. Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC8T595 v.1 20170509 Product data sheet - - 74LVC8T595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 30 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74LVC8T595 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 31 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74LVC8T595 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1 — 9 May 2017 © Nexperia B.V. 2017. All rights reserved. 32 / 33 74LVC8T595 Nexperia Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 10.2 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 2 Functional diagram ............................................. 2 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 4 Functional description ........................................5 Limiting values .................................................... 6 Recommended operating conditions ................ 6 Static characteristics .......................................... 7 Dynamic characteristics ...................................10 Waveforms and test circuit .............................. 21 Typical propagation delay characteristics ........ 25 Package outline .................................................28 Abbreviations .................................................... 30 Revision history ................................................ 30 Legal information .............................................. 31 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 9 May 2017 Document identifier: 74LVC8T595