74HC40105D,652

74HC40105 4-bit x 16-word FIFO register Rev. 5 — 19 April 2019 Product data sheet 1. General description The 74HC40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The clock pulse transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have buffered outputs. All empty locations "bubble" automatically to the input end, and all valid data ripples through to the output end. As a result, the status of the first control flip-flop (data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop (data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest data is removed from the bottom of the data stack (output end), all data entered later will automatically ripple toward the output. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • • • Independent asynchronous inputs and outputs Expandable in either direction Reset capability Status indicators on inputs and outputs 3-state outputs CMOS input levels Complies with JEDEC standard JESD7A ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package 74HC40105D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC40105 Nexperia 4-bit x 16-word FIFO register 4. Functional diagram 1 1 [IR] 2 1Z2 OE 4 D0 Q0 13 5 D1 Q1 12 6 D2 Q2 11 7 D3 Q3 10 3 SI DOR 14 15 SO DIR 2 9 15 9 aaa-008736 Logic symbol 4 D0 5 D1 6 D2 7 D3 2 DIR 3 SI [OR] 5 2 14 CTR 3 1 (+/C4) CT = 0 CT < 16 G1 CT > 0 G3 33Z5 4 5 MR Fig. 1. FIFO 16 x 4 EN6 4D 6 13 12 6 11 7 10 aaa-008737 Fig. 2. IEC logic symbol 4 x 16 DATA REGISTER CONTROL LOGIC Q0 13 Q1 12 Q2 11 Q3 10 OE 1 DOR 14 SO 15 MR 9 Fig. 3. aaa-008738 Functional diagram 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 2 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register MR DOR SO SI (1) R (2) FF1 S R Q S (2) Q FF2 R Q (2) Q FF3 R Q S S (1) Q FF4 R Q FF5 Q S 14 x DIR OE CL D0 D1 CL CL 4 LATCHES D2 CL CL 4 LATCHES CL Q0 4 LATCHES 3-STATE OUTPUT BUFFER D3 Q1 Q2 Q3 position 1 position 2 to 15 position 16 aaa-008739 (1) LOW on S input of FF1 and FF5 sets Q output to HIGH independent of state on R input. (2) LOW on R input of FF2, FF3 and FF4 sets Q output to LOW independent of state on S input. Fig. 4. Logic diagram 5. Pinning information 5.1. Pinning 74HC40105 OE 1 16 VCC DIR 2 15 SO SI 3 14 DOR D0 4 13 Q0 D1 5 12 Q1 D2 6 11 Q2 D3 7 10 Q3 GND 8 9 MR aaa-008740 Fig. 5. Pin configuration SOT109-1 (SO16) 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 3 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 5.2. Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) DIR 2 data-in-ready output SI 3 shift-in input (LOW-to-HIGH, edge triggered) D0 to D3 4, 5, 6, 7 parallel data input GND 8 ground (0 V) MR 9 asynchronous master-reset input (active HIGH) Q0 to Q3 13, 12, 11, 10 data output DOR 14 data-out-ready output SO 15 shift-out input (HIGH-to-LOW, edge triggered) VCC 16 supply voltage 6. Functional description 6.1. Inputs and outputs Data inputs (D0 to D3) As there is no weighting of the inputs, any input can be assigned as the MSB. The size of the FIFO memory can be reduced from the 4 x 16 configuration. For example, it can be reduced to 3 x 16, down to 1 x 16, by tying unused data input pins to VCC or GND. Data outputs (Q0 to Q3) As there is no weighting of the outputs, any output can be assigned as the MSB. The size of the FIFO memory can be reduced from the 4 x 16 configuration as described for data inputs. In a reduced format, the unused data outputs pins must be left open circuit. Master-reset (MR) When MR is HIGH, the control functions within the FIFO are cleared, and date content is declared invalid. The data-in ready (DIR) flag is set HIGH and the data-out-ready (DOR) flag is set LOW. The output stage remains in the state of the last word that was shifted out, or in the random state existing at power-up. Status flag outputs (DIR, DOR) Two status flags, data-in-ready (DIR) and data-out-ready (DOR), indicate the status of the FIFO: 1. DIR = HIGH indicates that the input stage is empty and ready to accept valid data; 2. DIR = LOW indicates that the FIFO is full or that a previous shift-in operation is not complete (busy); 3. DOR = HIGH assures valid data is present at the outputs Q0 to Q3 (does not indicate that new data is awaiting transfer into the output stage); 4. DOR = LOW indicates that the output stage is busy or there is no valid data. 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 4 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Shift-in control (SI) Data is loaded into the input stage on a LOW-to-HIGH transition of SI. It also triggers an automatic data transfer process (ripple through). If SI is held HIGH during reset, data is loaded at the falling edge of the MR signal. Shift-out control (SO) A HIGH-to-LOW transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW transition of SO causes upstream data to move into the output stage, and empty locations to move towards the input stage (bubble-up). Output enable (OE) The outputs Q0 to Q3 are enabled when OE = LOW. When OE = HIGH the outputs are in the high impedance OFF-state. 6.2. Data input Following power-up, the master-reset (MR) input is pulsed HIGH to clear the FIFO memory (see Fig. 6). The data-in-ready flag (DIR = HIGH) indicates that the FIFO input stage is empty and ready to receive data. When DIR is valid (HIGH), data present at D0 to D3 can be shifted-in using the SI control input. With SI = HIGH, data is shifted into the input stage. DIR going LOW provides a busy indication. The data remains at the first location in the FIFO until DIR is set to HIGH and data moves through the FIFO to the output stage, or to the last empty location. If the FIFO is not full after the SI pulse, DIR again becomes valid (HIGH) to indicate that space is available in the FIFO. The DIR flag remains LOW if the FIFO is full (see Fig. 7). To complete the shift-in process, the SI use must be made LOW. With the FIFO full, SI can be held HIGH until a shift-out (SO) pulse occurs. Then, following a shift-out of data, an empty location appears at the FIFO input and DIR goes HIGH to allow the next data to be shifted-in. This data remains at the first FIFO location until SI goes LOW (see Fig. 8). 6.3. Data transfer After data has been transferred from the input stage of the FIFO following SI = LOW, data moves through the FIFO asynchronously and is stacked at the output end of the register. Empty locations appear at the input end of the FIFO as data moves through the device. 6.4. Data output The data-out-ready flag (DOR = HIGH) indicates that there is valid data at the output (Q0 to Q3). The initial master-reset at power-on (MR = HIGH) sets DOR to LOW (see Fig. 6). After MR = LOW, data shifted into the FIFO moves through to the output stage causing DOR to go HIGH. As the DOR flag goes HIGH, data can be shifted-out using the SO = HIGH, data in the output stage is shifted out. DOR going LOW provides a busy indication. When SO is made LOW, data moves through the FIFO to fill the output stage and an empty location appears at the input stage. When the output stage is filled DOR goes HIGH, but if the last of the valid data has been shifted-out leaving the FIFO empty the DOR flag remains LOW (see Fig. 10). With the FIFO empty, the last word that was shifted-out is latched at the output Q0 to Q3. With the FIFO empty, the SO input can be held HIGH until the SI control input is used. Following an SI pulse, data moves through the FIFO to the output stage, resulting in the DOR flag pulsing HIGH and a shift-out of data occurring. The SO control must be made LOW before additional data can be shifted-out (see Fig. 13). 6.5. High-speed burst mode Assuming the shift-in/shift-out pulses are not applied until the respective status flags are valid, it follows that the status flags determine the shift-in/shift-out rates. However, without the status flags, a high-speed burst can be implemented. In this mode, pulse widths determine the burst-in/burst-out 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 5 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register rates of the shift-in/shift-out inputs. Burst rates of 35 MHz can be obtained. Shift pulses can be applied without regard to the status flags but shift-in pulses that would overflow the storage capacity of the FIFO are not allowed (see Fig. 11 and Fig. 12). 6.6. Expanded format With the addition of a logic gate, the FIFO is easily expanded to increase word length (see Fig. 18). The basic operation and timing are identical to a single FIFO, except for an additional gate delay on the flag outputs. If during application, the following occurs: • SI is held HIGH when the FIFO is empty, some additional logic is required to produce a composite DIR pulse (see Fig. 8 and Fig. 19). Due to the part-to-part spread of the ripple through time, the SI signals of FIFO A and FIFO B do not always coincide. As a result, the AND-gate does not produce a composite flag signal. The solution is given in Fig. 19. The 74HC40105 is easily cascaded to increase the word capacity and no external components are needed. In the cascaded configuration, the FIFOs perform all necessary communications and timing. The minimum flag pulse widths and the flag delays determine the intercommunication speed. The data rate of cascaded devices is typically 25 MHz. Word-capacity can be expanded to and beyond 32-words x 4-bits (see Fig. 20). 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +7 V VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA IO output current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA ICC supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW Min Typ Max Unit 2.0 5.0 6.0 V [1] [2] [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 4. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions VCC supply voltage VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 6 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 9. Static characteristics Table 5. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Conditions 25 °C -40 °C to +85 °C Min Typ Max Min Max VCC = 2.0 V 1.5 1.2 VCC = 4.5 V 3.15 2.4 - 1.5 - 3.15 VCC = 6.0 V 4.2 3.2 - VCC = 2.0 V - 0.8 VCC = 4.5 V - VCC = 6.0 V -40 °C to +125 °C Unit Min Max - 1.5 - V - 3.15 - V 4.2 - 4.2 - V 0.5 - 0.5 - 0.5 V 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.15 0.26 - 0.33 - 0.4 V μA VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND;VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V - - ±0.5 - ±5.0 - ±10.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8 - 80 - 160 μA CI input capacitance - 3.5 - - - - - pF 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 7 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 10. Dynamic characteristics Table 6. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 17. Symbol Parameter tpd propagation delay Conditions 25 °C HIGH to LOW propagation delay LOW to HIGH propagation delay Max Min Max Min Max VCC = 2.0 V - 52 175 - 220 - 265 ns VCC = 4.5 V - 19 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 16 - - - - - ns VCC = 6.0 V - 15 30 - 37 - 45 ns VCC = 2.0 V - 116 400 - 500 - 600 ns VCC = 4.5 V - 42 80 - 100 - 120 ns VCC = 5 V; CL = 15 pF - 37 - - - - - ns VCC = 6.0 V - 34 68 - 85 - 102 ns VCC = 2.0 V - 52 210 - 265 - 315 ns VCC = 4.5 V - 19 42 - 53 - 63 ns VCC = 5 V; CL = 15 pF - 16 - - - - - ns VCC = 6.0 V - 15 36 - 45 - 54 ns VCC = 2.0 V - 55 210 - 265 - 315 ns VCC = 4.5 V - 20 42 - 53 - 63 ns VCC = 5 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 36 - 45 - 54 ns VCC = 2.0 V - 564 2000 - 2500 - 3000 ns VCC = 4.5 V - 205 400 - 500 - 600 ns VCC = 6.0 V - 165 340 - 425 - 510 ns VCC = 2.0 V - 701 2500 - 3125 - 3750 ns VCC = 4.5 V - 255 500 - 625 - 750 ns VCC = 6.0 V - 204 425 - 532 - 638 ns VCC = 2.0 V - 41 150 - 190 - 225 ns VCC = 4.5 V - 15 30 - 38 - 45 ns VCC = 6.0 V - 12 26 - 33 - 38 ns VCC = 2.0 V - 41 140 - 175 - 210 ns VCC = 4.5 V - 15 28 - 35 - 42 ns VCC = 6.0 V - 12 24 - 30 - 36 ns MR to DIR or DOR; see Fig. 6 SI to DOR; see Fig. 13 tdis enable time disable time 74HC40105 Product data sheet OE to Qn; see Fig. 15 OE to Qn; see Fig. 15 [1] [1] SI to DIR; see Fig. 7 SO to DIR; see Fig. 8 ten Unit Typ [1] SO to DOR; see Fig. 10 tPLH -40 °C to +125 °C Min SO to Qn; see Fig. 9 tPHL -40 °C to +85 °C [1] [1][2] [1][3] [4] [5] All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 8 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Symbol Parameter tt tW transition time pulse width Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 120 39 - 150 - 180 - ns VCC = 4.5 V 24 14 - 30 - 36 - ns VCC = 6.0 V 20 11 - 26 - 31 - ns VCC = 2.0 V 12 58 180 10 225 10 270 ns VCC = 4.5 V 6 21 36 5 45 5 54 ns VCC = 6.0 V 5 17 31 4 38 4 46 ns VCC = 2.0 V 12 55 170 10 215 10 255 ns VCC = 4.5 V 6 20 34 5 43 5 51 ns VCC = 6.0 V 5 16 29 4 37 4 43 ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 50 14 - 65 - 75 - ns VCC = 4.5 V 10 5 - 13 - 15 - ns VCC = 6.0 V 9 4 - 11 - 13 - ns VCC = 2.0 V -5 -39 - -5 - -5 - ns VCC = 4.5 V -5 -14 - -5 - -5 - ns VCC = 6.0 V -5 -11 - -5 - -5 - ns VCC = 2.0 V 125 44 - 155 - 190 - ns VCC = 4.5 V 25 16 - 31 - 38 - ns VCC = 6.0 V 21 13 - 26 - 32 - ns Qn; see Fig. 9 [6] SI HIGH or LOW; see Fig. 7 SO HIGH or LOW; see Fig. 10 DIR HIGH; see Fig. 8 DOR LOW; see Fig. 13 MR HIGH; see Fig. 6 trec tsu th recovery time set-up time hold time 74HC40105 Product data sheet MR to SI; see Fig. 14 Dn to SI; see Fig. 16 Dn to SI; see Fig. 16 All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 9 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Symbol Parameter fmax maximum frequency Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 3.6 10 - 2.8 - 2.4 - MHz VCC = 4.5 V 18 30 - 14 - 12 - MHz - 33 - - - - - MHz 21 36 - 16 - 14 - MHz VCC = 2.0 V 3.6 10 - 2.8 - 2.4 - MHz VCC = 4.5 V 18 30 - 14 - 12 - MHz VCC = 6.0 V 21 36 - 16 - 14 - MHz - 134 - - - - - pF SI, SO using flags or burst mode; see Fig. 7, Fig. 10, Fig. 11 and Fig. 12 VCC = 5 V; CL = 15 pF VCC = 6.0 V SI, SO cascaded; see Fig. 7 and Fig. 10 CPD [1] [2] [3] [4] [5] [6] [7] power dissipation capacitance VI = GND to VCC [7] tpd is the same as tPLH and tPHL. This is the ripple through delay. This is the bubble-up delay. ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 10 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 10.1. Waveforms and test circuit Master reset applied with FIFO full MR input (2) VM tPLH DIR output tW VM (3) (1) tPHL (4) DOR output VM aaa-008742 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. (1) DIR LOW; output ready HIGH; assume that FIFO is full (2) MR pulse HIGH; clears FIFO (3) DIR goes HIGH; flag indicates input prepared for valid data (4) DOR goes LOW; flag indicates FIFO empty Fig. 6. Propagation delay MR input to DIR output, DOR output and Qn outputs and the MR pulse width. Table 7. Measurement points Input Output VM VM VX VY 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 11 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Shifting in sequence FIFO empty to FIFO full 1st word 2nd word 16th word 1/f max SI input VM (2) VM (5) tPHL (6) tW (1) VM DIR output (3) (4) (7) Dn input aaa-008743 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. (1) DIR initially HIGH; FIFO is prepared for valid data (2) SI set HIGH; data loaded into input stage (3) DIR drops LOW; input stage "busy" (4) DIR goes HIGH; status flag indicates FIFO prepared for additional data (5) SI set LOW; data from first location "ripple through" (6) To load 2 nd th word through to 16 word into FIFO, repeat the process. (7) DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs. Fig. 7. Propagation delay SI input to DIR output, the SI pulse width and the SI maximum frequency With FIFO full; SI held HIGH in anticipation of empty location (2) SO INPUT SI INPUT (1) VM VM tPLH (5) tW bubble - up delay VM DIR OUTPUT (4) (3) mga660 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. (1) FIFO is initially full, shift-in is held HIGH (2) SO pulse; data in output stage is unloaded, "bubble-up" process of empty location begins (3) DIR HIGH; when empty location reaches input stage, flag indicates that FIFO is prepared for data input (4) DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again (5) SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full Fig. 8. Bubble-up delay SO input to DIR output, the DIR pulse width. 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 12 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register SO input to Qn outputs propagation delay VM SO INPUT tPLH tPHL 90 % 90 % VM Qn OUTPUT 10 % 10 % tTLH tTHL mga664 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Propagation delay SO input to Qn outputs and the output transition time Shifting out sequence; FIFO full to FIFO empty 1st SO pulse 1/f max SO input 2nd SO pulse VM (2) 16th SO pulse VM (3) (6) tW tPLH tPLH (5) (1) VM DOR output VM (4) Qn output 1st word (7) 2nd word 16th word aaa-008744 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. (1) DOR HIGH; no data transfer in progress, valid data is present at the output stage (2) SO set HIGH; result in DOR going LOW (3) SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location "bubbles-up" to input stage (4) DOR drops LOW; output stage "busy" (5) DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay rd th (6) To unload the 3 through the 16 word from FIFO, repeat the process (7) DOR remains LOW; FIFO is empty Fig. 10. Propagation delay SO input to DOR output, the SO pulse width and the SO maximum frequency. 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 13 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Shift-in operation; high-speed burst mode 1/fmax tW SI INPUT VM Dn INPUT DIR OUTPUT mga662 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. In the high-speed mode, the minimum shift-in HIGH and shift-in LOW specifications determines the burst-in rate. The DIR status flag is a "don’t care" condition, and a shift-in pulse can be applied regardless of the flag. An SI pulse which would overflow the storage capacity of the FIFO is ignored. Fig. 11. The SI pulse width and the SI maximum frequency, in high-speed shift-in burst mode Shift-out operation; high-speed burst mode 1/fmax tW VM SO INPUT Qn OUTPUT DOR OUTPUT mga663 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. In the high-speed mode, the minimum shift-out HIGH and shift-out LOW specifications determine the burst-out rate. The DOR flag is a "don’t care" condition, and an SO pulse can be applied without regard to the flag. Fig. 12. The SO pulse width and the SO maximum frequency, in high-speed shift-out burst mode 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 14 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register With FIFO empty; SO is held HIGH in anticipation Sl input (2) SO input (1) VM VM (5) tPLH tPHL tW ripple through delay DOR output (3) VM (6) tPHL/tPLH (4) Qn output aaa-008745 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. (1) FIFO is initially empty. SO is held HIGH. (2) SI pulse; loads data into FIFO and initiates ripple through process (3) Output transition; data arrives at output stage after the specified propagation delay between the rising and falling edge of the DOR pulse to the Qn output (4) DOR flag signals the arrival of valid data at the output stage (5) SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty (6) DOR goes LOW; data shift-out is completed, FIFO is empty again Fig. 13. Ripple through delay SI input to DOR output, propagation delay DOR input to Qn outputs and the DOR pulse width MR to SI recovery time MR input VM trec VM SI input aaa-008746 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 14. MR to SI recovery time 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 15 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Enable and disable times VI OE input VM GND tPLZ tPZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY Qn output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled 001aah078 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 15. Enable and disable times Set-up and hold times Dn INPUT VM tsu SI INPUT tsu th th VM mga657 Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the output is permitted to change for predictable output performance Fig. 16. Set-up and hold times 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 16 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Test circuit for measuring switching times VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VCC VO RL RT S1 open CL 001aad983 Test data is given in Table 8. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig. 17. Test circuit for measuring switching times Table 8. Test data Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ VCC 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 17 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 11. Application information data input Dn 4 composite DIR flag Qn DIR data output 4 DOR composite DOR flag 74HC40105 SI MR SI SO SO MR OE OE DIR DOR SI SO 74HC40105 data input 4 MR OE Dn Qn data output 4 aaa-008747 The 74HC40105 is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of an AND gate. The basic operation and timing are identical to a single FIFO, except for an added gate delay on the flags. Fig. 18. Expanded FIFO for increased word length; 16 words x 8 bits 4 Q composite DIR DIR D CP Q 4 DOR SI SO MR OE DIR DOR composite DOR D 74HC74 CP Q Qn 74HC40105 74HC74 Q Dn R SI SI SO SO 74HC40105 MR 4 MR OE Dn Qn OE 4 aaa-008748 This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are started (see Fig. 8). Fig. 19. Expanded FIFO for increased word length 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 18 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 11.1. Expanded format Fig. 20 shows two cascaded FIFOs providing a capacity of 32 words x 4 bits. Fig. 21 shows the signals on the nodes of both FIFOs after the application of the SI pulse, when both FIFOs are initially empty. After a ripple through delay, data arrives at the output of FIFO A. Due to SOA being HIGH, a DORA pulse is generated. The DORA pulse width and the timing between the rising edge of DORA and QnA satisfy the requirements of SIB and DnB. After a second ripple through delay data arrives at the output of FIFO B. Fig. 22 shows the signals on the nodes of both FIFOs after the application of the SOB pulse, when both FIFOs are initially full. After a bubble-up delay, a DIRB pulse is generated, which acts as a SOA pulse for FIFO A. One word is transferred from the output of FIFO A to the input of FIFO B. The pulse width of DORB satisfy the requirements of the SOA pulse for FIFO A. After a second bubble-up delay, an empty space arrives at DnA, at which time DIRA goes HIGH. Fig. 23 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence. FIFO A SI SIA DIR DIRA FIFO B SIB DORA SOA DIRB 74HC40105 data input 4 DnA MR QnA OE DOR DORB SOB SO 74HC40105 4 DnB MR QnB 4 data output OE MR aaa-008749 OE The 74HC40105 is easily cascaded to increase word capacity without external circuitry. In cascaded format, the FIFOs handle all necessary communications. Fig. 18 and Fig. 20 demonstrate the communication timing between FIFO A and FIFO B. Fig. 23 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and shifted empty again. Fig. 20. Cascading for increased word capacity; 32 words x 4 bits 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 19 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register VM DIRA VM SIA (2) ripple through delay (4) DORA/SIB DIRB/SOA QnA/DnB VM (1) (5) VM (6) (3) ripple through delay DORB (7) VM QnB aaa-008750 (1) FIFO A and FIFO B are initially empty, SOA held HIGH in anticipation of data (2) Load one word into FIFO A; SI pulse; applied. results in DIR pulse (3) Data-out A/ data-in B transition; valid data arrives at FIFO A output stage after a specified delay of the DOR flag, meeting data input set-up requirements of FIFO B. (4) DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFO A as a result of the data output ready pulse, data is shifted into FIFO B (5) DIRB and SOA go LOW; flag indicates that input stage of FIFO B is busy, shift-out of FIFO A is complete (6) DIRB and SOA go HIGH automatically; the input stage of FIFO B is again able to receive data, SO is held HIGH in anticipation of additional data (7) DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFO B output stage Fig. 21. FIFO to FIFO communication; input timing under empty condition 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 20 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register VM DORB VM SOB (2) bubble - up delay DIRB/SOA DORA/SIB (3) VM (1) (4) VM (5) QnA/DnB bubble - up delay (6) VM DIRA aaa-008751 (1) FIFO A and FIFO B initially empty, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up (2) Unload one word from FIFO B; SO pulse applied, results in DOR pulse (3) DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFO B as a result of the DIR pulse, data is shifted out of FIFO A (4) DORA and SIB go LOW; flag indicates that the output stage of FIFO A is busy, shift-in of FIFO B is complete (5) DORA and SIB go HIGH; flag indicates that valid data is again available at FIFO A output stage, SIB is held HIGH, awaiting bubble-up of empty location. (6) DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFO A Fig. 22. FIFO to FIFO communication; output timing under full condition 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 21 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register sequence 1 sequence 2 sequence 3 sequence 4 sequence 5 sequence 6 (8) SOB input (3) (4) (14) DORB output QnB output DIRB output (5) (13) (9) DORA output (2) (12) (6) QnA output (10) (7) DIRA output SIA input (11) (1) DnA input MR input aaa-008752 (refer to Fig. 18) See also Sequence 1 (both FIFOs empty, starting SHIFT-IN process) to Sequence 6 (FIFO B runs empty) Fig. 23. Waveforms showing the functionality and intercommunication between to FIFOs Sequence 1 (both FIFOs empty, starting SHIFT-IN process) After an MR pulse has been applied, FIFO A and FIFO B are empty. The DOR flags of FIFO A and FIFO B go LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through the output stage of FIFO A and the input stage of FIFO B (2). When data arrives at the output of FIFO B, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes high (4). Sequence 2 (FIFO B runs full) After the MR pulse, a series of 16 SI pulses are applied. When 16 words are shifted in, DIRB remains LOW due to FIFO B being full (5). DORA goes LOW due to FIFO A being empty. Sequence 3 (FIFO A runs full) When 17 words are shifted in, DORA remains HIGH due to valid data remaining at the output of th th FIFO A. QnA remains HIGH, being the polarity of the 17 word (6). After the 32 SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no effect. 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 22 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Sequence 4 (both FIFOs full, starting SHIFT-OUT) SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty locations to bubble-up to the input stage of FIFO B, and proceed to FIFO A (9). When the first empty location arrives at the input of FIFO A, a DIRA pulse is generated (10) and a new word is shifted into FIFO A. SIA is made LOW and now the second empty location reaches the input stage of FIFO A, after which DIRA remains HIGH (11). Sequence 5 (FIFO A runs empty) At the start of sequence 5, FIFO A contains 15 valid words due to two words being shifted out and one word being shifted in, in sequence 4. And additional series of SOB pulses are applied. After 15 SOB pulses, all words from FIFO A are shifted in FIFO B. DORA remains LOW (12). Sequence 6 (FIFO B runs empty) After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFO B being empty (13). After another 15 SOB pulses, DORB remains LOW due to both FIFOs being empty (14). Additional SOB pulses have no effect. The last word remains available at the output Qn. 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 23 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 24. Package outline SOT109-1 (SO16) 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 24 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 13. Abbreviations Table 9. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge FIFO First In First Out HBM Human Body Model MM Machine Model MSB Most Significant Bit 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC40105 v.5 20190419 Product data sheet - Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74HCT40105D (SOT109-1) removed. Type numbers 74HC40105DB and 74HCT40105DB (SOT338-1) removed. Type number 74HC40105PW (SOT403-1) removed. 74HC_HCT40105 v. 4 20160129 Modifications: • 74HC_HCT40105 v. 3 20130925 Modifications: • • 74HC_HCT40105_CNV v.2 74HC40105 Product data sheet 74HC_HCT40105 v. 4 Product data sheet - 74HC_HCT40105 v. 3 Type numbers 74HC40105N and 74HCT40105N (SOT38-4) removed. Product data sheet - 74HC_HCT40105_CNV v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 19980123 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 - © Nexperia B.V. 2019. All rights reserved 25 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC40105 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 26 / 27 74HC40105 Nexperia 4-bit x 16-word FIFO register Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 4 6. Functional description................................................. 4 6.1. Inputs and outputs.......................................................4 6.2. Data input.................................................................... 5 6.3. Data transfer................................................................5 6.4. Data output.................................................................. 5 6.5. High-speed burst mode............................................... 5 6.6. Expanded format......................................................... 6 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................6 9. Static characteristics....................................................7 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit...................................... 11 11. Application information............................................18 11.1. Expanded format......................................................19 12. Package outline........................................................ 24 13. Abbreviations............................................................ 25 14. Revision history........................................................25 15. Legal information......................................................26 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 19 April 2019 74HC40105 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 April 2019 © Nexperia B.V. 2019. All rights reserved 27 / 27 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74HC40105D,652 74HC40105DB,112 74HC40105DB,118 74HC40105D,653 74HC40105PW,112 74HC40105PW,118 74HCT40105D,112 74HCT40105DB,112 74HCT40105DB,118 74HCT40105D,118 74HCT40105N,112