74AHC30; 74AHCT30
8-input NAND gate
Rev. 4 — 22 July 2015
Product data sheet
1. General description
The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC30; 74AHCT30 provides an 8-input NAND function.
2. Features and benefits
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than VCC
Input levels:
For 74AHC30: CMOS level
For 74AHCT30: TTL level
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
74AHC30D
Package
Temperature
range
Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
40 C to +125 C
XQFN12
SOT1174-1
74AHCT30D
74AHC30PW
74AHCT30PW
74AHC30BQ
74AHCT30BQ
74AHC30GU12
plastic, extremely thin quad flat package; no leads;
12 terminals; body 1.70 2.00 0.50 mm
74AHC30; 74AHCT30
Nexperia
8-input NAND gate
4. Marking
Table 2.
Marking codes
Type number
Marking
74AHC30D
74AHC30D
74AHCT30D
74AHCT30D
74AHC30PW
AHC30
74AHCT30PW
AHCT30
74AHC30BQ
AHC30
74AHCT30BQ
AHT30
74AHC30GU12
A3[1]
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
$
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PQD
PQD
Pin numbers are shown for SO14, TSSOP14 and
DHVQFN14 packages only
Fig 1.
Logic symbol
Pin numbers are shown for SO14, TSSOP14 and
DHVQFN14 packages only
Fig 2.
IEC logic symbol
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PQD
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Fig 3.
Logic diagram
74AHC_AHCT30
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 July 2015
©
Nexperia B.V. 2017. All rights reserved
2 of 17
74AHC30; 74AHCT30
Nexperia
8-input NAND gate
6. Pinning information
6.1 Pinning
$
WHUPLQDO
LQGH[DUHD
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QF
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)
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QF
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*1'
QF
*1'
<
QF
DDN
7UDQVSDUHQWWRSYLHZ
DDL
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad,
however if it is soldered the solder land should remain
floating or be connected to GND
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
WHUPLQDO
LQGH[DUHD
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Fig 6.
Pin configuration XQFN12 (SOT1174-1)
74AHC_AHCT30
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 July 2015
©
Nexperia B.V. 2017. All rights reserved
3 of 17
74AHC30; 74AHCT30
Nexperia
8-input NAND gate
6.2 Pin description
Table 3.
Symbol
A
Pin description
Pin
Description
SO14, TSSOP14 and DHVQFN14
XQFN12
1
1
data input
B
2
2
data input
C
3
3
data input
D
4
4
data input
E
5
5
data input
F
6
7
data input
GND
7
6
ground (0 V)
Y
8
8
data output
n.c.
9
-
not connected
n.c.
10
-
not connected
G
11
9
data input
H
12
10
data input
n.c.
13
11
not connected
VCC
14
12
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
A
B
C
D
E
F
G
H
Y
L
X
X
X
X
X
X
X
H
X
L
X
X
X
X
X
X
H
X
X
L
X
X
X
X
X
H
X
X
X
L
X
X
X
X
H
X
X
X
X
L
X
X
X
H
X
X
X
X
X
L
X
X
H
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74AHC_AHCT30
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 July 2015
©
Nexperia B.V. 2017. All rights reserved
4 of 17
74AHC30; 74AHCT30
Nexperia
8-input NAND gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7.0
V
VI
input voltage
0.5
+7.0
V
IIK
input clamping current
VI < 0.5 V
[1]
20
-
mA
IOK
output clamping current
VO VCC + 0.5 V
[1]
20
+20
mA
IO
output current
VO =0.5 V to (VCC + 0.5 V)
25
+25
mA
ICC
supply current
-
+75
mA
IGND
ground current
75
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
-
500
mW
-
250
mW
Tamb = 40 C to +125 C
[2]
SO14, TSSOP14 and DHVQFN14
XQFN12
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO14 packages: above 70 C, the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 C, the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 C, the value of Ptot derates linearly at 4.5 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise
and fall rate
74AHC_AHCT30
Product data sheet
Conditions
74AHC30
74AHCT30
Unit
Min
Typ
Max
Min
Typ
Max
2.0
5.0
5.5
4.5
5.0
5.5
V
0
-
5.5
0
-
5.5
V
0
-
VCC
0
-
VCC
V
40
+25
+125
40
+25
+125
C
VCC = 3.3 V 0.3 V
-
-
100
-
-
-
ns/V
VCC = 5.0 V 0.5 V
-
-
20
-
-
20
ns/V
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 July 2015
©
Nexperia B.V. 2017. All rights reserved
5 of 17
74AHC30; 74AHCT30
Nexperia
8-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
-
-
1.5
-
1.5
-
V
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
74AHC30
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 50 A; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = 50 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.40
-
V
IO = 8.0 mA; VCC = 4.5 V
3.94
-
-
3.80
-
3.70
-
V
LOW-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
A
II
input leakage
current
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
CI
input
capacitance
-
3
10
-
10
-
10
pF
CO
output
capacitance
-
4
-
-
-
-
-
pF
74AHC_AHCT30
Product data sheet
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
VI = VCC or GND
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 July 2015
©
Nexperia B.V. 2017. All rights reserved
6 of 17
74AHC30; 74AHCT30
Nexperia
8-input NAND gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
74AHCT30
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.80
-
3.70
-
V
-
0
0.1
-
0.1
-
0.1
V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
A
IO = 8.0 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 A
IO = 8.0 mA
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
ICC
additional
per input pin;
supply current VI = VCC 2.1 V; other pins
at VCC or GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
3
10
-
10
-
10
pF
CO
output
capacitance
-
4
-
-
-
-
-
pF
VI = VCC or GND
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
25 C
Conditions
Min
Typ[1]
40 C to +85 C
Max
40 C to +125 C Unit
Min
Max
Min
Max
74AHC30
tpd
propagation
delay
A, B, C, D, E, F, G, H to Y; see Figure 7 and 8 [2]
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
5.0
9.5
1.0
11.0
1.0
12.0
ns
CL = 50 pF
-
6.7
12.0
1.0
14.5
1.0
15.5
ns
-
3.6
6.5
1.0
7.5
1.0
8.0
ns
-
4.9
8.0
1.0
9.5
1.0
10.5
ns
-
10
-
-
-
-
-
pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
CPD
power
fi = 1 MHz;
dissipation
VI = GND to VCC
capacitance
74AHC_AHCT30
Product data sheet
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 July 2015
©
Nexperia B.V. 2017. All rights reserved
7 of 17
74AHC30; 74AHCT30
Nexperia
8-input NAND gate
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
25 C
Conditions
Min
Typ[1]
40 C to +85 C
Max
40 C to +125 C Unit
Min
Max
Min
Max
74AHCT30; VCC = 4.5 V to 5.5 V
propagation
delay
tpd
A, B, C, D, E, F, G, H to Y; see Figure 7 and 8 [2]
CL = 15 pF
CL = 50 pF
[3]
power
fi = 1 MHz;
dissipation
VI = GND to VCC
capacitance
CPD
-
3.3
6.5
1.0
7.5
1.0
8.0
ns
-
4.7
8.5
1.0
9.5
1.0
10.5
ns
-
12
-
-
-
-
-
pF
[1]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2]
tpd is the same as tPLH and tPHL.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
12. Waveforms
9,
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W3/+
92+
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