74AUP1G38GX,125

74AUP1G38 Low-power 2-input NAND gate (open drain) Rev. 7 — 4 April 2016 Product data sheet 1. General description The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 0.8 V to 3.6 V  High noise immunity  Complies with JEDEC standards:  JESD8-12 (0.8 V to 1.3 V)  JESD8-11 (0.9 V to 1.65 V)  JESD8-7 (1.2 V to 1.95 V)  JESD8-5 (1.8 V to 2.7 V)  JESD8-B (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F Class 3A exceeds 5000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Low static power consumption; ICC = 0.9 A (maximum)  Latch-up performance exceeds 100 mA per JESD 78 Class II  Inputs accept voltages up to 3.6 V  Low noise overshoot and undershoot < 10 % of VCC  IOFF circuitry provides partial power-down mode operation  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C 74AUP1G38 Nexperia Low-power 2-input NAND gate (open drain) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G38GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G38GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.5 mm 74AUP1G38GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1  1  0.5 mm 74AUP1G38GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74AUP1G38GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 74AUP1G38GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8  0.8  0.35 mm SOT1226 4. Marking Table 2. Marking Marking code[1] Type number 74AUP1G38GW aB 74AUP1G38GM aB 74AUP1G38GF aB 74AUP1G38GN aB 74AUP1G38GS aB 74AUP1G38GX aB [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram <  $  <   % Logic symbol 74AUP1G38 Product data sheet   % *1' DDE DDE Fig 1. $ Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 April 2016 DDE Fig 3. Logic diagram © Nexperia B.V. 2017. All rights reserved 2 of 19 74AUP1G38 Nexperia Low-power 2-input NAND gate (open drain) 6. Pinning information 6.1 Pinning $83* $83* $  %  *1'   9&&  < $   9&& %   QF *1'   < DDI 7UDQVSDUHQWWRSYLHZ DDI Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) $83* $83* $ $   9&& %   QF *1'   <  9&&  <  *1' % DDI  DDD 7UDQVSDUHQWWRSYLHZ 7UDQVSDUHQWWRSYLHZ Fig 6.  Pin configuration SOT891, SOT1115 and SOT1202 (XSON6) Fig 7. Pin configuration SOT1226 (X2SON5) 6.2 Pin description Table 3. Pin description Symbol Pin Description TSSOP5 and X2SON5 XSON6 A 1 1 data input B 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 74AUP1G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 April 2016 © Nexperia B.V. 2017. All rights reserved 3 of 19 74AUP1G38 Nexperia Low-power 2-input NAND gate (open drain) 7. Functional description Table 4. Function table[1] Input Output A B Y L L Z L H Z H L Z H H L [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO < 0 V [1] Min Max Unit 0.5 +4.6 50 - 0.5 +4.6 50 - 0.5 +4.6 V - +20 mA V mA V mA VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current - +50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 250 mW [1] [2] Tamb = 40 C to +125 C [2] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 and X2SON5 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate 74AUP1G38 Product data sheet Conditions Active mode and Power-down mode VCC = 0.8 V to 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 April 2016 Min Max Unit 0.8 3.6 V 0 3.6 V 0 3.6 V 40 +125 C 0 200 ns/V © Nexperia B.V. 2017. All rights reserved 4 of 19 74AUP1G38 Nexperia Low-power 2-input NAND gate (open drain) 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.70  VCC - - V VCC = 0.9 V to 1.95 V 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30  VCC V VCC = 0.9 V to 1.95 V - - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.31 V Tamb = 25 C VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL 0.3  VCC V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A IOZ OFF-state output current VI = VIH or VIL (and at least one input LOW); VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.2 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 40 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF CO output capacitance output enabled; VO = GND; VCC = 0 V - 1.7 - pF output disabled; VO = GND; VCC = 0 V - 1.1 - pF VCC = 0.8 V 0.70  VCC - - V VCC = 0.9 V to 1.95 V 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V Tamb = 40 C to +85 C VIH HIGH-level input voltage 74AUP1G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 April 2016 © Nexperia B.V. 2017. All rights reserved 5 of 19 74AUP1G38 Nexperia Low-power 2-input NAND gate (open drain) Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ VIL VCC = 0.8 V - - 0.30  VCC V VCC = 0.9 V to 1.95 V - - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V VOL LOW-level input voltage LOW-level output voltage Max Unit VI = VIH or VIL 0.3  VCC V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A IOZ OFF-state output current VI = VIH or VIL (and at least one input LOW); VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.6 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 50 A VCC = 0.8 V 0.75  VCC - - V VCC = 0.9 V to 1.95 V 0.70  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25  VCC V VCC = 0.9 V to 1.95 V - - 0.30  VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V Tamb = 40 C to +125 C VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage 74AUP1G38 Product data sheet VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 April 2016 0.33  VCC V © Nexperia B.V. 2017. All rights reserved 6 of 19 74AUP1G38 Nexperia Low-power 2-input NAND gate (open drain) Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A IOZ OFF-state output current VI = VIH or VIL (and at least one input LOW); VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.75 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 75 A 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9 Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min - 13.5 - - - - ns VCC = 1.1 V to 1.3 V 1.9 4.6 10.4 1.8 11.4 12.6 ns VCC = 1.4 V to 1.6 V 1.5 3.3 6.5 1.4 7.4 8.2 ns Max Max (85 C) (125 C) CL = 5 pF tpd propagation delay A or B to Y; see Figure 8 [2] VCC = 0.8 V VCC = 1.65 V to 1.95 V 1.2 2.9 5.1 1.1 5.9 6.5 ns VCC = 2.3 V to 2.7 V 1.0 2.2 3.8 0.9 4.5 4.9 ns VCC = 3.0 V to 3.6 V 0.9 2.3 4.0 0.8 4.5 4.9 ns - 16.3 - - - - ns VCC = 1.1 V to 1.3 V 2.3 5.6 12.3 2.1 13.7 15.1 ns VCC = 1.4 V to 1.6 V 1.8 4.1 7.6 1.7 8.8 9.7 ns CL = 10 pF tpd propagation delay A or B to Y; see Figure 8 [2] VCC = 0.8 V VCC = 1.65 V to 1.95 V 1.6 3.8 6.1 1.4 7.1 7.8 ns VCC = 2.3 V to 2.7 V 1.4 2.9 4.6 1.2 5.4 5.9 ns VCC = 3.0 V to 3.6 V 1.3 3.2 5.7 1.1 6.4 7.0 ns - 19.0 - - - - ns VCC = 1.1 V to 1.3 V 2.6 6.6 14.2 2.4 15.8 17.4 ns VCC = 1.4 V to 1.6 V 2.1 4.8 8.7 1.9 10.1 11.1 ns VCC = 1.65 V to 1.95 V 1.9 4.6 7.6 1.7 8.5 9.3 ns VCC = 2.3 V to 2.7 V 1.6 3.6 5.6 1.5 6.3 6.9 ns VCC = 3.0 V to 3.6 V 1.6 4.1 7.5 1.4 8.3 9.1 ns CL = 15 pF tpd propagation delay A or B to Y; see Figure 8 VCC = 0.8 V 74AUP1G38 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 April 2016 © Nexperia B.V. 2017. All rights reserved 7 of 19 74AUP1G38 Nexperia Low-power 2-input NAND gate (open drain) Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9 Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min - 27.0 - - - - ns 3.6 9.5 19.5 3.2 21.8 24.0 ns Max Max (85 C) (125 C) CL = 30 pF propagation delay A or B to Y; see Figure 8 tpd [2] VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V 2.9 7.0 11.5 2.6 13.6 15.0 ns VCC = 1.65 V to 1.95 V 2.6 7.0 12.1 2.3 13.3 14.6 ns VCC = 2.3 V to 2.7 V 2.4 5.4 8.9 2.1 9.9 10.9 ns VCC = 3.0 V to 3.6 V 2.3 6.5 12.7 2.1 13.9 15.3 ns VCC = 0.8 V - 0.6 - - - - pF VCC = 1.1 V to 1.3 V - 0.7 - - - - pF VCC = 1.4 V to 1.6 V - 0.8 - - - - pF VCC = 1.65 V to 1.95 V - 0.9 - - - - pF VCC = 2.3 V to 2.7 V - 1.1 - - - - pF VCC = 3.0 V to 3.6 V - 1.4 - - - - pF CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPZL and tPLZ. [3] [3] fi = 1 MHz; VI = GND to VCC CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N where: fi = input frequency in MHz; VCC = supply voltage in V; N = number of inputs switching. 74AUP1G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 4 April 2016 © Nexperia B.V. 2017. All rights reserved 8 of 19 74AUP1G38 Nexperia Low-power 2-input NAND gate (open drain) 12. Waveforms 9, $%LQSXW 90 *1' W 3/= W 3=/ 9&&