74AUP1G98GF,132

74AUP1G98 Low-power configurable multiple function gate Rev. 8 — 23 September 2015 Product data sheet 1. General description The 74AUP1G98 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G98 has Schmitt trigger inputs making it capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT is defined as the input hysteresis voltage VH. 2. Features and benefits  Wide supply voltage range from 0.8 V to 3.6 V  High noise immunity  ESD protection:  HBM JESD22-A114F exceeds 5000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Low static power consumption; ICC = 0.9 A (maximum)  Latch-up performance exceeds 100 mA per JESD 78 Class II  Inputs accept voltages up to 3.6 V  Low noise overshoot and undershoot < 10 % of VCC  IOFF circuitry provides partial power-down mode operation  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C 74AUP1G98 Nexperia Low-power configurable multiple function gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G98GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP1G98GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.5 mm 74AUP1G98GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1  1  0.5 mm 74AUP1G98GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74AUP1G98GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 74AUP1G98GX 40 C to +125 C X2SON6 plastic thermal extremely thin small outline package; no leads; 6 terminals; body 1  0.8  0.35 mm SOT1255 4. Marking Table 2. Marking Type number Marking code[1] 74AUP1G98GW a9 74AUP1G98GM a9 74AUP1G98GF a9 74AUP1G98GN a9 74AUP1G98GS a9 74AUP1G98GX a9 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram $   % & Fig 1.  <  DDG Logic diagram 74AUP1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 © Nexperia B.V. 2017. All rights reserved 2 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate 6. Pinning information 6.1 Pinning $83* $83* %   & *1'   9&& $   < %   & *1'   9&& $   < DDG 7UDQVSDUHQWWRSYLHZ DDG Fig 2. Pin configuration SOT363 Fig 3. Pin configuration SOT886 $83* $83* %  %   & *1'   9&& $   < *1' &    $ DDG  < DDD 7UDQVSDUHQWWRSYLHZ Fig 4. 9&&  7UDQVSDUHQWWRSYLHZ Pin configuration SOT891, SOT1115 and SOT1202 Fig 5. Pin configuration SOT1255 (X2SON6) 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input GND 2 ground (0 V) A 3 data input Y 4 data output VCC 5 supply voltage C 6 data input 74AUP1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 © Nexperia B.V. 2017. All rights reserved 3 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate 7. Functional description Table 4. Function table[1] Input Output C B A Y L L L H L L H H L H L L L H H L H L L H H L H L H H L H H H H L [1] H = HIGH voltage level; L = LOW voltage level. 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input MUX with inverted output see Figure 6 2-input NAND see Figure 7 2-input NOR with one input inverted see Figure 8 2-input AND with one input inverted see Figure 8 2-input NAND with one input inverted see Figure 9 2-input OR with one input inverted see Figure 9 2-input NOR see Figure 10 Buffer see Figure 11 Inverter see Figure 12 9&& 9&& % %   & < $ & $     $ & < < $       DDG Fig 6. 2-input MUX with inverted output 74AUP1G98 Product data sheet & < DDG Fig 7. 2-input NAND gate All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 © Nexperia B.V. 2017. All rights reserved 4 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate 9&& $ & < $ & < $      9&& & <  % & < % & < %       < DDG DDG Fig 8. & 2-input AND gate with input A inverted or 2-input NOR gate with inverted C input Fig 9. 2-input OR gate with input B inverted or 2-input NAND gate with input C inverted 9&& % % & <       9&& & & <       & < DDG < DDG Fig 10. 2-input NOR gate Fig 11. Buffer 9&& % % <       < DDG Fig 12. Inverter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO < 0 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current 74AUP1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 [1] Min Max Unit 0.5 +4.6 V 50 - 0.5 +4.6 50 - 0.5 +4.6 V - 20 mA - 50 mA © mA V mA Nexperia B.V. 2017. All rights reserved 5 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate Table 6. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter IGND ground current Tstg storage temperature total power dissipation Ptot Conditions Tamb = 40 C to +125 C Min Max Unit 50 - mA 65 +150 C - 250 mW [2] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For X2SON6 and XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb Conditions Min Max Unit 0.8 3.6 V 0 3.6 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V 40 +125 C ambient temperature 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V Tamb = 25 C VOH VOL HIGH-level output voltage LOW-level output voltage 74AUP1G98 Product data sheet VI = VT+ or VT IO = 1.1 mA; VCC = 1.1 V 0.75VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.11 - - V IO = 1.9 mA; VCC = 1.65 V 1.32 - - V IO = 2.3 mA; VCC = 2.3 V 2.05 - - V IO = 3.1 mA; VCC = 2.3 V 1.9 - - V IO = 2.7 mA; VCC = 3.0 V 2.72 - - V IO = 4.0 mA; VCC = 3.0 V 2.6 - - V VI = VT+ or VT IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 © Nexperia B.V. 2017. All rights reserved 6 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.2 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 40 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 1.1 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF VCC  0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.7VCC - - V [1] Tamb = 40 C to +85 C VOH HIGH-level output voltage VI = VT+ or VT IO = 20 A; VCC = 0.8 V to 3.6 V VOL LOW-level output voltage IO = 1.7 mA; VCC = 1.4 V 1.03 - - V IO = 1.9 mA; VCC = 1.65 V 1.30 - - V IO = 2.3 mA; VCC = 2.3 V 1.97 - - V IO = 3.1 mA; VCC = 2.3 V 1.85 - - V IO = 2.7 mA; VCC = 3.0 V 2.67 - - V IO = 4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V VI = VT+ or VT II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.6 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 50 A 74AUP1G98 Product data sheet [1] All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 © Nexperia B.V. 2017. All rights reserved 7 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 40 C to +125 C VOH HIGH-level output voltage VI = VT+ or VT IO = 20 A; VCC = 0.8 V to 3.6 V LOW-level output voltage VOL VCC  0.11 - - V IO = 1.1 mA; VCC = 1.1 V 0.6VCC - - V IO = 1.7 mA; VCC = 1.4 V 0.93 - - V IO = 1.9 mA; VCC = 1.65 V 1.17 - - V IO = 2.3 mA; VCC = 2.3 V 1.77 - - V IO = 3.1 mA; VCC = 2.3 V 1.67 - - V IO = 2.7 mA; VCC = 3.0 V 2.40 - - V IO = 4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V VI = VT+ or VT IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.75 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 75 A [1] [1] One input at VCC  0.6 V, other input at VCC or GND. 74AUP1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 © Nexperia B.V. 2017. All rights reserved 8 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min - 23.3 - - - - Max Max (85 C) (125 C) CL = 5 pF tpd propagation delay A, B, C to Y; see Figure 13 [2] VCC = 0.8 V ns VCC = 1.1 V to 1.3 V 2.9 6.7 12.9 2.7 13.2 13.4 ns VCC = 1.4 V to 1.6 V 2.4 4.8 7.7 2.4 8.3 8.7 ns VCC = 1.65 V to 1.95 V 2.2 4.0 6.3 1.9 7.0 7.4 ns VCC = 2.3 V to 2.7 V 2.0 3.2 4.6 1.8 5.2 5.4 ns VCC = 3.0 V to 3.6 V 1.9 2.9 4.0 1.6 4.2 4.4 ns - 27.1 - - - - ns CL = 10 pF tpd propagation delay A, B, C to Y; see Figure 13 [2] VCC = 0.8 V VCC = 1.1 V to 1.3 V 3.3 7.6 14.5 3.0 15.1 15.3 ns VCC = 1.4 V to 1.6 V 2.7 5.4 8.8 2.8 9.5 9.9 ns VCC = 1.65 V to 1.95 V 2.5 4.6 7.2 2.3 8.0 8.4 ns VCC = 2.3 V to 2.7 V 2.4 3.8 5.3 2.2 5.9 6.2 ns VCC = 3.0 V to 3.6 V 2.3 3.5 4.7 2.0 4.9 5.2 ns - 30.6 - - - - ns CL = 15 pF tpd propagation delay A, B, C to Y; see Figure 13 VCC = 0.8 V 74AUP1G98 Product data sheet [2] VCC = 1.1 V to 1.3 V 3.6 8.4 16.1 3.3 16.9 17.2 ns VCC = 1.4 V to 1.6 V 3.0 6.0 9.7 3.1 10.5 11.0 ns VCC = 1.65 V to 1.95 V 2.8 5.1 7.9 2.5 8.9 9.3 ns VCC = 2.3 V to 2.7 V 2.7 4.2 5.9 2.5 6.6 7.0 ns VCC = 3.0 V to 3.6 V 2.5 3.9 5.2 2.2 5.5 5.8 ns All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 © Nexperia B.V. 2017. All rights reserved 9 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min - 38.7 - - - - ns VCC = 1.1 V to 1.3 V 4.5 10.7 21.1 4.1 22.0 22.4 ns Max Max (85 C) (125 C) CL = 30 pF propagation delay tpd A, B, C to Y; see Figure 13 [2] VCC = 0.8 V VCC = 1.4 V to 1.6 V 3.8 7.6 12.3 3.8 13.5 14.2 ns VCC = 1.65 V to 1.95 V 3.5 6.3 10.1 3.1 11.3 11.9 ns VCC = 2.3 V to 2.7 V 3.4 5.3 7.5 3.2 8.4 8.9 ns VCC = 3.0 V to 3.6 V 3.2 5.0 6.7 2.9 7.1 7.5 ns VCC = 0.8 V - 2.7 - - - - pF VCC = 1.1 V to 1.3 V - 2.9 - - - - pF VCC = 1.4 V to 1.6 V - 3.0 - - - - pF VCC = 1.65 V to 1.95 V - 3.2 - - - - pF VCC = 2.3 V to 2.7 V - 3.8 - - - - pF VCC = 3.0 V to 3.6 V - 4.4 - - - - pF CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD fi = 1 MHz; VI = GND to VCC [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL [3] [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. 74AUP1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 23 September 2015 © Nexperia B.V. 2017. All rights reserved 10 of 24 74AUP1G98 Nexperia Low-power configurable multiple function gate 12. Waveforms 9, $%&LQSXW 90 90 *1' W 3+/ W 3/+ 92+ 90