74AUP1T98GW-Q100H

74AUP1T98-Q100 Low-power configurable gate with voltage-level translator Rev. 2 — 5 October 2018 Product data sheet 1. General description The 74AUP1T98-Q100 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T98-Q100 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 2.3 V to 3.6 V High noise immunity ESD protection: • MIL-STD-883, method 3015 Class 3A, exceeds 5000 V • HBM JESD22-A114F Class 3A, exceeds 5000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Low static power consumption; ICC = 1.5 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation 3. Ordering information Table 1. Ordering information Type number Package 74AUP1T98GW-Q100 Temperature range Name Description Version -40 °C to +125 °C plastic surface-mounted package; 6 leads SOT363 SC-88 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator 4. Marking Table 2. Marking Type number Marking code 74AUP1T98GW-Q100 aR 5. Functional diagram 3 A 4 1 B 6 C Fig. 1. Y 001aad987 Logic symbol 6. Pinning information 6.1. Pinning 74AUP1T98 B 1 6 C GND 2 5 VCC A 3 4 Y 001aah839 Fig. 2. Pin configuration SOT363 (SC-88) 6.2. Pin description Table 3. Pin description Symbol Pin Description B 1 data input GND 2 ground (0 V) A 3 data input Y 4 data output VCC 5 supply voltage C 6 data input 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 2 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Output Input C B A Y L L L H L L H H L H L L L H H L H L L H H L H L H H L H H H H L 7.1. Logic configurations Table 5. Function selection table Logic function Figure 2-input MUX (inverting) see Fig. 3 2-input NAND see Fig. 4 2-input NOR with one input inverted see Fig. 5 2-input AND with one input inverted see Fig. 5 2-input NAND with one input inverted see Fig. 6 2-input OR with one input inverted see Fig. 6 2-input NOR see Fig. 7 Buffer see Fig. 8 Inverter see Fig. 9 VCC B Y A C B 1 A 6 2 5 3 4 VCC C A C Y Y A 1 6 2 5 3 4 001aad991 Fig. 3. 2-input MUX (inverting) C Y 001aad992 Fig. 4. 2-input NAND gate VCC A C Y A C Y A 1 6 2 5 3 4 VCC C Y B C Y B C Y B 1 6 2 5 3 4 001aad993 Fig. 5. Product data sheet Y 001aad994 2-input AND gate with input A inverted or 2input NOR gate with input C inverted 74AUP1T98_Q100 C Fig. 6. 2-input OR gate with input B inverted or 2-input NAND gate with input C inverted All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 3 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator VCC B B C Y 1 6 2 5 3 4 VCC C C Y Y 1 6 2 5 3 4 001aad995 Fig. 7. C Y 001aad996 2-input NOR gate Fig. 8. Buffer VCC B B Y 1 6 2 5 3 4 Y 001aad997 Fig. 9. Inverter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC supply voltage -0.5 +4.6 V IIK input clamping current -50 - VI input voltage IOK output clamping current VO < 0 V -0.5 +4.6 -50 - VO output voltage Active mode and Power-down mode -0.5 +4.6 V IO output current VO = 0 V to VCC - ±20 mA ICC supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] Conditions VI < 0 V [1] Tamb = -40 °C to +125 °C [1] [2] mA V mA The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SC-88 package: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 2.3 3.6 V VI input voltage 0 3.6 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V -40 +125 °C Tamb ambient temperature 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 4 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VT+ positive-going threshold voltage VCC = 2.3 V to 2.7 V 0.60 - 1.10 V VCC = 3.0 V to 3.6 V 0.75 - 1.16 V VT- negative-going threshold voltage VCC = 2.3 V to 2.7 V 0.35 - 0.60 V VCC = 3.0 V to 3.6 V 0.50 - 0.85 V hysteresis voltage (VH = VT+ - VT-) VCC = 2.3 V to 2.7 V 0.23 - 0.60 V VCC = 3.0 V to 3.6 V 0.25 - 0.56 V VCC - 0.1 - - V IO = -2.3 mA; VCC = 2.3 V 2.05 - - V IO = -3.1 mA; VCC = 2.3 V 1.9 - - V IO = -2.7 mA; VCC = 3.0 V 2.72 - - V IO = -4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 μA; VCC = 2.3 V to 3.6 V - - 0.10 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V VH VOH HIGH-level output voltage VI = VT+ or VTIO = -20 μA; VCC = 2.3 V to 3.6 V VOL LOW-level output voltage VI = VT+ or VT- II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.1 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.2 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 2.3 V to 3.6 V - - 1.2 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 5 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator Symbol Parameter Conditions Min Typ Max Unit Tamb = -40 °C to +85 °C VT+ positive-going threshold voltage VCC = 2.3 V to 2.7 V 0.60 - 1.10 V VCC = 3.0 V to 3.6 V 0.75 - 1.19 V VT- negative-going threshold voltage VCC = 2.3 V to 2.7 V 0.35 - 0.60 V VCC = 3.0 V to 3.6 V 0.50 - 0.85 V hysteresis voltage (VH = VT+ - VT-) VCC = 2.3 V to 2.7 V 0.10 - 0.60 V VCC = 3.0 V to 3.6 V 0.15 - 0.56 V VCC - 0.1 - - V IO = -2.3 mA; VCC = 2.3 V 1.97 - - V IO = -3.1 mA; VCC = 2.3 V 1.85 - - V IO = -2.7 mA; VCC = 3.0 V 2.67 - - V IO = -4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 μA; VCC = 2.3 V to 3.6 V - - 0.1 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V VH VOH HIGH-level output voltage VI = VT+ or VTIO = -20 μA; VCC = 2.3 V to 3.6 V VOL LOW-level output voltage VI = VT+ or VT- II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.5 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 2.3 V to 3.6 V - - 1.5 μA ΔICC additional supply current VCC = 2.3 V to 2.7 V; IO = 0 A [1] - - 4 μA VCC = 3.0 V to 3.6 V; IO = 0 A [2] - - 12 μA 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 6 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator Symbol Parameter Conditions Min Typ Max Unit Tamb = -40 °C to +125 °C VT+ positive-going threshold voltage VCC = 2.3 V to 2.7 V 0.60 - 1.10 V VCC = 3.0 V to 3.6 V 0.75 - 1.19 V VT- negative-going threshold voltage VCC = 2.3 V to 2.7 V 0.33 - 0.64 V VCC = 3.0 V to 3.6 V 0.46 - 0.85 V hysteresis voltage (VH = VT+ - VT-) VCC = 2.3 V to 2.7 V 0.10 - 0.60 V VCC = 3.0 V to 3.6 V 0.15 - 0.56 V VCC - 0.11 - - V IO = -2.3 mA; VCC = 2.3 V 1.77 - - V IO = -3.1 mA; VCC = 2.3 V 1.67 - - V IO = -2.7 mA; VCC = 3.0 V 2.40 - - V IO = -4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 μA; VCC = 2.3 V to 3.6 V - - 0.11 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V VH VOH HIGH-level output voltage VI = VT+ or VTIO = -20 μA; VCC = 2.3 V to 3.6 V VOL LOW-level output voltage VI = VT+ or VT- II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.75 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 2.3 V to 3.6 V - - 3.5 μA ΔICC additional supply current VCC = 2.3 V to 2.7 V; IO = 0 A [1] - - 7 μA VCC = 3.0 V to 3.6 V; IO = 0 A [2] - - 22 μA [1] [2] One input at 0.3 V or 1.1 V, other input at VCC or GND. One input at 0.45 V or 1.2 V, other input at VCC or GND. 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 7 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 11. Symbol Parameter Conditions 25 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max (85 °C) Max (125 °C) CL = 5 pF 2.0 3.6 5.7 0.5 6.8 7.5 ns CL = 10 pF 2.5 4.2 6.3 1.0 7.9 8.7 ns CL = 15 pF 2.9 4.6 6.9 1.0 8.7 9.6 ns CL = 30 pF 3.9 5.8 8.3 1.5 10.8 11.9 ns CL = 5 pF 1.7 3.4 5.6 0.5 6.0 6.6 ns CL = 10 pF 2.1 4.0 6.3 1.0 7.1 7.9 ns CL = 15 pF 2.5 4.5 6.9 1.0 7.9 8.7 ns CL = 30 pF 3.4 5.6 8.4 1.5 10.0 11.0 ns CL = 5 pF 1.3 3.2 5.2 0.5 5.5 6.1 ns CL = 10 pF 1.8 3.7 5.9 1.0 6.5 7.2 ns CL = 15 pF 2.2 4.2 6.5 1.0 7.4 8.2 ns CL = 30 pF 3.1 5.4 7.9 1.5 9.5 10.5 ns CL = 5 pF 2.0 2.9 4.1 0.5 8.0 8.8 ns CL = 10 pF 2.4 3.5 4.8 1.0 8.5 9.4 ns CL = 15 pF 2.8 3.9 5.4 1.0 9.1 10.1 ns CL = 30 pF 3.6 5.1 6.9 1.5 9.8 10.8 ns CL = 5 pF 1.5 2.8 4.4 0.5 5.3 5.9 ns CL = 10 pF 2.0 3.4 5.1 1.0 6.1 6.8 ns CL = 15 pF 2.4 3.9 5.7 1.0 6.8 7.5 ns CL = 30 pF 3.4 5.0 7.2 1.5 8.5 9.4 ns CL = 5 pF 1.3 2.8 4.4 0.5 4.7 5.2 ns CL = 10 pF 1.7 3.3 5.2 1.0 5.7 6.3 ns CL = 15 pF 2.1 3.8 5.8 1.0 6.2 6.9 ns CL = 30 pF 3.1 5.0 7.2 1.5 7.8 8.6 ns VCC = 2.3 V to 2.7 V; VI = 1.65 V to 1.95 V tpd propagation delay A, B, C to Y; see Fig. 10 [2] VCC = 2.3 V to 2.7 V; VI = 2.3 V to 2.7 V tpd propagation delay A, B, C to Y; see Fig. 10 [2] VCC = 2.3 V to 2.7 V; VI = 3.0 V to 3.6 V tpd propagation delay A, B, C to Y; see Fig. 10 [2] VCC = 3.0 V to 3.6 V; VI = 1.65 V to 1.95 V tpd propagation delay A, B, C to Y; see Fig. 10 [2] VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V tpd propagation delay A, B, C to Y; see Fig. 10 [2] VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V tpd propagation delay A, B, C to Y; see Fig. 10 74AUP1T98_Q100 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 8 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator Symbol Parameter Conditions 25 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max (85 °C) Max (125 °C) VCC = 2.3 V to 2.7 V - 3.6 - - - - pF VCC = 3.0 V to 3.6 V - 4.3 - - - - pF Tamb = 25 °C CPD [1] [2] [3] power dissipation capacitance fi = 1 MHz; VI = GND to VCC [3] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of the outputs. 11.1. Waveforms and test circuits VI A, B, C input VM VM GND t PHL t PLH VOH VM Y output VM VOL t PLH t PHL VOH Y output VM VM VOL 001aab593 Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. Input A, B and C to output Y propagation delay times Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 2.3 V to 3.6 V 0.5 x VCC 0.5 x VI 1.65 V to 3.6 V ≤ 3.0 ns 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 9 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator VCC G VI DUT VEXT 5 kΩ VO RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 11. Test circuit for measuring switching times Table 11. Test data Supply voltage Load VCC CL RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 2.3 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ open GND 2 × VCC [1] VEXT For measuring enable and disable times RL = 5 kΩ. For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 10 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator 12. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E y A X HE 6 5 v M A 4 Q pin 1 index A 1 2 e1 A1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT363 JEITA EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 SC-88 Fig. 12. Package outline SOT363 (SC-88) 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 11 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator 13. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 14. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1T98_Q100 v.2 20181005 Product data sheet - 74AUP1T98_Q100 v.1 Modifications: • • 74AUP1T98_Q100 v.1 74AUP1T98_Q100 Product data sheet The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 20140519 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 - © Nexperia B.V. 2018. All rights reserved 12 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 13 / 14 74AUP1T98-Q100 Nexperia Low-power configurable gate with voltage-level translator Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 2 7. Functional description................................................. 3 7.1. Logic configurations.....................................................3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................8 11.1. Waveforms and test circuits.......................................9 12. Package outline........................................................ 11 13. Abbreviations............................................................ 12 14. Revision history........................................................12 15. Legal information......................................................13 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 5 October 2018 74AUP1T98_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 October 2018 © Nexperia B.V. 2018. All rights reserved 14 / 14 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74AUP1T98GW-Q100H