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74AXP1G09GSH

74AXP1G09GSH

  • 厂商:

    NEXPERIA(安世)

  • 封装:

    XSON6_1X1MM

  • 描述:

    IC GATE AND OD 1CH 2-INP 6XSON

  • 数据手册
  • 价格&库存
74AXP1G09GSH 数据手册
74AXP1G09 Low-power 2-input AND gate with open-drain Rev. 2 — 17 December 2015 Product data sheet 1. General description The 74AXP1G09 is a single 2-input AND gate with open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits               Wide supply voltage range from 0.7 V to 2.75 V Low input capacitance; CI = 0.5 pF (typical) Low output capacitance; CO = 0.7 pF (typical) Low dynamic power consumption; CPD = 1.0 pF at VCC = 1.2 V (typical) Low static power consumption; ICC = 0.6 A (85 C maximum) High noise immunity Complies with JEDEC standard:  JESD8-12A.01 (1.1 V to 1.3 V)  JESD8-11A.01 (1.4 V to 1.6 V)  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A.01 (2.3 V to 2.7 V) ESD protection:  HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV  CDM JESD22-C101E exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Input accepts voltages up to 2.75 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C 74AXP1G09 Nexperia Low-power 2-input AND gate with open-drain 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AXP1G09GM 40 C to +85 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.5 mm 74AXP1G09GN 40 C to +85 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74AXP1G09GS 40 C to +85 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 74AXP1G09GX 40 C to +85 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8  0.8  0.35 mm SOT1226 4. Marking Table 2. Marking Type number Marking code[1] 74AXP1G09GM r9 74AXP1G09GN r9 74AXP1G09GS r9 74AXP1G09GX r9 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y A B A 1 2 4 1 Y 2 001aad598 Fig 1. Logic symbol 74AXP1G09 Product data sheet & 4 GND B 001aad600 001aad599 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 17 December 2015 Fig 3. Logic diagram © Nexperia B.V. 2017. All rights reserved 2 of 17 74AXP1G09 Nexperia Low-power 2-input AND gate with open-drain 6. Pinning information 6.1 Pinning $;3* $;3* $;3* %   9&& $   QF *1'   < %   9&& % $   QF *1'   < DDD Pin configuration SOT886 $  DDD Fig 5. Pin configuration SOT1115 and SOT1202  9&&  <  *1' DDD 7UDQVSDUHQWWRSYLHZ 7UDQVSDUHQWWRSYLHZ 7UDQVSDUHQWWRSYLHZ Fig 4.  Fig 6. Pin configuration SOT1226 (X2SON5) 6.2 Pin description Table 3. Pin description Symbol Pin Description XSON6 X2SON5 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. 5 - not connected VCC 6 5 supply voltage 7. Functional description Table 4. Function table[1] Input Output A B Y L L L L H L H L L H H Z [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state. 74AXP1G09 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 17 December 2015 © Nexperia B.V. 2017. All rights reserved 3 of 17 74AXP1G09 Nexperia Low-power 2-input AND gate with open-drain 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage Conditions VI < 0 V [1] VO < 0 V [1] Min Max Unit 0.5 +3.3 V 50 - 0.5 +3.3 50 - 0.5 +3.3 mA V mA V IO output current - 20 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 250 mW [1] VO = 0 V to VCC Tamb = 40 C to +85 C The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Tamb ambient temperature t/V input transition rise and fall rate 74AXP1G09 Product data sheet Min Max Unit 0.7 2.75 V 0 2.75 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 2.75 V 40 +85 C 0 200 ns/V VCC = 0.7 V to 2.75 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 17 December 2015 © Nexperia B.V. 2017. All rights reserved 4 of 17 74AXP1G09 Nexperia Low-power 2-input AND gate with open-drain 10. Static characteristics Table 7. Static characteristics At recommended operating conditions, unless otherwise specified; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Min HIGH-level input voltage VIH LOW-level input voltage VIL LOW-level output voltage VOL Unit Typ 25 C Max 25 C Max 85 C VCC = 0.75 V to 0.85 V 0.75VCC - - - V VCC = 1.1 V to 1.95 V 0.65VCC - - - V VCC = 2.3 V to 2.7 V 1.6 - - - V VCC = 0.75 V to 0.85 V - - 0.25VCC 0.25VCC V VCC = 1.1 V to 1.95 V - - 0.35VCC 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 0.7 V IO = 20 A; VCC = 0.7 V - 0.01 - - V IO = 100 A; VCC = 0.75 V - - 0.1 0.1 V IO = 2 mA; VCC = 1.1 V - - 0.275 0.275 V IO = 3 mA; VCC = 1.4 V - - 0.35 0.35 V IO = 4.5 mA; VCC = 1.65 V - - 0.45 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.7 0.7 V - 0.001 0.1 0.5 A II input leakage current VI = 0 V to 2.75 V; VCC = 0 V to 2.75 V [1] IOZ OFF-state output current VI = VIL; VO = 0 V to 2.75 V [1] - 0.02 0.1 0.5 A IOFF power-off leakage current VI or VO = 0 V to 2.75 V; VCC = 0 V [1] - 0.01 0.1 0.5 A IOFF additional power-off VI or VO = 0 V or 2.75 V; leakage current VCC = 0 V to 0.1 V [1] - 0.02 0.1 0.5 A ICC supply current VI = 0 V or VCC; IO = 0 A [1] - 0.01 0.3 0.6 A ICC additional supply current VI = VCC  0.5 V; IO = 0 A; VCC = 2.5 V - 2 100 150 A [1] All typical values are measured at VCC = 1.2 V. 74AXP1G09 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 17 December 2015 © Nexperia B.V. 2017. All rights reserved 5 of 17 74AXP1G09 Nexperia Low-power 2-input AND gate with open-drain 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13. Symbol Parameter propagation delay tpd Tamb = 25 C Conditions Tamb = 40 C to +85 C Unit Min Typ[1] Max Min Max 4 11 37 3 88 ns VCC = 1.1 V to 1.3 V 2.2 4.9 8.0 2.1 8.3 ns VCC = 1.4 V to 1.6 V 1.7 3.7 5.6 1.6 5.9 ns VCC = 1.65 V to 1.95 V 1.4 3.5 5.7 1.4 6.1 ns VCC = 2.3 V to 2.7 V 1.2 2.6 4.1 1.1 4.4 ns - - - 0.9 - ns A, B to Y; see Figure 7 [2][3] VCC = 0.75 V to 0.85 V VCC = 2.7 V; see Figure 7 [4] tt transition time CI input capacitance VI = 0 V or VCC; VCC = 0 V to 2.75 V - 0.5 - - - pF CO output capacitance - 0.7 - - - pF CPD power dissipation fi = 1 MHz; VI = 0 V to VCC capacitance VCC = 0.75 V to 0.85 V VO = 0 V; VCC = 0 V [5] - 0.9 - - - pF VCC = 1.1 V to 1.3 V - 1.0 - - - pF VCC = 1.4 V to 1.6 V - 1.0 - - - pF VCC = 1.65 V to 1.95 V - 1.1 - - - pF VCC = 2.3 V to 2.7 V - 1.3 - - - pF [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPZL and tPLZ. [3] For additional propagation delay (tPZL) values at different load capacitances see Figure 8 to Figure 12. [4] tt is the same as tTHL. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + CL  VCC2  fo where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V. N = number of inputs switching. 74AXP1G09 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 17 December 2015 © Nexperia B.V. 2017. All rights reserved 6 of 17 74AXP1G09 Nexperia Low-power 2-input AND gate with open-drain 12. Waveforms 9, $%LQSXW 90 *1' W3=/ W3/= 9&& 
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