74AXP1G58
Low-power configurable multiple function gate
Rev. 3 — 16 September 2015
Product data sheet
1. General description
The 74AXP1G58 is a configurable multiple function gate with Schmitt-trigger inputs. The
device can be configured as any of the following logic functions AND, OR, NAND, NOR,
XOR, inverter and buffer. All inputs can be connected directly to VCC or GND.
This device ensures very low static and dynamic power consumption across the entire
VCC range from 0.7 V to 2.75 V. This device is fully specified for partial power-down
applications using IOFF. The IOFF circuitry disables the output, preventing the potentially
damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.7 V to 2.75 V
Low input capacitance; CI = 0.5 pF (typical)
Low output capacitance; CO = 1.0 pF (typical)
Low dynamic power consumption; CPD = 2.7 pF at VCC = 1.2 V (typical)
Low static power consumption; ICC = 0.6 A (85 C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10% of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C
74AXP1G58
Nexperia
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AXP1G58GM
40 C to +85 C
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
74AXP1G58GN
40 C to +85 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
74AXP1G58GS
40 C to +85 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
74AXP1G58GX
40 C to +85 C
X2SON6
plastic thermal extremely thin small outline package;
no leads; 6 terminals; body 1 0.8 0.35 mm
SOT1255
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74AXP1G58GM
RK
74AXP1G58GN
RK
74AXP1G58GS
RK
74AXP1G58GX
RK
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
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&
Fig 1.
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DDE
Logic symbol
74AXP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 September 2015
©
Nexperia B.V. 2017. All rights reserved
2 of 18
74AXP1G58
Nexperia
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
$;3*
$;3*
%
%
&
$;3*
&
%
*1'
9&&
*1'
9&&
*1'
$
<
$
DDD
Pin configuration SOT886
<
<
DDD
Fig 3.
Pin configuration SOT1115
and SOT1202
9&&
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DDD
7UDQVSDUHQWWRSYLHZ
7UDQVSDUHQWWRSYLHZ
7UDQVSDUHQWWRSYLHZ
Fig 2.
&
Fig 4.
Pin configuration SOT1255
(X2SON6)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
B
1
data input
GND
2
ground (0 V)
A
3
data input
Y
4
data output
VCC
5
supply voltage
C
6
data input
7. Functional description
Table 4.
Function table[1]
Input
Output
C
B
A
Y
L
L
L
L
L
L
H
H
L
H
L
L
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
L
H
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level.
74AXP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 September 2015
©
Nexperia B.V. 2017. All rights reserved
3 of 18
74AXP1G58
Nexperia
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input NAND
see Figure 5
2-input NAND with both inputs inverted
see Figure 8
2-input AND with inverted input
see Figure 6 and Figure 7
2-input NOR with inverted input
see Figure 6 and Figure 7
2-input OR
see Figure 8
2-input OR with both inputs inverted
see Figure 5
2-input XOR
see Figure 9
Buffer
see Figure 10
Inverter
see Figure 11
9&&
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&
%
&
<
%
<
9&&
%
&
&
<
%
&
<
%
<
DDE
Fig 5.
2-input NAND gate or 2-input OR gate with
both inputs inverted
&
<
DDE
Fig 6.
2-input AND gate with inverted B input or
2-input NOR gate with inverted C input
9&&
9&&
$
&
$
&
<
$
<
$
&
&
<
$
&
<
<
$
DDE
Fig 7.
2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
&
<
DDE
Fig 8.
2-input OR gate or 2-input NAND gate with
both inputs inverted
9&&
9&&
%
%
&
<
&
$
<
$
<
DDE
DDE
Fig 9.
2-input XOR gate
74AXP1G58
Product data sheet
<
Fig 10. Buffer
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 September 2015
©
Nexperia B.V. 2017. All rights reserved
4 of 18
74AXP1G58
Nexperia
Low-power configurable multiple function gate
9&&
%
%
<
<
DDE
Fig 11. Inverter
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
Conditions
Min
Max
Unit
0.5
+3.3
V
50
-
[1]
0.5
+3.3
50
-
[1]
0.5
+3.3
V
-
20
mA
50
mA
VI < 0 V
VI
input voltage
IOK
output clamping current
VO
output voltage
IO
output current
ICC
supply current
-
VO < 0 V
VO = 0 V to VCC
mA
V
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
-
250
mW
[1]
Tamb = 40 C to +85 C
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
9. Recommended operating conditions
Table 7.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
Conditions
Product data sheet
Max
Unit
0.7
2.75
V
0
2.75
V
active mode
0
VCC
V
power-down mode; VCC = 0 V
0
2.75
V
40
+85
C
ambient temperature
74AXP1G58
Min
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 September 2015
©
Nexperia B.V. 2017. All rights reserved
5 of 18
74AXP1G58
Nexperia
Low-power configurable multiple function gate
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions, unless otherwise specified; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Tamb = 40 C to +85 C
Conditions
Min
Typ 25 C
Max 25 C
Max 85 C
0.3VCC
-
0.8VCC
0.8VCC
V
VCC = 1.1 V to 1.95 V
0.4VCC
-
0.7VCC
0.7VCC
V
VCC = 2.3 V to 2.7 V
0.9
-
1.7
1.7
V
0.2VCC
-
0.7VCC
0.7VCC
V
VCC = 1.1 V to 1.95 V
0.3VCC
-
0.6VCC
0.6VCC
V
VCC = 2.3 V to 2.7 V
0.7
-
1.5
1.5
V
VCC = 0.75 V to 0.85 V
0.06VCC
-
0.5VCC
0.5VCC
V
VCC = 1.1 V to 1.95 V
0.1VCC
-
0.4VCC
0.4VCC
V
VCC = 2.3 V to 2.7 V
0.2
-
1.0
1.0
V
positive-going
see Figure 12 and Figure 13
threshold voltage
VCC = 0.75 V to 0.85 V
VT+
negative-going
see Figure 12 and Figure 13
threshold voltage
VCC = 0.75 V to 0.85 V
VT
hysteresis
voltage
VH
VOH
HIGH-level
output voltage
LOW-level
output voltage
VOL
Unit
see Figure 12 and Figure 13
IO = 20 A; VCC = 0.7 V
-
0.69
-
-
V
IO = 100 A; VCC = 0.75 V
0.65
-
-
-
V
IO = 2 mA; VCC = 1.1 V
0.825
-
-
-
V
IO = 3 mA; VCC = 1.4 V
1.05
-
-
-
V
IO = 4.5 mA; VCC = 1.65 V
1.2
-
-
-
V
IO = 8 mA; VCC = 2.3 V
1.7
-
-
-
V
IO = 20 A; VCC = 0.7 V
-
0.01
-
-
V
IO = 100 A; VCC = 0.75 V
-
-
0.1
0.1
V
IO = 2 mA; VCC = 1.1 V
-
-
0.275
0.275
V
IO = 3 mA; VCC = 1.4 V
-
-
0.35
0.35
V
IO = 4.5 mA; VCC = 1.65 V
-
-
0.45
0.45
V
IO = 8 mA; VCC = 2.3 V
-
-
0.7
0.7
V
-
0.001
0.1
0.5
A
II
input leakage
current
VI = 0 V to 2.75 V;
VCC = 0 V to 2.75 V
[1]
IOFF
power-off
leakage current
VI or VO = 0 V to 2.75 V;
VCC = 0 V
[1]
-
0.01
0.1
0.5
A
IOFF
additional
power-off
leakage current
VI or VO = 0 V or 2.75 V;
VCC = 0 V to 0.1 V
[1]
-
0.02
0.1
0.5
A
ICC
supply current
VI = 0 V or VCC; IO = 0 A
[1]
-
0.01
0.3
0.6
A
ICC
additional supply VI = VCC 0.5 V; IO = 0 A;
current
VCC = 2.5 V
-
2
100
150
A
[1]
Typical values are measured at VCC = 1.2 V.
74AXP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 September 2015
©
Nexperia B.V. 2017. All rights reserved
6 of 18
74AXP1G58
Nexperia
Low-power configurable multiple function gate
10.1 Waveform transfer characteristics
92
97
9,
9+
97
9,
9+
97
97
92
PQD
PQD
Fig 12. Transfer characteristic
Fig 13. Definition of VT+, VT and VH
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 20.
Symbol Parameter
propagation delay
tpd
Tamb = 25 C
Conditions
Min
Max
Min
Max
VCC = 0.75 V to 0.85 V
3.0
14
46
1
152
ns
VCC = 1.1 V to 1.3 V
2.3
5.0
8.3
2.1
8.7
ns
VCC = 1.4 V to 1.6 V
1.9
3.7
5.6
1.7
6.0
ns
A, B and C to Y; see Figure 14
[2][3]
VCC = 1.65 V to 1.95 V
1.6
3.1
4.7
1.4
5.1
ns
VCC = 2.3 V to 2.7 V
1.3
2.4
3.5
1.1
3.9
ns
-
-
-
1.0
-
ns
-
0.5
-
-
-
pF
-
1.0
-
-
-
pF
VCC = 0.75 V to 0.85 V
-
2.5
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
2.6
-
-
-
pF
tt
transition time
VCC = 2.7 V; see Figure 14
CI
input capacitance
VI = 0 V or VCC; VCC = 0 V to 2.75 V
CO
output capacitance VO = 0 V; VCC = 0 V
CPD
power dissipation
capacitance
[1]
Tamb = 40 C to +85 C Unit
Typ[1]
fi = 1 MHz; VI = 0 V to VCC
[4]
[5]
VCC = 1.4 V to 1.6 V
-
2.7
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
2.9
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
3.3
-
-
-
pF
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
For additional propagation delay values at different load capacitances, see Figure 15 to Figure 19.
[4]
tt is the same as tTHL and tTLH.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + CL VCC2 fo where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching.
74AXP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 September 2015
©
Nexperia B.V. 2017. All rights reserved
7 of 18
74AXP1G58
Nexperia
Low-power configurable multiple function gate
11.1 Waveforms and graphs
9,
$%&LQSXW
90
90
9
W3+/
92+
W3/+
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