74HC10; 74HCT10
Triple 3-input NAND gate
Rev. 3 — 5 August 2016
Product data sheet
1. General description
The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that
enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For74HC10: CMOS level
For 74HCT10: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
74HC10D
Package
Temperature range
Name
Description
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Version
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT10D
74HC10DB
74HCT10DB
74HC10PW
74HCT10PW
74HC10; 74HCT10
Nexperia
Triple 3-input NAND gate
4. Functional diagram
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PQD
Fig 1.
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PQD
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
PQD
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
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+&7
+&
+&7
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9&&
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9&&
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*1'
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DDD
Fig 4.
DDD
Pin configuration SO14
Fig 5.
Pin configuration for (T)SSOP14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A, 2A, 3A
1, 3, 9
data input
1B, 2B, 3B
2, 4, 10
data input
GND
7
ground (0 V)
1C, 2C, 3C
13, 5, 11
data input
1Y, 2Y, 3Y
12, 6, 8
data output
VCC
14
supply voltage
74HC_HCT10
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 5 August 2016
©
Nexperia B.V. 2017. All rights reserved
2 of 14
74HC10; 74HCT10
Nexperia
Triple 3-input NAND gate
6. Functional description
Table 3.
Function selection[1]
Input
Output
nA
nB
nC
nY
L
X
X
H
X
L
X
H
X
X
L
H
H
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1]
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
-
20
mA
IO
output current
0.5 V < VO < VCC + 0.5 V
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
total power dissipation
Ptot
[2]
SO14 and (T)SSOP14
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74HC10
Min
Typ
74HCT
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
-
+125
40
-
+125
C
t/V
input transition rise and fall rate
74HC_HCT10
Product data sheet
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 5 August 2016
©
Nexperia B.V. 2017. All rights reserved
3 of 14
74HC10; 74HCT10
Nexperia
Triple 3-input NAND gate
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
74HC10
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4.0 mA; VCC = 4.5 V
3.98
4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
5.34
-
5.2
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
VI = VIH or VIL
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
0.1
-
1
-
1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
2.0
-
20
-
40
A
CI
input
capacitance
-
3.5
-
-
-
-
-
pF
74HC_HCT10
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 5 August 2016
©
Nexperia B.V. 2017. All rights reserved
4 of 14
74HC10; 74HCT10
Nexperia
Triple 3-input NAND gate
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
74HCT10
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA
3.98
4.32
-
3.84
-
3.7
-
V
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4 A; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
-
0.1
-
1
-
1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
ICC
additional
supply current
per input pin;
VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
-
150
540
-
675
-
735
A
CI
input
capacitance
-
3.5
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for test circuit, see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Max
(85 C)
Max
(125 C)
VCC = 2.0 V
-
30
95
120
145
ns
VCC = 4.5 V
-
11
19
24
29
ns
VCC = 5.0 V; CL = 15 pF
-
9
-
-
-
ns
-
9
16
20
25
ns
VCC = 2.0 V
-
19
75
95
110
ns
VCC = 4.5 V
-
7
15
19
22
ns
-
6
13
16
19
ns
-
12
-
-
-
pF
74HC10
tpd
propagation delay nA, nB to nY; see Figure 6
[1]
VCC = 6.0 V
tt
transition time
[2]
see Figure 6
VCC = 6.0 V
CPD
power dissipation
capacitance
74HC_HCT10
Product data sheet
per package; VI = GND to VCC
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 5 August 2016
©
Nexperia B.V. 2017. All rights reserved
5 of 14
74HC10; 74HCT10
Nexperia
Triple 3-input NAND gate
Table 7.
Dynamic characteristics …continued
GND = 0 V; CL = 50 pF; for test circuit, see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Max
(85 C)
Max
(125 C)
-
14
24
30
36
ns
-
11
-
-
-
ns
74HCT10
[1]
propagation delay nA, nB to nY; see Figure 6
tpd
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
[2]
CPD
power dissipation
capacitance
per package;
VI = GND to VCC 1.5 V
[3]
[1]
-
7
15
19
22
ns
-
14
-
-
-
pF
tpd is the same as tPHL and tPLH.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9O
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92+
W3/+
9<
90
9;
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