74HC4002D-Q100,118

74HC4002-Q100; 74HCT4002-Q100 Dual 4-input NOR gate Rev. 1 — 18 July 2012 Product data sheet 1. General description The 74HC4002-Q100; 74HCT4002-Q100 is a dual 4-input NOR gate. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Complies with JEDEC standard JESD7A  Low-power dissipation  Input levels:  For 74HC4002-Q100: CMOS level  For 74HCT4002-Q100: TTL level  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options 3. Ordering information Table 1. Ordering information Type number 74HC4002D-Q100 Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT4002D-Q100 74HC4002PW-Q100 40 C to +125 C 74HC4002-Q100; 74HCT4002-Q100 Nexperia Dual 4-input NOR gate 4. Functional diagram         $ % < &    '  $  % < &    '   DDD Fig 1. Functional diagram  Fig 2. $ % & <  ' $ % & <  ' DDD Logic symbol •   $   %  • <   &   ' DDD Fig 3. IEC Logic symbol Fig 4. DDD Logic diagram 5. Pinning information 5.1 Pinning +&4 +&74 <   9&& $   < %   ' &   & '   % QF  *1'  +&4 <   9&& $   < %   ' &   & '   %  $ QF   $  QF *1'   QF DDD DDD Fig 5. Pin configuration SOT108-1 74HC_HCT4002_Q100 Product data sheet Fig 6. Pin configuration SOT402-1 All information provided in this document is subject to legal disclaimers. Rev. 1 — 18 July 2012 © Nexperia B.V. 2017. All rights reserved 2 of 14 74HC4002-Q100; 74HCT4002-Q100 Nexperia Dual 4-input NOR gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1Y 1 data output 1A, 1B, 1C, 1D 2, 3, 4, 5 data input n.c. 6, 8 not connected GND 7 ground (0 V) 2Y 13 data output 2A, 2B, 2C, 2Y 9, 10, 11, 12 data input VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nC nD nY L L L L H H X X X L X H X X L X X H X L X X X H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC IGND Tstg storage temperature Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA supply current - 50 mA ground current 50 - mA 65 +150 C DIP14 package - 750 mW SO14, and (T)SSOP14 packages - 500 mW [2] total power dissipation Ptot Min [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 74HC_HCT4002_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 18 July 2012 © Nexperia B.V. 2017. All rights reserved 3 of 14 74HC4002-Q100; 74HCT4002-Q100 Nexperia Dual 4-input NOR gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC4002-Q100 Min Typ 74HCT4002-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC4002-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2 - 20 - 40 A 74HC_HCT4002_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 18 July 2012 © Nexperia B.V. 2017. All rights reserved 4 of 14 74HC4002-Q100; 74HCT4002-Q100 Nexperia Dual 4-input NOR gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min CI input capacitance Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max - 3.5 - - - - - pF 74HCT4002-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.84 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA - 0.15 0.26 - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2 - 20 - 40 A ICC additional supply current per input pin; VI = VCC  2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 45 162 - 203 - 221 A CI input capacitance - 3.5 - - - - - pF 74HC_HCT4002_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 18 July 2012 © Nexperia B.V. 2017. All rights reserved 5 of 14 74HC4002-Q100; 74HCT4002-Q100 Nexperia Dual 4-input NOR gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 8. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) VCC = 2.0 V - 30 100 125 150 ns VCC = 4.5 V - 11 20 25 30 ns VCC = 6.0 V - 9 17 21 26 ns - 9 - - - ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns - 6 13 16 19 ns - 16 - - - pF - 13 22 28 33 ns 74HC4002-Q100 tpd propagation delay nA, nB, nC or nD to nY; see Figure 7 [1] VCC = 5.0 V; CL = 15 pF tt transition time [2] see Figure 7 VCC = 6.0 V CPD power dissipation capacitance per package; VI = GND to VCC [3] 74HCT4002-Q100 tpd propagation delay nA, nB, nC or nD to nY; see Figure 7 [1] VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt CPD [1] transition time power dissipation capacitance - 11 - - - ns VCC = 4.5 V; see Figure 7 [2] - 7 15 19 22 ns per package; VI = GND to VCC  1.5 V [3] - 22 - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching;  (CL  VCC2  fo) = sum of outputs. 74HC_HCT4002_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 18 July 2012 © Nexperia B.V. 2017. All rights reserved 6 of 14 74HC4002-Q100; 74HCT4002-Q100 Nexperia Dual 4-input NOR gate 11. Waveforms 9, Q$Q%Q& Q'LQSXW 90 *1' W3+/ 92+ W3/+ 9< 90 Q