74HC21PW,118

74HC21 Dual 4-input AND gate Rev. 7 — 30 November 2015 Product data sheet 1. General description The 74HC21 is a dual 4-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Low-power dissipation  Complies with JEDEC standard no. 7A  ESD protection:  HBM JESD22-A114E exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC21D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC21DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HC21PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HC21 Nexperia Dual 4-input AND gate 4. Functional diagram $  %  < &    ' $  < &    %        '   $ %  ' $ % < &  ' DDE DDE Fig 1. < & Functional diagram Fig 2. Logic symbol    $   %   <  &   ' DDE Fig 3. IEC Logic symbol Fig 4. DDE Logic diagram 5. Pinning information 5.1 Pinning +& $   9&& %   ' QF   & &   QF '   % <   $ *1'   < +& $   9&& %   ' QF   & &   QF '   % <   $ *1'   < DDL DDE Fig 5. Pin configuration SOT108-1 74HC21 Product data sheet Fig 6. Pin configuration SOT337-1 and SOT402-1 All information provided in this document is subject to legal disclaimers. Rev. 7 — 30 November 2015 © Nexperia B.V. 2017. All rights reserved 2 of 14 74HC21 Nexperia Dual 4-input AND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 1B, 1C, 1D 1, 2, 4, 5 data input n.c. 3, 11 not connected 1Y 6 data output GND 7 ground (0 V) 2Y 8 data output 2A, 2B, 2C, 2D 9, 10, 12, 13 data input VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nC nD nY L X X X L X L X X L X X L X L X X X L L H H H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot SO14 and (T)SSOP14 packages [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 74HC21 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 30 November 2015 © Nexperia B.V. 2017. All rights reserved 3 of 14 74HC21 Nexperia Dual 4-input AND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions VCC supply voltage Min Typ Max Unit 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V Tamb ambient temperature - - 83 40 - +125 ns/V C 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 A CI input capacitance - 3.5 - - - - - pF 74HC21 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 30 November 2015 © Nexperia B.V. 2017. All rights reserved 4 of 14 74HC21 Nexperia Dual 4-input AND gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; test circuit see Figure 8. Symbol Parameter propagation delay tpd transition time tt power dissipation capacitance CPD 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 33 110 - 140 - 165 ns VCC = 4.5 V - 12 22 - 28 - 33 ns VCC = 6.0 V - 10 19 - 24 - 28 ns VCC = 5.0 V; CL = 15 pF - 10 - - - - - ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns - 15 - - - - - pF nA, nB, nC or nD to nY; see Figure 7 nY output; see Figure 7 [1] [2] [3] VI = GND to VCC [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching;  (CL  VCC2  fo) = sum of outputs. 74HC21 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 30 November 2015 © Nexperia B.V. 2017. All rights reserved 5 of 14 74HC21 Nexperia Dual 4-input AND gate 11. Waveforms 9, Q$Q%Q& Q'LQSXW 90 *1' W3+/ 92+ Q