74LV00
Quad 2-input NAND gate
Rev. 4 — 9 December 2015
Product data sheet
1. General description
The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC00 and 74HCT00.
The 74LV00 provides a quad 2-input NAND function.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LV00D
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV00DB
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LV00PW
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV00BQ
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
74LV00
Nexperia
Quad 2-input NAND gate
4. Functional diagram
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Fig 1.
PQD
Logic symbol
Fig 2.
PQD
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
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(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 4.
Pin configuration SO14 and (T)SSOP14
74LV00
Product data sheet
Fig 5.
Pin configuration DHVQFN14
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 December 2015
©
Nexperia B.V. 2017. All rights reserved
2 of 14
74LV00
Nexperia
Quad 2-input NAND gate
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A to 4A
1, 4, 9, 12
data input
1B to 4B
2, 5, 10, 13
data input
1Y to 4Y
3, 6, 8, 11
data output
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
Output
nA
nB
nY
L
X
H
X
L
H
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1]
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
VO = 0.5 V to (VCC + 0.5 V)
Min
Max
Unit
0.5
+7.0
V
-
20
mA
-
50
mA
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +125 C
SO14 package
[2]
-
500
mW
(T)SSOP14 package
[3]
-
500
mW
DHVQFN14 package
[4]
-
500
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 8 mW/K above 70 C.
[3]
Ptot derates linearly with 5.5 mW/K above 60 C.
[4]
Ptot derates linearly with 4.5 mW/K above 60 C.
74LV00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 December 2015
©
Nexperia B.V. 2017. All rights reserved
3 of 14
74LV00
Nexperia
Quad 2-input NAND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
[1]
Min
Typ
Max
Unit
1.0
3.3
5.5
V
VCC
supply voltage
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
C
t/V
input transition rise and fall rate
VCC = 1.0 V to 2.0 V
-
-
500
ns/V
VCC = 2.0 V to 2.7 V
-
-
200
ns/V
VCC = 2.7 V to 3.6 V
-
-
100
ns/V
VCC = 3.6 V to 5.5 V
-
-
50
ns/V
[1]
The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
74LV00
Product data sheet
Conditions
VCC = 1.2 V
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
0.9
-
-
0.9
-
V
VCC = 2.0 V
1.4
-
-
1.4
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
0.7VCC
-
V
VCC = 1.2 V
-
-
0.3
-
0.3
V
VCC = 2.0 V
-
-
0.6
-
0.6
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
-
IO = 100 A; VCC = 1.2 V
-
1.2
-
-
-
V
IO = 100 A; VCC = 2.0 V
1.8
2.0
-
1.8
-
V
IO = 100 A; VCC = 2.7 V
2.5
2.7
-
2.5
-
V
IO = 100 A; VCC = 3.0 V
2.8
3.0
-
2.8
-
V
IO = 100 A; VCC = 4.5 V
4.3
4.5
-
4.3
-
V
IO = 6 mA; VCC = 3.0 V
2.4
2.82
-
2.2
-
V
IO = 12 mA; VCC = 4.5 V
3.6
4.2
-
3.5
-
V
0.3VCC V
VI = VIH or VIL
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 December 2015
©
Nexperia B.V. 2017. All rights reserved
4 of 14
74LV00
Nexperia
Quad 2-input NAND gate
Table 6.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOL
40 C to +85 C
Conditions
LOW-level output voltage
Min
Typ[1]
40 C to +125 C Unit
Max
Min
Max
VI = VIH or VIL
IO = 100 A; VCC = 1.2 V
-
0
-
-
-
V
IO = 100 A; VCC = 2.0 V
-
0
0.2
-
0.2
V
IO = 100 A; VCC = 2.7 V
-
0
0.2
-
0.2
V
IO = 100 A; VCC = 3.0 V
-
0
0.2
-
0.2
V
IO = 100 A; VCC = 4.5 V
-
0
0.2
-
0.2
V
IO = 6 mA; VCC = 3.0 V
-
0.25
0.40
-
0.50
V
IO = 12 mA; VCC = 4.5 V
-
0.35
0.55
-
0.65
V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
20.0
-
40
A
ICC
additional supply current
per input; VI = VCC 0.6 V;
VCC = 2.7 V to 3.6 V
-
-
500
-
850
A
CI
input capacitance
-
3.5
-
-
-
pF
[1]
Typical values are measured at Tamb = 25 C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
tpd
propagation delay
40 C to +85 C
Conditions
power dissipation
capacitance
Unit
Min
Max
Min
Max
VCC = 1.2 V
-
45
-
-
-
ns
VCC = 2.0 V
-
15
26
-
31
ns
nA, nB to nY; see Figure 6
[2]
VCC = 2.7 V
CPD
40 C to +125 C
Typ[1]
-
11
18
-
23
ns
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
-
7
-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
9.0
15
-
18
ns
VCC = 4.5 V to 5.5 V
[3]
-
6.5
11
-
14
ns
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[4]
-
22
-
-
-
pF
[1]
All typical values are measured at Tamb = 25 C.
[2]
tpd is the same as tPLH and tPHL.
[3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
74LV00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 December 2015
©
Nexperia B.V. 2017. All rights reserved
5 of 14
74LV00
Nexperia
Quad 2-input NAND gate
11. Waveforms
9,
90
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W3+/
92+
90
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