74LVC08A
Quad 2-input AND gate
Rev. 7 — 19 April 2016
Product data sheet
1. General description
The 74LVC08A provides four 2-input AND gates.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC08AD
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVC08ADB
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LVC08APW
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVC08ABQ
40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
74LVC08A
Nexperia
Quad 2-input AND gate
4. Functional diagram
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Fig 1.
PQD
PQD
PQD
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one gate
5. Pinning information
5.1 Pinning
74LVC08A
1A
terminal 1
index area
14 VCC
74LVC08A
1
14 VCC
1B
2
13 4B
1B
2
13 4B
1Y
3
12 4A
1Y
3
12 4A
2A
4
11 4Y
2B
5
2Y
6
1
1A
5
10 3B
2Y
6
9
3A
GND
7
8
3Y
GND(1)
10 3B
9
8
2B
3Y
11 4Y
7
4
GND
2A
3A
001aac946
Transparent top view
001aac945
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and (T)SSOP14
74LVC08A
Product data sheet
Fig 5.
Pin configuration DHVQFN14
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 19 April 2016
©
Nexperia B.V. 2017. All rights reserved
2 of 15
74LVC08A
Nexperia
Quad 2-input AND gate
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A to 4A
1, 4, 9, 12
data input
1B to 4B
2, 5, 10, 13
data input
1Y to 4Y
3, 6, 8, 11
data output
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function selection[1]
Input
Output
nA
nB
nY
L
X
L
X
L
L
H
H
H
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO > VCC or VO < 0 V
VO
output voltage
output HIGH or LOW-state
IO
output current
VO = 0 V to VCC
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
[1]
Tamb = 40 C to +125 C
[2]
[3]
Min
Max
Unit
0.5
+6.5
50
-
0.5
+6.5
V
-
50
mA
0.5
VCC + 0.5
-
50
mA
-
100
mA
100
-
mA
-
500
mW
65
+150
C
V
mA
V
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
For SO14 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
74LVC08A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 19 April 2016
©
Nexperia B.V. 2017. All rights reserved
3 of 15
74LVC08A
Nexperia
Quad 2-input AND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Typ
Max
Unit
1.65
-
3.6
V
1.2
-
-
V
0
-
5.5
V
0
-
VCC
V
40
-
+125
C
VCC = 1.65 V to 2.7 V
0
-
20
ns/V
VCC = 2.7 V to 3.6 V
0
-
10
ns/V
functional
VI
input voltage
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise and fall rate
output HIGH or LOW-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
VOH
VOL
II
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output
voltage
LOW-level
output
voltage
40 C to +85 C
Conditions
VCC = 1.2 V
Product data sheet
Unit
Min
Max
Min
Max
1.08
-
-
1.08
-
V
0.65 VCC
-
-
0.65 VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 1.2 V
-
-
0.12
-
0.12
V
VCC = 1.65 V to 1.95 V
VCC = 1.65 V to 1.95 V
-
-
0.35 VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
0.35 VCC V
VCC 0.2
-
-
VCC 0.3
-
V
IO = 4 mA; VCC = 1.65 V
1.2
-
-
1.05
-
V
IO = 8 mA; VCC = 2.3 V
1.8
-
-
1.65
-
V
IO = 12 mA; VCC = 2.7 V
2.2
-
-
2.05
-
V
IO = 18 mA; VCC = 3.0 V
2.4
-
-
2.25
-
V
IO = 24 mA; VCC = 3.0 V
2.2
-
-
2.0
-
V
IO = 100 A;
VCC = 1.65 V to 3.6 V
-
-
0.2
-
0.3
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
-
0.65
V
IO = 8 mA; VCC = 2.3 V
-
-
0.6
-
0.8
V
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
VI = VIH or VIL
IO = 12 mA; VCC = 2.7 V
-
-
0.4
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
-
0.1
5
-
20
A
input leakage VCC = 3.6 V; VI = 5.5 V or GND
current
74LVC08A
40 C to +125 C
Typ[1]
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 19 April 2016
©
Nexperia B.V. 2017. All rights reserved
4 of 15
74LVC08A
Nexperia
Quad 2-input AND gate
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C
Min
Typ[1]
Max
Min
Max
Unit
ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.1
10
-
40
A
ICC
additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
-
5
500
-
5000
A
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
-
4.0
-
-
-
pF
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
propagation delay
tpd
40 C to +85 C
Conditions
Min
Max
Min
Max
-
11.0
-
-
-
ns
VCC = 1.65 V to 1.95 V
0.5
4.2
9.0
0.5
10.4
ns
VCC = 2.3 V to 2.7 V
1.0
2.5
6.9
1.0
8.0
ns
VCC = 2.7 V
1.5
2.5
4.8
1.5
5.6
ns
VCC = 3.0 V to 3.6 V
1.0
2.3
4.1
1.0
4.8
ns
-
-
1.0
-
1.5
ns
nA, nB to nY; see Figure 6
[2]
VCC = 1.2 V
tsk(o)
power dissipation
capacitance
CPD
[1]
output skew time
40 C to +125 C Unit
Typ[1]
VCC = 3.0 V to 3.6 V
[3]
per gate; VI = GND to VCC
[4]
VCC = 1.65 V to 1.95 V
-
4.4
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
7.7
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
10.5
-
-
-
pF
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
74LVC08A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 19 April 2016
©
Nexperia B.V. 2017. All rights reserved
5 of 15
74LVC08A
Nexperia
Quad 2-input AND gate
11. AC waveforms
9,
90
Q$Q%LQSXW
*1'
W 3+/
W 3/+
92+
Q
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