74LVC1G98GF,132

74LVC1G98 Low-power configurable multiple function gate Rev. 4 — 19 December 2016 Product data sheet 1. General description The 74LVC1G98 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected to VCC or GND. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits             Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V). 24 mA output drive (VCC = 3.0 V) ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C. 74LVC1G98 Nexperia Low-power configurable multiple function gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G98GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC1G98GV 40 C to +125 C SC-74 plastic surface mounted package; 6 leads SOT457 74LVC1G98GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm SOT886 74LVC1G98GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1  0.5 mm SOT891 74LVC1G98GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74LVC1G98GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 4. Marking Table 2. Marking Type number Marking code[1] 74LVC1G98GW V9 74LVC1G98GV V98 74LVC1G98GM V9 74LVC1G98GF V9 74LVC1G98GN V9 74LVC1G98GS V9 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram $   % & Fig 1.  <  DDG Logic symbol 74LVC1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 19 December 2016 © Nexperia B.V. 2017. All rights reserved 2 of 20 74LVC1G98 Nexperia Low-power configurable multiple function gate 6. Pinning information 6.1 Pinning /9&* /9&* %   & *1'   9&& $   < %   & *1'   9&& $  %   & *1'   9&& $   < < DDQ DDQ 7UDQVSDUHQWWRSYLHZ DDQ Fig 2.  /9&* Pin configuration SOT363 and SOT457 Fig 3. Pin configuration SOT886 7UDQVSDUHQWWRSYLHZ Fig 4. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input GND 2 ground (0 V) A 3 data input Y 4 data output VCC 5 supply voltage C 6 data input 7. Functional description Table 4. Function table[1] Input Output C B A Y L L L H L L H H L H L L L H H L H L L H H L H L H H L H H H H L [1] H = HIGH voltage level; L = LOW voltage level. 74LVC1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 19 December 2016 © Nexperia B.V. 2017. All rights reserved 3 of 20 74LVC1G98 Nexperia Low-power configurable multiple function gate 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input MUX with inverted output see Figure 5 2-input NAND see Figure 6 2-input NOR with one input inverted see Figure 7 2-input AND with one input inverted see Figure 7 2-input NAND with one input inverted see Figure 8 2-input OR with one input inverted see Figure 8 2-input NOR see Figure 9 Buffer see Figure 10 Inverter see Figure 11 9&& 9&& %  %  & < $ & $     $ & < < $       DDG Fig 5. 2-input MUX with inverted output & < DDG Fig 6. 2-input NAND gate 9&& $ & < $ & < $       9&& & < % & < % & < %       2-input AND gate with input A inverted or 2-input NOR gate with inverted C input < DDG DDG Fig 7. & Fig 8. 2-input OR gate with input B inverted or 2-input NAND gate with input C inverted 9&& % % & <       9&& & & <       < DDG Fig 9. 2-input NOR gate 74LVC1G98 Product data sheet & < DDG Fig 10. Buffer All information provided in this document is subject to legal disclaimers. Rev. 4 — 19 December 2016 © Nexperia B.V. 2017. All rights reserved 4 of 20 74LVC1G98 Nexperia Low-power configurable multiple function gate 9&& % % <       < DDG Fig 11. Inverter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions Min Max Unit 0.5 +6.5 V 50 - 0.5 +6.5 V - 50 mA Active mode [1][2] 0.5 +6.5 V Power-down mode [1][2] 0.5 +6.5 V VI < 0 V [1] VO > VCC or VO < 0 V mA IO output current - 50 mA ICC supply current - +100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 250 mW total power dissipation Ptot VO = 0 V to VCC Tamb = 40 C to +125 C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Conditions Active mode VCC = 0 V; Power-down mode 74LVC1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 19 December 2016 Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V 0 - VCC V 0 - 5.5 V 40 - +125 C © Nexperia B.V. 2017. All rights reserved 5 of 20 74LVC1G98 Nexperia Low-power configurable multiple function gate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter LOW-level output voltage VOL VOH HIGH-level output voltage 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.7 V IO = 8 mA; VCC = 2.3 V - - 0.3 - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.8 V VCC  0.1 - - VCC  0.1 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 0.95 - V IO = 8 mA; VCC = 2.3 V 1.9 - - 1.7 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V IO = 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V VI = VCC or GND VI = VCC or GND IO = 100 A; VCC = 1.65 V to 5.5 V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - 0.1 1 - 1 A IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 2 - 2 A ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 4 - 4 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 - 500 A CI input capacitance - 2.5 - - - pF [1] Typical values are measured at maximum VCC and Tamb = 25 C. 74LVC1G98 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 19 December 2016 © Nexperia B.V. 2017. All rights reserved 6 of 20 74LVC1G98 Nexperia Low-power configurable multiple function gate 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.0 6.0 14.4 1.0 18.0 ns VCC = 2.3 V to 2.7 V 0.5 3.5 8.3 0.5 10.4 ns VCC = 2.7 V 0.5 4.2 8.5 0.5 10.6 ns VCC = 3.0 V to 3.6 V 0.5 3.8 6.3 0.5 7.9 ns VCC = 4.5 V to 5.5 V 0.5 3.0 5.1 0.5 6.4 ns - 20 - - - pF [2] propagation delay A, B, C to Y; see Figure 12 tpd power dissipation capacitance CPD [3] VCC = 3.3 V; VI = GND to VCC [1] Typical values are measured at nominal VCC and at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL [3] 40 C to +125 C Unit Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 12. Waveforms 9, $%&LQSXW 90 90 *1' W 3+/ W 3/+ 92+ 90