74LVC1G58GW-Q100H

74LVC1G58-Q100 Low-power configurable multiple function gate Rev. 2 — 9 December 2016 Product data sheet 1. General description The 74LVC1G58-Q100 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Wide supply voltage range from 1.65 V to 5.5 V  5 V tolerant input/output for interfacing with 5 V logic  High noise immunity  Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V).  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  24 mA output drive (VCC = 3.0 V)  CMOS low power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V 74LVC1G58-Q100 Nexperia Low-power configurable multiple function gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVC1G58GW-Q100 40 C to +125 C 74LVC1G58GV-Q100 40 C to +125 C Description Version SC-88 plastic surface-mounted package; 6 leads SOT363 TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457 4. Marking Table 2. Marking Type number Marking code[1] 74LVC1G58GW-Q100 YK 74LVC1G58GV-Q100 V58 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram $   % & Fig 1.  <  DDE Logic symbol 6. Pinning information 6.1 Pinning /9&*4 %   & *1'   9&& $   < DDD Fig 2. Pin configuration SOT363 and SOT457 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 December 2016 © Nexperia B.V. 2017. All rights reserved 2 of 17 74LVC1G58-Q100 Nexperia Low-power configurable multiple function gate 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input GND 2 ground (0 V) A 3 data input Y 4 data output VCC 5 supply voltage C 6 data input 7. Functional description Table 4. Function table[1] Inputs Output C B A Y L L L L L L H H L H L L L H H H H L L H H L H H H H L L H H H L [1] H = HIGH voltage level; L = LOW voltage level 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input NAND see Figure 3 2-input NAND with both inputs inverted see Figure 6 2-input AND with inverted input see Figure 4 and 5 2-input NOR with inverted input see Figure 4 and 5 2-input OR see Figure 6 2-input OR with both inputs inverted see Figure 3 2-input XOR see Figure 7 Buffer see Figure 8 Inverter see Figure 9 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 December 2016 © Nexperia B.V. 2017. All rights reserved 3 of 17 74LVC1G58-Q100 Nexperia Low-power configurable multiple function gate 9&& % & % & < % <       9&& % & & < < % & % <       < DDE DDE Fig 3. & 2-input NAND gate or 2-input OR with both inputs inverted Fig 4. 2-input AND gate with inverted B input or 2-input NOR gate with inverted C input 9&& 9&& $ & $ & < $ <       $ & & < $ & < < $       < DDE DDE Fig 5. & 2-input AND gate with inverted C input or 2-input NOR gate with inverted A input Fig 6. 2-input OR gate or 2-input NAND gate with both inputs inverted 9&& 9&& % % & <       & $ < < $       DDE Fig 7. < DDE 2-input XOR gate Fig 8. Buffer 9&& % % <       < DDE Fig 9. Inverter 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 December 2016 © Nexperia B.V. 2017. All rights reserved 4 of 17 74LVC1G58-Q100 Nexperia Low-power configurable multiple function gate 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - 0.5 +6.5 V mA - 50 mA Active mode [1][2] 0.5 +6.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA VO > VCC or VO < 0 V IO output current ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 250 mW [1] VO = 0 V to VCC Tamb = 40 C to +125 C [3] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb Conditions Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V Active mode 0 - VCC V Power-down mode; VCC = 0 V 0 - 5.5 V 40 - +125 C ambient temperature 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 December 2016 © Nexperia B.V. 2017. All rights reserved 5 of 17 74LVC1G58-Q100 Nexperia Low-power configurable multiple function gate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Typ[1] Max Unit IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V Conditions Tamb = 40 C to +85 C VOL VOH LOW-level output voltage VI = VT+ or VT IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V HIGH-level output voltage VI = VT+ or VT IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 - - V IO = 8 mA; VCC = 2.3 V 1.9 - - V IO = 12 mA; VCC = 2.7 V 2.2 - - V IO = 24 mA; VCC = 3.0 V 2.3 - - V IO = 32 mA; VCC = 4.5 V 3.8 - - V - 0.1 1 A II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 2 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 4 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 A CI input capacitance - 2.5 - pF IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.7 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.8 V IO = 32 mA; VCC = 4.5 V - - 0.8 V VCC  0.1 - - V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V Tamb = 40 C to +125 C VOL VOH LOW-level output voltage VI = VT+ or VT HIGH-level output voltage VI = VT+ or VT IO = 100 A; VCC = 1.65 V to 5.5 V 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 December 2016 © Nexperia B.V. 2017. All rights reserved 6 of 17 74LVC1G58-Q100 Nexperia Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Min Typ[1] Max - - 1 A power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 2 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 4 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 500 A Symbol Parameter Conditions II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V IOFF [1] Unit Typical values are measured at maximum VCC and Tamb = 25 C. 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions A, B, C to Y; see Figure 10 [1] Max Min Max 1.0 6.0 14.4 1.0 18.0 ns VCC = 2.3 V to 2.7 V 0.5 3.5 8.3 0.5 10.4 ns VCC = 2.7 V 0.5 4.2 8.5 0.5 10.6 ns VCC = 3.0 V to 3.6 V 0.5 3.8 6.3 0.5 7.9 ns 0.5 3.0 5.1 0.5 6.4 ns - 20 - - - pF VCC = 4.5 V to 5.5 V power dissipation capacitance Typ[1] [2] VCC = 1.65 V to 1.95 V CPD 40 C to +125 C Unit Min VCC = 3.3 V; VI = GND to VCC [3] Typical values are measured at nominal VCC and at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 74LVC1G58_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 December 2016 © Nexperia B.V. 2017. All rights reserved 7 of 17 74LVC1G58-Q100 Nexperia Low-power configurable multiple function gate 12. Waveforms 9, $%&LQSXW 90 90 *1' W 3+/ W 3/+ 92+ 90