74ALVC16244DGG,112

74ALVC16244; 74ALVCH16244 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state Rev. 5 — 15 January 2019 Product data sheet 1. General description The 74ALVC16244; 74ALVCH16244 is a 16-bit non-inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-state outputs are controlled by the output enable inputs 1OE, 2OE, 3OE and 4OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. The 74ALVCH16244 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. The 74ALVC16244 has 5 V tolerant inputs. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Direct interface with TTL levels (2.7 V to 3.6 V) Bus hold on data inputs (74ALVCH16244 only) Output drive capability 50 Ω transmission lines at 85 °C Current drive ±24 mA at 3.0 V Complies with JEDEC standard no. 8-1A ESD protection: • HBM JESD22-A114-A exceeds 2000 V • MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74ALVC16244DL -40 °C to +85 °C SSOP48 plastic shrink small outline package; 48 leads; SOT370-1 body width 7.5 mm 74ALVC16244DGG -40 °C to +85 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm 74ALVCH16244DGG Version SOT362-1 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 4. Functional diagram 1A0 1A1 1A2 1A3 1OE 47 2 46 3 44 5 43 6 1Y0 3A0 1Y1 3A1 1Y2 3A2 1Y3 3A3 1 3OE 36 13 35 14 33 16 32 17 3Y0 3Y1 1 1OE 48 2OE 25 3OE 24 4OE 3Y2 3Y3 1A0 1A1 25 1A2 1A3 2A0 2A1 41 40 8 9 2Y0 2Y1 4A0 4A1 19 30 29 20 2A0 2A1 4Y0 2A2 2A3 3A0 4Y1 3A1 2A2 2A3 2OE 38 37 11 12 2Y2 2Y3 48 4A2 4A3 4OE 22 27 23 26 3A2 4Y2 3A3 4A0 4A1 4Y3 4A2 24 4A3 EN1 EN2 EN3 EN4 47 46 Logic symbol 2 1 3 44 5 43 6 41 40 1 8 2 9 38 11 37 12 36 35 1 3 13 14 33 16 32 17 30 29 1 4 19 20 27 22 26 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 001aae231 mna996 Fig. 1. 1 Fig. 2. IEC logic symbol VCC data input to internal circuit mna705 Fig. 3. Bus hold circuit 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 2 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 5. Pinning information 5.1. Pinning 74ALVC16244 74ALVCH16244 Fig. 4. 1OE 1 48 2OE 1Y0 2 47 1A0 1Y1 3 46 1A1 GND 4 45 GND 1Y2 5 44 1A2 1Y3 6 43 1A3 VCC 7 42 VCC 2Y0 8 41 2A0 2Y1 9 40 2A1 GND 10 39 GND 2Y2 11 38 2A2 2Y3 12 37 2A3 3Y0 13 36 3A0 3Y1 14 35 3A1 GND 15 34 GND 3Y2 16 33 3A2 3Y3 17 32 3A3 VCC 18 31 VCC 4Y0 19 30 4A0 4Y1 20 29 4A1 GND 21 28 GND 4Y2 22 27 4A2 4Y3 23 26 4A3 40E 24 25 3OE Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE, 3OE, 4OE 1, 48, 25, 24 output enable inputs (active LOW) 1A0, 1A1, 1A2, 1A3 47, 46, 44, 43 data inputs 2A0, 2A1, 2A2, 2A3 41, 40, 38, 37 data inputs 3A0, 3A1, 3A2, 3A3 36, 35, 33, 32 data inputs 4A0, 4A1, 4A2, 4A3 30, 29, 27, 26 data inputs 1Y0, 1Y1, 1Y2, 1Y3 2, 3, 5, 6 data outputs 2Y0, 2Y1, 2Y2, 2Y3 8, 9, 11, 12 data outputs 3Y0, 3Y1, 3Y2, 3Y3 13, 14, 16, 17 data outputs 4Y0, 4Y1, 4Y2, 4Y3 19, 20, 22, 23 data outputs GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 supply voltage 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 3 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Output Input nOE nAn nYn L L L L H H H X Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage Conditions Min -0.5 Max Unit +4.6 V 74ALVCH16244; data inputs; [1] -0.5 VCC + 0.5 V 74ALVC16244; data inputs; [1] -0.5 +5.5 V control inputs [1] -0.5 +5.5 V [1] -0.5 VO output voltage IIK input clamping current VI < 0 V -50 - mA IOK output clamping current VO > VCC or VO < 0 V - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation SSOP48 package - 850 mW TSSOP48 package - 600 mW [1] [2] Tamb = -40 °C to +85 °C VCC + 0.5 V [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SSOP48 packages: above 55 °C derate linearly with 11.3 mW/K. For TSSOP48 packages: above 55 °C derate linearly with 8 mW/K. 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 4 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC Min Max Unit VCC = 2.5 V: CL = 30 pF 2.3 2.7 V VCC = 3.3 V: CL = 50 pF 3.0 3.6 V maximum speed performance supply voltage LOW-voltage applications VI input voltage 1.2 3.6 V 74ALVCH16244; data inputs; 0 VCC V 74ALVC16244; data inputs; 0 5.5 V control inputs 0 5.5 V 0 VCC V VO output voltage Tamb ambient temperature in free air -40 +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 20 ns/V VCC = 3.0 V to 3.6 V 0 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Tamb = -40 °C to +85 °C Symbol Parameter Conditions Min Typ [1] Max VIH HIGH-level input voltage VCC = 1.2 V VCC - - V VCC = 1.8 V 0.7 × VCC 0.9 - V VCC = 2.3 to 2.7 V 1.7 1.2 - V VCC = 2.7 to 3.6 V VIL VOH VOL LOW-level input voltage HIGH-level output voltage LOW-level output voltage 74ALVC_ALVCH16244 Product data sheet Unit 2.0 1.5 - V VCC = 1.2 V - - GND V VCC = 1.8 V - 0.9 VCC = 2.3 to 2.7 V - 1.2 0.7 V VCC = 2.7 to 3.6 V - 1.5 0.8 V IO = -100 μA; VCC = 1.8 V to 3.6 V VCC - 0.2 VCC - V IO = -6 mA; VCC = 1.8 V VCC - 0.4 VCC - 0.10 - V IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V IO = -12 mA; VCC = 2.3 V VCC - 0.5 VCC - 0.17 - V IO = -18 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V IO = 100 μA; VCC = 1.8 V to 3.6 V - GND 0.20 V IO = 6 mA; VCC = 1.8 V - 0.09 0.30 V IO = 6 mA; VCC = 2.3 V - 0.07 0.20 V IO = 12 mA; VCC = 2.3 V - 0.15 0.40 V IO = 18 mA; VCC = 2.3 V - 0.23 0.60 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V 0.2 × VCC V VI = VIH or VIL VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 5 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state Symbol Parameter Min Typ [1] Max II input leakage current 74ALVCH16244; data inputs; VI = VCC or GND; VCC = 1.8 V to 3.6 V - 0.1 5 μA 74ALVC16244; data inputs; VI = 5.5 V or GND; VCC = 1.8 V to 3.6 V - 0.1 5 μA control inputs; VI = 5.5 V or GND; VCC = 1.8 V to 3.6 V - 0.1 5 μA Conditions Unit bus hold LOW current VCC = 2.3 V; VI = 0.7 V [2] 45 - - μA VCC = 3.0 V; VI = 0.8 V [2] 75 150 - μA bus hold HIGH current VCC = 2.3 V; VI = 1.7 V [2] -45 - - μA VCC = 3.0 V; VI = 2.0 V [2] -75 -175 - μA IBHLO bus hold LOW overdrive current VCC = 2.7 V [2] 300 - - μA VCC = 3.6 V [2] 450 - - μA IBHHO bus hold HIGH overdrive current VCC = 2.7 V [2] -300 - - μA VCC = 3.6 V [2] -450 - - μA OFF-state output current VCC = 1.8 to 2.7 V; VI = VIH or VIL; VO = VCC or GND - 0.1 5 μA VCC = 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 μA VCC = 1.8 to 2.7 V; VI = VCC or GND; IO = 0 A - 0.1 20 μA VCC = 2.3 to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA 74ALVCH16244 - 150 750 μA 74ALVC16244 - 5 500 μA control pin - 5 500 μA - 5.0 - pF IBHL IBHH IOZ ICC supply current ΔICC CI [1] [2] additional supply current per input pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V input capacitance All typical values are measured at Tamb = 25 °C. Valid for data inputs of bus hold parts. 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 6 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit, see Fig. 7. Symbol tpd ten Parameter propagation delay enable time Conditions Tamb = -40 °C to +85 °C Min Typ [1] VCC = 1.2 V - 5.8 - ns VCC = 1.8 V 1.5 2.8 5.1 ns VCC = 2.3 V to 2.7 V 1.0 1.9 3.7 ns VCC = 2.7 V 1.0 2.1 3.6 ns VCC = 3.0 V to 3.6 V 1.0 1.9 3.0 ns VCC = 1.2 V - 8.4 - ns VCC = 1.8 V 1.5 3.8 7.1 ns VCC = 2.3 V to 2.7 V 1.0 2.5 4.9 ns VCC = 2.7 V 1.0 2.9 4.9 ns 1.0 2.3 4.0 ns VCC = 1.2 V - 5.9 - ns VCC = 1.8 V 1.5 3.1 5.4 ns VCC = 2.3 V to 2.7 V 1.0 2.1 4.1 ns VCC = 2.7 V 1.0 3.0 4.5 ns VCC = 3.0 V to 3.6 V 1.0 2.7 4.1 ns outputs enabled - 25 - pF outputs disabled - 4 - pF nAn to nYn; see Fig. 5 nOE to nYn; see Fig. 6 CPD [1] [2] [3] [4] [5] disable time power dissipation capacitance nOE to nYn; see Fig. 6 per buffer; VI = GND to VCC Max [2] [3] VCC = 3.0 V to 3.6 V tdis Unit [4] [5] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = total load switching outputs 2 Σ(CL × VCC × fo) = sum of the outputs 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 7 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 10.1. Waveforms and test circuit VI nAn input VM VM GND tPLH tPHL VOH VM nYn output VM VOL mna171 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 5. Inputs nAn to output nYn propagation delays VI nOE input VM GND t PLZ nYn output LOW-to-OFF OFF-to-LOW t PZL VCC VM VX VOL t PZH t PHZ nYn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs disabled outputs enabled 001aae014 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. OFF-state to HIGH or LOW and HIGH or LOW to OFF-state propagation delays Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 VCC 0.5 x VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 1.8 V VCC 0.5 x VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V VCC 0.5 x VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 8 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 1.8 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74ALVC_ALVCH16244 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 9 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 11. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3 ) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 Fig. 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Package outline SSOP48 (SOT370-1) 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 10 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 Fig. 9. References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Package outline TSSOP48 (SOT362-1) 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 11 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC_ALVCH16244 v.5 20190115 Product data sheet - 74ALVC_ALVCH16244 v.4 Modifications: • 74ALVC_ALVCH16244 v.4 20170612 Modifications: • • Type number 74ALVCH16244DL (SOT370-1) removed. Product data sheet - 74ALVC_ALVCH16244 v.3 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74ALVC_ALVCH16244 v.3 20030514 Product specification - 74ALVC_ALVCH16244 v.2 74ALVC_ALVCH16244 v.2 19980629 Product specification - 74ALVCH16244 v.1 74ALVCH16244 v.1 19970321 Product specification - - 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 12 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74ALVC_ALVCH16244 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 13 / 14 74ALVC16244; 74ALVCH16244 Nexperia 2.5 V / 3.3 V 16-bit buffer/line driver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 8 11. Package outline........................................................ 10 12. Abbreviations............................................................ 12 13. Revision history........................................................12 14. Legal information......................................................13 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 15 January 2019 74ALVC_ALVCH16244 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 January 2019 © Nexperia B.V. 2019. All rights reserved 14 / 14