74AVC16835ADGG,118

74AVC16835A 18-bit registered driver with Dynamic Controlled Outputs; 3-state Rev. 6 — 24 September 2018 Product data sheet 1. General description The 74AVC16835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient. See Fig. 5 for typical curves. 2. Features and benefits • • • • • • • • Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standards: • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8-1A (2.7 V to 3.6 V) CMOS low power consumption Input/output tolerant up to 3.6 V Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation Low inductance multiple VCC and GND pins to minimize noise and ground bounce Power off disables 74AVC16835A outputs, permitting Live Insertion Integrated input diodes to minimize input overshoot and undershoot 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AVC16835ADGG -40 °C to + 85 °C Description TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm Version SOT364-1 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 4. Functional diagram OE CP 27 OE 30 CP 28 LE LE A1 D LE A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Y1 CP to the 17 other channels Fig. 1. aaa-027574 Logic diagram VCC A1 002aac725 Fig. 3. Typical input (data or control) 74AVC16835A Product data sheet 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 EN1 2C3 G3 G2 3D 1 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 aaa-027575 Fig. 2. Logic symbol (IEEE/IEC) All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 2 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 5. Pinning information 5.1. Pinning 74AVC16835A n.c. 1 56 GND n.c. 2 55 n.c. Y1 3 54 A1 GND 4 53 GND Y2 5 52 A2 Y3 6 51 A3 VCC 7 50 VCC Y4 8 49 A4 Y5 9 48 A5 Y6 10 47 A6 GND 11 46 GND Y7 12 45 A7 Y8 13 44 A8 Y9 14 43 A9 Y10 15 42 A10 Y11 16 41 A11 Y12 17 40 A12 GND 18 39 GND Y13 19 38 A13 Y14 20 37 A14 Y15 21 36 A15 VCC 22 35 VCC Y16 23 34 A16 Y17 24 33 A17 GND 25 32 GND Y18 26 31 A18 OE 27 30 CP LE 28 29 GND aaa-029061 Fig. 4. Pin configuration SOT364-1 (TSSOP56) 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 3 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 5.2. Pin description Table 2. Pin description Symbol Pin Description A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 data outputs n.c. 1, 2, 55 not connected LE 28 latch enable input OE 27 output enable input (active LOW) CP 30 clock input GND 4, 11, 18, 25, 29, 32, 39, 46, 53, 56 ground (0 V) VCC 7, 22, 35, 50 supply voltage 6. Functional description Table 3. Function selection H = HIGH voltage level; L = LOW voltage level; X = Don’t care; Z = high-impedance OFF-state; ↑ = LOW to HIGH level transition. Outputs Inputs OE LE CP An Yn H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H L L H X Y0 [1] L L L X Y0 [2] [1] [2] Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. Output level before the indicated steady-state input conditions were established. 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 4 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +4.6 V -50 - -0.5 +4.6 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage output HIGH or LOW [1] -0.5 output 3-state [1] -0.5 +4.6 V - ±50 mA VI < 0 V [1] VCC + 0.5 V IO output current ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 600 mW [1] [2] VO = 0 V to VCC mA Tamb = −40 °C to +85 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Above 55 °C the value of Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Min Typ Max Unit for low-voltage applications 1.2 - 3.6 V according to JEDEC Low Voltage Standards 1.65 - 1.95 V 2.3 - 2.7 V 3.0 - 3.6 V 0 - 3.6 V output HIGH or LOW 0 - VCC V output 3-state 0 - 3.6 V −40 - +85 °C Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.3 V 0 - 30 ns/V VCC = 2.3 V to 3.0 V 0 - 20 ns/V VCC = 3.0 V to 3.6 V 0 - 10 ns/V 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 5 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; Tamb = −40 °C to +85 °C; Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max VIH VCC = 1.2 V VCC - - V 0.65 × VCC 0.9 - V VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 3.0 V to 3.6 V 2.0 1.5 - V VCC = 1.2 V - - GND V VCC = 1.65 V to 1.95 V - 0.9 VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 3.0 V to 3.6 V - 1.5 0.8 V IO = -100 μA; VCC = 1.65 V to 3.6 V VCC - 0.20 VCC - V IO = -4 mA; VCC = 1.65 V VCC - 0.45 VCC - 0.10 - V IO = -8 mA; VCC = 2.3 V VCC - 0.55 VCC - 0.28 - V IO = -12 mA; VCC = 3.0 V VCC - 0.70 VCC - 0.32 - V IO = 100 μA; VCC = 1.65 V to 3.6 V - GND 0.20 V IO = 4 mA; VCC = 1.65 V - 0.10 0.45 V IO = 8 mA; VCC = 2.3 V - 0.26 0.55 V IO = 12 mA; VCC = 3.0 V HIGH-level input voltage VIL LOW-level input voltage VOH VOL HIGH-level output voltage LOW-level output voltage VCC = 1.65 V to 1.95 V Unit 0.35 × VCC V VI = VIH or VIL VI = VIH or VIL - 0.36 0.70 V II input leakage current VI = VCC or GND; VCC = 1.65 V to 3.6 V - 0.1 2.5 μA IOFF power-off leakage current VI or VO = 3.6 V; VCC = 0 V - 0.1 ±10 μA IIHZ/IILZ power-off leakage current VCC = 1.65 V to 3.6 V; VI = VCC or GND - 0.1 12.5 μA IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND VCC = 1.65 V to 2.7 V - 0.1 5 μA VCC = 3.0 V to 3.6 V - 0.1 10 μA VCC = 1.65 V to 2.7 V - 0.1 20 μA VCC = 3.0 V to 3.6 V - 0.2 40 μA - 3.8 - pF ICC supply current CI [1] VI = VCC or GND; IO = 0 A input capacitance All typical values are measured at Tamb = 25 °C. 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 6 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 9.1. Dynamic Controlled Output graphs A Dynamic Controlled Output (DCO) circuit is designed in. During the transition, it initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Fig. 5 show VOL vs. IOL and VOH vs. IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DCO circuit provides a maximum dynamic drive that is equivalent to a high drive standard output device. aaa-028429 3.5 VOL output 3 voltage (V) 2.5 VOH output 3 voltage (V) 2.5 2 2 1.5 1.5 1 0 VCC = 2.5 V 50 100 150 200 250 IOL output current (mA) a. LOW-level output current. Fig. 5. VCC = 2.5 V VCC = 1.8 V 0.5 VCC = 1.8 V 0 VCC = 3.3 V 1 VCC = 3.3 V 0.5 aaa-028430 3.5 0 -250 -200 -150 -100 -50 0 IOH output current (mA) b. HIGH-level output current. Output current as a function of output voltage. 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 7 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 12. Symbol Parameter Conditions tpd An to Yn; see Fig. 6 propagation delay Min Typ [1] Max - 5.2 - ns VCC = 1.4 V to 1.6 V 1.6 3.6 5.1 ns VCC = 1.65 V to 1.95 V 1.3 2.1 4.2 ns VCC = 2.3 V to 2.7 V 1.0 1.7 3.0 ns VCC = 3.0 V to 3.6 V 0.9 1.5 2.5 ns [2] VCC = 1.2 V LE to Yn; see Fig. 7 [2] VCC = 1.2 V - 4.2 - ns VCC = 1.4 V to 1.6 V 1.6 2.8 4.6 ns VCC = 1.65 V to 1.95 V 1.3 2.2 4.0 ns VCC = 2.3 V to 2.7 V 1.1 1.9 3.5 ns VCC = 3.0 V to 3.6 V 0.9 1.6 2.9 ns - 4.3 - ns VCC = 1.4 V to 1.6 V 1.6 2.9 4.6 ns VCC = 1.65 V to 1.95 V 1.5 2.2 3.7 ns VCC = 2.3 V to 2.7 V 1.0 1.8 3.0 ns 0.8 1.7 2.7 ns - 6.3 - ns VCC = 1.4 V to 1.6 V 2.5 4.4 7.6 ns VCC = 1.65 V to 1.95 V 2.2 3.1 5.8 ns VCC = 2.3 V to 2.7 V 1.5 2.5 4.5 ns VCC = 3.0 V to 3.6 V 1.2 2.1 4.0 ns - 5.5 - ns VCC = 1.4 V to 1.6 V 2.2 4.1 7.6 ns VCC = 1.65 V to 1.95 V 2.0 3.1 5.6 ns VCC = 2.3 V to 2.7 V 1.2 2.2 4.5 ns VCC = 3.0 V to 3.6 V 1.1 2.6 4.8 ns VCC = 1.65 V to 1.95 V 2.0 - - ns VCC = 2.3 V to 2.7 V 1.2 - - ns VCC = 3.0 V to 3.6 V 1.0 - - ns VCC = 1.65 V to 1.95 V 2.0 - - ns VCC = 2.3 V to 2.7 V 1.2 - - ns VCC = 3.0 V to 3.6 V 1.0 - - ns CP to Yn; see Fig. 9 [2] VCC = 1.2 V VCC = 3.0 V to 3.6 V ten enable time OE to Yn; see Fig. 11 [2] VCC = 1.2 V tdis disable time OE to Yn; see Fig. 11 VCC = 1.2 V tW pulse width Unit [2] CP HIGH or LOW; see Fig. 9. LE HIGH; see Fig. 7. 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 8 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state Symbol Parameter Conditions tsu An to CP; see Fig. 10 set-up time VCC = 1.2 V Min Typ [1] Max Unit - 0.0 - ns VCC = 1.4 V to 1.6 V 0.2 0.0 - ns VCC = 1.65 V to 1.95 V 0.0 -0.2 - ns VCC = 2.3 V to 2.7 V 0.0 -0.2 - ns VCC = 3.0 V to 3.6 V 0.0 -0.3 - ns An to LE; see Fig. 8 VCC = 1.2 V th hold time - 1.5 - ns VCC = 1.4 V to 1.6 V 1.6 0.9 - ns VCC = 1.65 V to 1.95 V 1.1 0.6 - ns VCC = 2.3 V to 2.7 V 0.7 0.3 - ns VCC = 3.0 V to 3.6 V 1.0 0.5 - ns - 0.1 - ns VCC = 1.4 V to 1.6 V 0.7 0.3 - ns VCC = 1.65 V to 1.95 V 0.7 0.3 - ns VCC = 2.3 V to 2.7 V 0.7 0.3 - ns VCC = 3.0 V to 3.6 V 1.3 0.6 - ns - -0.7 - ns VCC = 1.4 V to 1.6 V 0.0 -0.3 - ns VCC = 1.65 V to 1.95 V 0.2 -0.2 - ns VCC = 2.3 V to 2.7 V 0.2 0.0 - ns VCC = 3.0 V to 3.6 V 0.3 0.8 - ns VCC = 1.65 V to 1.95 V 250 - - MHz VCC = 2.3 V to 2.7 V 400 - - MHz 500 - - MHz outputs enabled - 25 - pF outputs disabled - 6 - pF An to CP; see Fig. 10 VCC = 1.2 V An to LE; see Fig. 8 VCC = 1.2 V fmax maximum frequency CP; see Fig. 9 VCC = 3.0 V to 3.6 V power dissipation capacitance per buffer; VI = GND to VCC CPD [1] [2] [3] [3] Typical values are measured at Tamb = 25 °C and VCC = 1.5 V, 1.8 V, 2.5 V and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching 2 Σ(CL x VCC x fo) = sum of the outputs. 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 9 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 10.1. Waveforms and test circuit An input VI LE input GND VI VM tPHL Yn output tPLH Input (An) to output (Yn) propagation delay tPLH VM Yn output VOL VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. tPHL VOH VOH VM VM tW GND 002aac726 Fig. 6. VM aaa-027577 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Latch enable input (LE) pulse width, the latch enable input to output (Yn) propagation delays 1 / fmax VI An input GND VI LE input GND VM CP input VM tw th th tsu tsu VM Yn output aaa-027578 GND tPLH tPHL VOH VM VOL 002aac729 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Data set-up and hold times, An input to LE input CP input VI VM VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 8. VM The clock (CP) to output (Yn) propagation delays, the clock pulse width and the maximum clock frequency VI VM tsu th tsu th GND OE input VI An input GND VOH Yn output VOL 002aac730 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. output LOW-to-OFF OFF-to-LOW VI VM tPLZ GND tPZL VX tPHZ output HIGH-to-OFF OFF-to-HIGH VCC VM VOL tPZH VY outputs enabled VM outputs disabled 002aac731 Fig. 11. 3-state enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY ≤ 2.3 V VCC 0.5 x VCC 0.5 x VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V VCC 0.5 x VCC 0.5 x VCC VOL + 0.15 V VOH - 0.15 V 3.0 V to 3.6 V VCC 0.5 x VCC 0.5 x VCC VOL + 0.3 V VOH - 0.3 V Product data sheet GND outputs enabled Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 10. Data set-up and hold times, An input to CP input 74AVC16835A VOH All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 10 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 12. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH ≤ 2.3 V VCC ≤ 2.0 ns 30 pF 1000 Ω open 2 x VCC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 x VCC GND 3.0 V to 3.6 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 x VCC GND 74AVC16835A Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 11 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 11. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 13. Package outline SOT364-1 (TSSOP56) 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 12 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DCO Dynamic Controlled Output DUT Device Under Test 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVC16835A v.6 20180924 Product data sheet - 74AVC16835A v.5 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74AVC16835ADGV (SOT481-2) removed. 74AVC16835A v.5 20020315 Product data sheet - 74AVC16835A v.4 74AVC16835A v.4 20000725 Product specification - 74AVC16835A v.3 74AVC16835A v.3 20000502 Preliminary specification - 74AVC16835 v.2 74AVC16835 v.2 19990405 Preliminary specification - 74AVC_AVCH16835 v.1 74AVC_AVCH16835 v.1 19981207 Objective specification - - 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 13 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 14 / 15 74AVC16835A Nexperia 18-bit registered driver with Dynamic Controlled Outputs; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 4 6. Functional description................................................. 4 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................5 9. Static characteristics....................................................6 9.1. Dynamic Controlled Output graphs..............................7 10. Dynamic characteristics..............................................8 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 12 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 24 September 2018 74AVC16835A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 September 2018 © Nexperia B.V. 2018. All rights reserved 15 / 15 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74AVC16835ADGG,112 74AVC16835ADGG,118 74AVC16835ADGV,112 74AVC16835ADGV,118