74LVC2G240GM,125

74LVC2G240 Dual inverting buffer/line driver; 3-state Rev. 11 — 30 July 2019 Product data sheet 1. General description The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pins nOE causes the outputs to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G240 as a translator in a mixed 3.3 V and 5 V environment. It is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G240DP -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G240DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74LVC2G240GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 74LVC2G240GF -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm SOT1089 74LVC2G240GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm SOT1116 74LVC2G240GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT1203 4. Marking Table 2. Marking codes Type number Marking code [1] 74LVC2G240DP V240 74LVC2G240DC V40 74LVC2G240GT V40 74LVC2G240GF V2 74LVC2G240GN V2 74LVC2G240GS V2 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram EN 1OE 1A 1Y EN 2OE 2A 2Y 001aah782 Fig. 1. Logic symbol 74LVC2G240 Product data sheet 001aah783 Fig. 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 2 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 6. Pinning information 6.1. Pinning 74LVC2G240 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 74LVC2G240 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 001aaf076 Transparent top view 001aaf075 Fig. 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig. 4. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 (XSON8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1OE 1 output enable input 1OE (active LOW) 1A 2 data input 2Y 3 data output GND 4 ground (0 V) 2A 5 data input 1Y 6 data output 2OE 7 output enable input 2OE (active LOW) VCC 8 supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Output Input nOE nA nY L L H L H L H X Z 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 3 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage Enable mode [1] -0.5 VCC + 0.5 V Disable mode [1] -0.5 +6.5 V Power-down mode; VCC = 0 V [1] -0.5 +6.5 V VI < 0 V [1] IO output current - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] VO = 0 V to VCC mA Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT505-2 (TSSOP8) packages: Ptot derates linearly with 4.6 mW/K above 96 °C. For SOT765-1 (VSSOP8) packages: Ptot derates linearly with 4.9 mW/K above 99 °C. For SOT833-1 (XSON8) packages: Ptot derates linearly with 3.1 mW/K above 68 °C. For SOT1089 (XSON8) packages: Ptot derates linearly with 4.0 mW/K above 88 °C. For SOT1116 (XSON8) packages: Ptot derates linearly with 4.2 mW/K above 90 °C. For SOT1203 (XSON8) packages: Ptot derates linearly with 3.6 mW/K above 81 °C. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate 74LVC2G240 Product data sheet Conditions Min Max Unit 1.65 5.5 V 0 5.5 V VCC = 1.65 V to 5.5 V; Enable mode 0 VCC V VCC = 1.65 V to 5.5 V; Disable mode 0 5.5 V VCC = 0 V; Power-down mode 0 5.5 V -40 +125 °C VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 4 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage VOL LOW-level output voltage VOH HIGH-level output voltage Conditions Tamb = -40 °C to +85 °C VCC = 1.65 V to 1.95 V Tamb = -40 °C to +125 °C Min Typ [1] Max Min Max Unit 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.3 - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V - - 0.35VCC V VI = VIH or VIL VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 5.5 V VCC - 0.1 - - VCC - 0.1 - V IO = -4 mA; VCC = 1.65 V 1.2 - - 0.95 - V IO = -8 mA; VCC = 2.3 V 1.9 - - 1.7 - V IO = -12 mA; VCC = 2.7 V 2.2 - - 1.9 - V IO = -24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = -32 mA; VCC = 4.5 V 3.8 - - 3.4 - V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±1 - ±1 μA IOZ OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - ±0.1 ±2 - ±2 μA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±2 - ±2 μA ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 4 - 4 μA ΔICC additional supply current per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 - 500 μA CI input capacitance - 2 - - - pF [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 5 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7. Symbol Parameter tpd propagation delay Conditions Tamb = -40 °C to +85 °C Min Typ [1] Max Min Max VCC = 1.65 V to 1.95 V 1.0 4.1 9.5 1.0 11.9 ns VCC = 2.3 V to 2.7 V 0.5 2.6 5.2 0.5 6.5 ns VCC = 2.7 V 1.0 3.0 5.5 1.0 6.9 ns VCC = 3.0 V to 3.6 V 0.5 2.5 4.6 0.5 5.8 ns 0.5 2.0 4.0 0.5 5.0 ns VCC = 1.65 V to 1.95 V 1.5 4.5 10.3 1.5 12.9 ns VCC = 2.3 V to 2.7 V 1.0 2.9 5.6 1.0 7.0 ns VCC = 2.7 V 1.5 3.4 5.6 1.5 7.0 ns VCC = 3.0 V to 3.6 V 0.5 2.5 4.7 0.5 5.9 ns VCC = 4.5 V to 5.5 V 0.5 2.0 3.8 0.5 4.8 ns VCC = 1.65 V to 1.95 V 1.0 3.5 11.6 1.0 14.1 ns VCC = 2.3 V to 2.7 V 0.5 1.9 5.8 0.5 7.6 ns VCC = 2.7 V 1.0 2.8 4.5 1.0 5.8 ns VCC = 3.0 V to 3.6 V 1.0 2.7 4.4 1.0 5.7 ns VCC = 4.5 V to 5.5 V 0.5 1.9 3.4 0.5 4.6 ns output enabled - 18 - - - pF output disabled - 5 - - - pF nA to nY; see Fig. 5 [2] VCC = 4.5 V to 5.5 V ten enable time tdis disable time CPD [1] [2] [3] [4] [5] power dissipation capacitance Tamb = Unit -40 °C to +125 °C nOE to nY; see Fig. 6 nOE to nY; see Fig. 6 per buffer; VI = GND to VCC [3] [4] [5] Typical values are measured at nominal VCC and at Tamb = 25 °C. tpd is the same as tPLH and tPHL ten is the same as tPZH and tPZL tdis is the same as tPLZ and tPHZ CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of outputs. 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 6 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 11.1. Waveforms and test circuit VI VM nA input VM GND t PHL t PLH VOH VM VM nY output VOL mna960 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. The data input (nA) to output (nY) propagation delays VI nOE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PHZ output HIGH-to-OFF OFF-to-HIGH VOH t PZH VY VM GND outputs enabled outputs enabled outputs disabled mna961 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. 3-state enable and disable times Table 9. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 4.5 V to 5.5 V 0.5 × VCC 0.5 × VCC VOL + 0.3 V VOH - 0.3 V 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 7 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 10. Test data Supply voltage Input Load VCC VI CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC 30 pF 1 kΩ open GND 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 6V 4.5 V to 5.5 V VCC 50 pF 500 Ω open GND 2 × VCC 74LVC2G240 Product data sheet VEXT All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 8 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 pin 1 index (A3) A1 θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 Fig. 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Package outline SOT505-2 (TSSOP8) 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 9 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D SOT765-1 E A X c y HE v A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 detail X 4 e L w bp 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A max. max nom min 1 A1 A2 0.15 0.85 0.00 0.60 A3 0.12 D(1) E(2) 0.27 0.23 2.1 2.4 0.17 0.08 1.9 2.2 bp c e HE 0.5 3.2 3.0 L 0.4 Lp Q 0.40 0.21 0.15 0.19 v w y 0.2 0.08 0.1 Z(1) θ 0.4 8° 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version SOT765-1 Fig. 9. References IEC JEDEC JEITA sot765-1_po European projection Issue date 07-06-02 16-05-31 MO-187 Package outline SOT765-1 (VSSOP8) 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 10 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig. 10. Package outline SOT833-1 (XSON8) 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 11 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Fig. 11. Package outline SOT1089 (XSON8) 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 12 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 e1 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1116_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1116 Fig. 12. Package outline SOT1116 (XSON8) 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 13 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 1 2 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1203_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1203 Fig. 13. Package outline SOT1203 (XSON8) 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 14 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G240 v.11 20190730 Product data sheet - Modifications: • • 74LVC2G240 v.10 20181101 Modifications: • • • 74LVC2G240 v.10 Type number 74LVC2G240GM (SOT902-2/XQFN8) removed. Table 5: Derating values for Ptot total power dissipation updated. Product data sheet - 74LVC2G240 v.9 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LVC2G240GD (SOT996-2) removed. 74LVC2G240 v.9 20161215 Modifications: • 74LVC2G240 v.8 20130408 Modifications: • 74LVC2G240 v.7 20120622 Modifications: • 74LVC2G240 v.6 20111128 Modifications: • 74LVC2G240 v.5 20100915 74LVC2G240 v.4 Product data sheet - 74LVC2G240 v.8 Table 7: The maximum limits for leakage current and supply current have changed. Product data sheet - 74LVC2G240 v.7 For type number 74LVC2G240GD XSON8U has changed to XSON8. Product data sheet - 74LVC2G240 v.6 For type number 74LVC2G240GM the SOT code has changed to SOT902-2. - 74LVC2G240 v.5 Product data sheet - 74LVC2G240 v.4 20080229 Product data sheet - 74LVC2G240 v.3 74LVC2G240 v.3 20071005 Product data sheet - 74LVC2G240 v.2 74LVC2G240 v.2 20060728 Product data sheet - 74LVC2G240 v.1 74LVC2G240 v.1 20030311 Product specification - - 74LVC2G240 Product data sheet Product data sheet Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 15 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. 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It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 16 / 17 74LVC2G240 Nexperia Dual inverting buffer/line driver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 7 12. Package outline.......................................................... 9 13. Abbreviations............................................................ 15 14. Revision history........................................................15 15. Legal information......................................................16 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 July 2019 74LVC2G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 30 July 2019 © Nexperia B.V. 2019. All rights reserved 17 / 17 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74LVC2G240GS,115 74LVC2G240DC,125 74LVC2G240DP,125 74LVC2G240GM,125 74LVC2G240GT,115 74LVC2G240GF,115 74LVC2G240GD,125 74LVC2G240GN,115