74LVC3G16DPH

74LVC3G16 Triple buffer Rev. 2 — 11 October 2016 Product data sheet 1. General description The 74LVC3G16 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G16 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits            Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 74LVC3G16 Nexperia Triple buffer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC3G16DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC3G16GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35  1  0.5 mm SOT1089 74LVC3G16GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6  1.6  0.5 mm SOT902-2 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC3G16DP YU 74LVC3G16GF YU 74LVC3G16GM YU [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram  $ <  < $ $ <  $ DDK DDK Fig 1. Logic symbol 74LVC3G16 Product data sheet < Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 October 2016 DDF Fig 3. Logic diagram (one gate) © Nexperia B.V. 2017. All rights reserved 2 of 15 74LVC3G16 Nexperia Triple buffer 6. Pinning information 6.1 Pinning /9&* $   9&& <   < $   $ *1'   < /9&* $   9&& <   < $   $ *1'   < DDD 7UDQVSDUHQWWRSYLHZ DDD Pin configuration SOT505-2 (TSSOP8) Fig 5. Pin configuration SOT1089 (XSON8) /9&* <  $ <  9&& WHUPLQDO LQGH[DUHD  $   <   $ *1'  Fig 4. DDD 7UDQVSDUHQWWRSYLHZ Fig 6. Pin configuration SOT902-2 (XQFN8) 6.2 Pin description Table 3. Pin description Symbol Pin Description SOT505-2 and SOT1089 SOT902-2 1A, 2A, 3A 1, 3, 6 7, 5, 2 data input 1Y, 2Y, 3Y 7, 5, 2 1, 3, 6 data output GND 4 4 ground (0 V) VCC 8 8 supply voltage 74LVC3G16 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 October 2016 © Nexperia B.V. 2017. All rights reserved 3 of 15 74LVC3G16 Nexperia Triple buffer 7. Functional description Table 4. Function table[1] Input nA Output nY L L H H [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current Conditions input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage Active mode Power-down mode Max Unit +6.5 V 50 - [1] 0.5 +6.5 - 50 [1] 0.5 VCC + 0.5 V [1][2] 0.5 +6.5 V - 50 mA VI < 0 V VI Min 0.5 VO = 0 V to VCC mA V mA IO output current ICC supply current - 100 mA IGND ground current 100 - mA Ptot total power dissipation - 250 mW Tstg storage temperature 65 +150 C Tamb = 40 C to +125 C [3] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For XSON8, XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Tamb ambient temperature t/V input transition rise and fall rate 74LVC3G16 Product data sheet Min Max Unit 1.65 5.5 V 0 5.5 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V 40 +125 VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 October 2016 © C Nexperia B.V. 2017. All rights reserved 4 of 15 74LVC3G16 Nexperia Triple buffer 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit Tamb = 40 C to +85 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7  VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3  VCC V VCC  0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 - - V IO = 8 mA; VCC = 2.3 V 1.9 - - V IO = 12 mA; VCC = 2.7 V 2.2 - - V IO = 24 mA; VCC = 3.0 V 2.3 - - V IO = 32 mA; VCC = 4.5 V 3.8 - - V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V VOL LOW-level output voltage 0.35  VCC V VCC = 1.65 V to 1.95 V VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - 0.1 5 A IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 10 A ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC  0.6 V; IO = 0 A - 5 500 A CI input capacitance VCC = 3.3 V; VI = GND to VCC - 2.5 - pF 74LVC3G16 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 October 2016 © Nexperia B.V. 2017. All rights reserved 5 of 15 74LVC3G16 Nexperia Triple buffer Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max 0.65  VCC - - V Unit Tamb = 40 C to +125 C HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7  VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3  VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V LOW-level output voltage VOL 0.35  VCC V VCC  0.1 - - V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V VI = VIH or VIL IO = 4 mA; VCC = 1.65 V - - 0.7 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.8 V IO = 32 mA; VCC = 4.5 V - - 0.8 V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 20 A IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - - 20 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 40 A ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC  0.6 V; IO = 0 A - - 5000 A [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 74LVC3G16 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 October 2016 © Nexperia B.V. 2017. All rights reserved 6 of 15 74LVC3G16 Nexperia Triple buffer 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.8 8.6 1.0 10.8 ns VCC = 2.3 V to 2.7 V 0.5 2.4 4.4 0.5 5.5 ns VCC = 2.7 V 0.5 2.5 5.0 0.5 6.3 ns VCC = 3.0 V to 3.6 V 0.5 2.2 4.1 0.5 5.1 ns VCC = 4.5 V to 5.5 V 0.5 1.9 3.2 0.5 4.0 ns - 14 - - - pF propagation delay nA to nY; see Figure 7 tpd power dissipation capacitance CPD 40 C to +125 C Unit Typ[1] VI = GND to VCC; VCC = 3.3 V [2] [3] [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 74LVC3G16 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 October 2016 © Nexperia B.V. 2017. All rights reserved 7 of 15 74LVC3G16 Nexperia Triple buffer 12. AC waveforms 9, Q$LQSXW 90 9(;7 90 9&& *1' W3/+ W3+/ * 92+ 90 Q