74AHCT139D-Q100J

74AHC139-Q100; 74AHCT139-Q100 Dual 2-to-4 line decoder/demultiplexer Rev. 1 — 5 June 2013 Product data sheet 1. General description The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device has two independent decoders. Each decoder accepts two binary weighted inputs (nA0 and nA1) and provides four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Balanced propagation delays  All inputs have Schmitt-trigger actions  Inputs accept voltages higher than VCC  Input levels:  For 74AHC139-Q100: CMOS level  For 74AHCT139-Q100: TTL level  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options 74AHC139-Q100; 74AHCT139-Q100 Nexperia Dual 2-to-4 line decoder/demultiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC139D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74AHC139PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74AHC139-Q100 74AHCT139-Q100 74AHCT139D-Q100 74AHCT139PW-Q100 40 C to +125 C 4. Functional diagram 1 1E 1Y0 2 3 1A0 1Y1 1A1 1Y2 1Y3 2Y0 14 13 2A0 2Y1 2A1 2Y2 2Y3 4 5 6 2 3 1 DX 0 0 1 G 3 1 2 0 3 7 5 6 7 2 3 1 X/Y 0 1 1 2 2 EN 3 4 5 6 7 12 11 14 10 13 9 15 DX 0 0 1 G 3 1 2 0 2E 15 4 3 12 11 10 9 14 13 15 X/Y 0 1 2 2 EN (a) mna779 1 3 (b) 12 11 10 9 mna781 a = demultiplexer and b = decoder Fig 1. Logic symbol 74AHC_AHCT139_Q100 Product data sheet Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 5 June 2013 © Nexperia B.V. 2017. All rights reserved 2 of 16 74AHC139-Q100; 74AHCT139-Q100 Nexperia Dual 2-to-4 line decoder/demultiplexer 2 1A0 3 1A1 1 1E 14 2A0 DECODER 1Y0 4 1Y1 5 1Y2 6 1Y3 7 2Y0 12 13 2A1 2Y1 11 DECODER 2Y2 10 2Y3 15 9 2E mna780 Fig 3. Functional diagram 5. Pinning information 5.1 Pinning $+&4 $+&74 (   9&& $   ( $   $