74AHCT594DB,118

74AHC594; 74AHCT594 8-bit shift register with output register Rev. 02 — 9 June 2008 Product data sheet 1. General description The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register. 2. Features n n n n n n n n n Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Wide supply voltage range from 2.0 V to 5.5 V 8-bit serial-in, parallel-out shift register with storage Independent direct overriding clears on shift and storage registers Independent clocks for shift and storage registers Latch-up performance exceeds 100 mA per JESD78 Class II Input levels: u For 74AHC594: CMOS level u For 74AHCT594: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Applications n Serial-to parallel data conversion n Remote control holding register 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC594D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74AHC594DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74AHC594PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74AHC594BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 74AHCT594D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74AHCT594DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74AHCT594PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74AHCT594BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 74AHC594 74AHCT594 5. Functional diagram DS SHCP SHR 14 11 8-STAGE SHIFT REGISTER 10 9 STCP STR 12 13 8-BIT STORAGE REGISTER 15 1 2 3 4 5 6 7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Fig 1. Q7S mbc320 Functional diagram © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 2 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register SHCP STCP STR 11 12 STCP Q7S 9 DS SHR Fig 2. C2 10 R1 SRG8 11 Q0 1 Q1 2 Q2 3 Q3 2 4 Q4 3 5 Q5 4 6 Q6 7 Q7 SHCP DS C1/ 14 1D 15 2D 1 5 6 7 13 9 STR mbc319 Fig 3. Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7S IEC logic symbol STAGES 1 TO 6 STAGE 0 D Q0 mbc322 Logic symbol DS R2 12 15 14 10 SHR 13 Q D STAGE 7 Q FFSH0 D Q7S Q FFSH7 CP CP R R SHCP SHR D D Q FFST0 Q FFST7 CP CP R R STCP STR Q0 Fig 4. Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc321 Logic diagram © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 3 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register 6. Pinning information 6.1 Pinning 74AHC594 74AHCT594 Q1 1 16 VCC Q2 2 15 Q0 Q3 3 14 DS Q4 4 13 STR Q5 5 12 STCP Q6 6 11 SHCP Q7 7 10 SHR GND 8 9 Q7S 001aae343 Fig 5. Pin configuration SO16 terminal 1 index area 1 74AHC594 74AHCT594 16 VCC Q1 74AHC594 74AHCT594 Q2 2 15 Q0 Q3 3 14 DS 2 16 VCC 15 Q0 Q4 4 13 STR Q3 3 14 DS Q5 5 Q4 4 13 STR Q6 6 Q5 5 12 STCP Q7 7 Q6 6 11 SHCP Q7 7 10 SHR GND 8 Q7S 11 SHCP 10 SHR 9 9 12 STCP GND(1) Q7S Q2 8 1 GND Q1 001aae345 Transparent top view 001aae344 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 6. Pin configuration (T)SSOP16 Fig 7. Pin configuration DHVQFN16 © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 4 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register 6.2 Pin description Table 2. Pin description Symbol Pin Description Q1 1 parallel data output Q2 2 parallel data output Q3 3 parallel data output Q4 4 parallel data output Q5 5 parallel data output Q6 6 parallel data output Q7 7 parallel data output GND 8 ground (0 V) Q7S 9 serial data output SHR 10 shift register reset input (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input STR 13 storage register reset input (active LOW) DS 14 serial data input Q0 15 parallel data output VCC 16 supply voltage 7. Functional description Function table[1] Table 3. Input Output Function SHCP STCP SHR STR DS Q7S Qn X X X X L NC X X X L X NC L a LOW-state on STR only affects the storage register X ↑ L H X L L empty shift register loaded into storage register ↑ X H X H Q6S NC logic HIGH level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X ↑ H H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages ↑ ↑ H H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages [1] L a LOW-state on SHR only affects the shift register H = HIGH voltage state; L = LOW voltage state; ↑ = LOW to HIGH transition; X = don’t care; NC = no change; © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 5 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register SHCP DS STCP SHR STR Q0 Q1 Q6 Q7 Q7S mbc323 Fig 8. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI Conditions Min Max Unit supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V −20 - mA −20 +20 mA input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] VO = −0.5 V to (VCC + 0.5 V) IIK IO output current −25 +25 mA ICC supply current - +75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For (T)SSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 6 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register 9. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 74AHC594 VCC supply voltage 2.0 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.5 V - - 20 ns/V 74AHCT594 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74AHC594 VIH VIL VOH VOL HIGH-level input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 7 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions VI = 5.5 V or GND; VCC = 0 V to 5.5 V −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - - 0.1 - 1.0 - 2.0 µA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA CI input capacitance - 3 10 - 10 - 10 pF VI = VCC or GND 74AHCT594 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −8.0 mA; VCC = 4.5 V VOL 3.94 - - 3.80 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 8 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 µA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF VI = VCC or GND 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max - 5.2 8.5 2.2 9.7 2.2 10.6 ns - 7.4 11.5 3.0 13.2 3.0 14.3 ns CL = 15 pF - 3.8 6.3 1.7 7.2 1.7 7.8 ns CL = 50 pF - 4.8 8.0 2.4 9.1 2.4 10.0 ns 74AHC594 tPLH LOW to HIGH SHCP to Q7S; see Figure 9 propagation VCC = 3.0 V to 3.6 V delay CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 8 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 5.1 8.3 2.3 9.5 2.3 10.6 ns CL = 50 pF - 7.3 11.9 3.3 13.6 3.3 14.7 ns CL = 15 pF - 3.5 5.7 1.8 6.5 1.8 7.1 ns CL = 50 pF - 4.8 7.8 2.6 9.0 2.6 9.8 ns - 5.5 8.9 2.3 10.2 2.3 11.0 ns - 7.4 12.1 3.0 13.9 3.0 15.1 ns CL = 15 pF - 4.1 6.7 1.9 7.6 1.9 8.2 ns CL = 50 pF - 5.4 8.8 2.5 10.1 2.5 11.0 ns CL = 15 pF - 5.5 9.1 2.4 10.4 2.4 11.3 ns CL = 50 pF - 7.3 12.0 3.2 13.8 3.2 15.0 ns CL = 15 pF - 3.7 6.0 1.9 6.9 1.9 7.5 ns CL = 50 pF - 5.2 8.5 2.6 9.7 2.6 10.5 ns CL = 15 pF - 5.7 9.5 2.3 10.8 2.3 11.7 ns CL = 50 pF - 7.5 12.2 3.6 14.0 3.6 15.2 ns CL = 15 pF - 4.1 6.7 2.0 7.6 2.0 8.2 ns CL = 50 pF - 5.4 8.8 2.8 10.1 2.8 11.0 ns CL = 15 pF - 5.8 9.6 2.8 11.0 2.8 12.0 ns CL = 50 pF - 7.7 12.5 3.8 14.4 3.8 15.6 ns CL = 15 pF - 4.1 7.2 2.2 8.2 2.2 8.9 ns CL = 50 pF - 5.4 9.4 3.0 10.7 3.0 11.6 ns VCC = 3.0 V to 3.6 V 80 125 - 70 - 65 - MHz VCC = 4.5 V to 5.5 V 90 170 - 80 - 70 - MHz STCP to Qn; see Figure 10 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tPHL HIGH to LOW SHCP to Q7S; see Figure 9 propagation VCC = 3.0 V to 3.6 V delay CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V STCP to Qn; see Figure 10 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V SHR to Q7S; see Figure 13 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V STR to Qn; see Figure 14 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum frequency SHCP or STCP; see Figure 9 and 10 © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 9 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter tW pulse width 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max VCC = 3.0 V to 3.6 V 6.0 - - 6.5 - 7.0 - ns VCC = 4.5 V to 5.5 V 5.5 - - 6.0 - 6.5 - ns VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.5 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.2 - 5.7 - ns VCC = 3.0 V to 3.6 V 3.5 - - 3.5 - 4.0 - ns VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.5 - ns VCC = 3.0 V to 3.6 V 8.0 - - 9.0 - 9.5 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.5 - ns VCC = 3.0 V to 3.6 V 8.0 - - 8.5 - 9.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.5 - ns VCC = 3.0 V to 3.6 V 1.5 - - 1.5 - 2.0 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.5 - ns VCC = 3.0 V to 3.6 V 4.2 - - 4.8 - 5.3 - ns VCC = 4.5 V to 5.5 V 2.9 - - 3.3 - 3.8 - ns 4.6 - - 5.3 - 5.8 - ns SHCP and STCP HIGH or LOW; see Figure 9 and 10 SHR and STR HIGH or LOW; see Figure 13 and 14 tsu set-up time DS to SHCP; see Figure 11 SHR to STCP; see Figure 12 SHCP to STCP; see Figure 10 th trec hold time DS to SHCP; see Figure 11 recovery time SHR to SHCP; see Figure 13 STR to STCP; see Figure 14 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance 3.2 - - 3.7 - 4.3 - ns - 55 - - - - - pF - 3.8 6.3 1.7 7.2 1.7 7.8 ns - 4.8 8.0 2.2 9.1 2.2 9.9 ns CL = 15 pF - 3.5 5.7 1.8 6.5 1.8 7.1 ns CL = 50 pF - 4.6 7.7 2.6 8.8 2.6 9.6 ns fi = 1 MHz; VI = GND to VCC [2] 74AHCT594; VCC = 4.5 V to 5.5 V tPLH LOW to HIGH SHCP to Q7S; see Figure 9 propagation CL = 15 pF delay CL = 50 pF STCP to Qn; see Figure 10 © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 10 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 15. Symbol Parameter tPHL 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min - 4.1 6.7 - 5.4 8.8 CL = 15 pF - 3.7 CL = 50 pF - CL = 15 pF CL = 50 pF Max Min 1.8 7.6 1.8 8.3 ns 2.4 10.1 2.4 11.0 ns 6.1 1.9 6.9 1.9 7.2 ns 5.2 8.5 2.6 9.7 2.6 10.5 ns - 4.3 7.0 2.4 8.0 2.4 8.7 ns - 5.4 8.8 2.7 10.1 2.7 11.0 ns CL = 15 pF - 4.5 7.4 2.3 8.4 2.3 9.2 ns CL = 50 pF - 5.7 9.4 3.1 10.7 3.1 11.7 ns HIGH to LOW SHCP to Q7S; see Figure 9 propagation CL = 15 pF delay CL = 50 pF Max STCP to Qn; see Figure 10 SHR to Q7S; see Figure 13 STR to Qn; see Figure 14 fmax maximum frequency SHCP or STCP; see Figure 9 and 10 90 160 - 80 - 70 - MHz tW pulse width SHCP and STCP HIGH or LOW; see Figure 9 and 10 5.5 - - 6.0 - 6.5 - ns SHR and STR HIGH or LOW; see Figure 13 and 14 5.2 - - 5.5 - 6.0 - ns DS to SHCP; see Figure 11 3.0 - - 3.0 - 3.5 - ns SHR to STCP; see Figure 12 5.0 - - 5.0 - 5.5 - ns SHCP to STCP; see Figure 10 5.0 - - 5.0 - 5.5 - ns DS to SHCP; see Figure 11 2.0 - - 2.0 - 2.5 - ns 2.9 - - 3.3 - 3.8 - ns 3.4 - - 3.8 - 4.3 - ns - 55 - - - - - pF tsu set-up time th hold time trec recovery time SHR to SHCP; see Figure 13 STR to STCP; see Figure 14 CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC [2] [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 11 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register 12. Waveforms 1/fmax SHCP input VM tW tPLH Q7S output tPHL VM tTLH tTHL 001aae341 Measurement points are given in Table 8. Fig 9. Shift register clock pulse width, maximum frequency and input to output propagation delays SHCP input VM tsu STCP input 1/fmax VM tW tPHL tPLH Qn outputs VM mla512 Measurement points are given in Table 8. Fig 10. Shift register clock to storage register clock set-up time and storage clock pulse width, maximum frequency and input to output propagation delays © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 12 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register VM SHCP input t su t su th th VM DS input VM Q7 output 001aae342 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 11. Shift register clock to data input set-up and hold times STR input VM tW trec VM STCP input tPHL Qn outputs VM mbc325 Measurement points are given in Table 8. Fig 12. Storage register reset pulse width, input to output propagation delay and recovery time © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 13 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register VM SHR input tW trec VM SHCP input tPHL VM Q7S output mbc324 Measurement points are given in Table 8. Fig 13. Shift register reset pulse width, input to output propagation delay and recovery time VM SHR input tsu VM STCP input VM Qn outputs mbc326 Measurement points are given in Table 8. Fig 14. Shift register reset to storage register clock set-up time Table 8. Measurement points Type Input Output VM VM 74AHC594 0.5 × VCC 0.5 × VCC 74AHCT594 1.5 V 0.5 × VCC © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 14 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register VI negative pulse tW 90 % VM VM 10 % GND tr tf tr VI positive pulse GND tf 90 % VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 For test data see Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 15. Load circuitry for measuring switching times Table 9. Test data Type Input Load Test VI tr, tf CL 74AHC594 VCC ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHCT594 3.0 V ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 15 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT109-1 (SO16) © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 16 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 17. Package outline SOT338-1 (SSOP16) © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 17 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 18. Package outline SOT403-1 (TSSOP16) © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 18 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 19. Package outline SOT763-1 (DHVQFN16) © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 19 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT594_2 20080609 Product data sheet - 74AHC_AHCT594_1 Modifications: 74AHC_AHCT594_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. 20060704 Product data sheet - © 74AHC_AHCT594_2 Product data sheet - Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 20 of 22 74AHC594; 74AHCT594 Nexperia 8-bit shift register with output register 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Nexperia. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com © 74AHC_AHCT594_2 Product data sheet Rev. 02 — 9 June 2008 Nexperia B.V. 2017. All rights reserved 21 of 22 Nexperia 74AHC594; 74AHCT594 8-bit shift register with output register 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 09 June 2008 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74AHC594BQ,115 74AHC594D,112 74AHC594DB,112 74AHC594DB,118 74AHC594D,118 74AHC594PW,112 74AHC594PW,118 74AHCT594BQ,115 74AHCT594D,112 74AHCT594DB,112 74AHCT594DB,118 74AHCT594D,118 74AHCT594PW,112 74AHCT594PW,118