74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 9 — 28 February 2017
1
Product data sheet
General description
The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register and 3-state outputs. Both the shift and storage register have separate
clocks. The device features a serial input (DS) and a serial output (Q7S) to enable
cascading and an asynchronous reset MR input. A LOW on MR will reset the shift
register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a LOW-to-HIGH transition of
the STCP input. If both clocks are connected together, the shift register will always be
one clock pulse ahead of the storage register. Data in the storage register appears at
the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the
outputs to assume a high-impedance OFF-state. Operation of the OE input does not
affect the state of the registers. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2
Features and benefits
•
•
•
•
•
•
•
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
Complies with JEDEC standard no. 7A
Input levels:
– For 74HC595: CMOS level
– For 74HCT595: TTL level
• ESD protection:
– HBM JESD22-A114F exceeds 2000 V
– MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3
Applications
• Serial-to-parallel data conversion
• Remote control holding register
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4
Ordering information
Table 1. Ordering information
Type number Package
74HC595D
Temperature
range
Name
Description
Version
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
-40 °C to +125 °C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
-40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
-40 °C to +125 °C
DHVQFN16
plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
74HCT595D
74HC595DB
74HCT595DB
74HC595PW
74HCT595PW
74HC595BQ
74HCT595BQ
5
Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
12 STCP
13 OE
9
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
15 1
2
3
4
5
6
7
mna554
Figure 1. Functional diagram
74HC_HCT595
Product data sheet
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2 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
13
11
12
15
Q0
1D
2D
3
4
5
5
6
Q6
6
7
Q7
7
OE
10
1
3
4
Q5
15
2
3
Q3
Q4
9
13
mna553
mna552
Figure 2. Logic symbol
Figure 3. IEC logic symbol
STAGE 0
DS
C1/
2
Q2
MR
14
1
Q1
SRG8
R
11
9
Q7S
DS
C2
10
SHCP STCP
14
EN3
12
D
STAGES 1 TO 6
Q
D
STAGE 7
Q
D
FF7
FF0
CP
Q7S
Q
CP
R
R
SHCP
MR
D
Q
D
Q
LATCH
LATCH
CP
CP
STCP
OE
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
mna555
Figure 4. Logic diagram
74HC_HCT595
Product data sheet
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Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
3 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6
Pinning information
6.1 Pinning
1
Q1
terminal 1
index area
2
Q3
3
14 DS
Q4
4
13 OE
Q5
5
12 STCP
Q6
6
11 SHCP
Q7
7
10 MR
GND
8
9
Q7S
001aao242
Figure 5. Pin configuration for SO16, SSOP16 and
TSSOP16
14 DS
Q4
4
13 OE
Q5
5
12 STCP
Q6
6
Q7
7
GND(1)
11 SHCP
10 MR
9
Q2
16 VCC
15 Q0
15 Q0
3
8
1
2
Q3
Q7S
Q1
Q2
GND
74HC595
74HCT595
16 VCC
74HC595
74HCT595
001aao243
Transparent top view
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Figure 6. Pin configuration for DHVQFN16
6.2 Pin description
Table 2. Pin description
Symbol
Pin
Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
GND
8
ground (0 V)
Q7S
9
serial data output
MR
10
master reset (active LOW)
SHCP
11
shift register clock input
STCP
12
storage register clock input
OE
13
output enable input (active LOW)
DS
14
serial data input
Q0
15
parallel data output 0
VCC
16
supply voltage
74HC_HCT595
Product data sheet
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4 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
7
Functional description
Table 3. Function table
[1]
Input Output
Control
Function
SHCP STCP OE
MR
DS
Q7S
Qn
X
X
L
L
X
L
NC
a LOW-level on MR only affects the shift registers
X
↑
L
L
X
L
L
empty shift register loaded into storage register
X
X
H
L
X
L
Z
shift register clear; parallel outputs in high-impedance OFF-state
↑
X
L
H
H
Q6S
NC
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X
↑
L
H
X
NC
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
↑
↑
L
H
X
Q6S
QnS
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1]
H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
SHCP
DS
STCP
MR
OE
Z-state
Q0
Z-state
Q1
Z-state
Q6
Z-state
Q7
Q7S
mna556
Figure 7. Timing diagram
74HC_HCT595
Product data sheet
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5 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
8
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
-0.5
+7
V
VCC
supply voltage
IIK
input clamping current
VI < -0.5 V or VI > VCC + 0.5 V
-
±20
mA
IOK
output clamping current
VO < -0.5 V or VO > VCC + 0.5 V
-
±20
mA
IO
output current
VO = -0.5 V to (VCC + 0.5 V)
pin Q7S
-
±25
mA
pins Qn
-
±35
mA
ICC
supply current
-
70
mA
IGND
ground current
-70
-
mA
Tstg
storage temperature
Ptot
[1]
[2]
[3]
total power dissipation
-65
+150
°C
SO16 package
[1]
-
500
mW
SSOP16 package
[2]
-
500
mW
TSSOP16 package
[2]
-
500
mW
DHVQFN16 package
[3]
-
500
mW
For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 °C.
9
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
74HC595
74HCT595
Unit
Min
Typ
Max
Min
Typ
Max
2.0
5.0
6.0
4.5
5.0
5.5
V
VCC
supply voltage
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Δt/ΔV
input transition rise and
fall rate
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
-40
+25
+125
-40
+25
+125
Tamb
ambient temperature
74HC_HCT595
Product data sheet
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Rev. 9 — 28 February 2017
°C
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6 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
10 Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Typ
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
V
IO = -20 μA; VCC = 2.0 V
1.9
2.0
-
1.9
-
V
IO = -20 μA; VCC = 4.5 V
4.4
4.5
-
4.4
-
V
IO = -20 μA; VCC = 6.0 V
5.9
6.0
-
5.9
-
V
IO = -4 mA; VCC = 4.5 V
3.84
4.32
-
3.7
-
V
IO = -5.2 mA; VCC = 6.0 V
5.34
5.81
-
5.2
-
V
IO = -6 mA; VCC = 4.5 V
3.84
4.32
-
3.7
-
V
IO = -7.8 mA; VCC = 6.0 V
5.34
5.81
-
5.2
-
V
IO = 20 μA; VCC = 2.0 V
-
0
0.1
-
0.1
V
IO = 20 μA; VCC = 4.5 V
-
0
0.1
-
0.1
V
IO = 20 μA; VCC = 6.0 V
-
0
0.1
-
0.1
V
IO = 4 mA; VCC = 4.5 V
-
0.15
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.33
-
0.4
V
IO = 6 mA; VCC = 4.5 V
-
0.15
0.33
-
0.4
V
IO = 7.8 mA; VCC = 6.0 V
-
0.16
0.33
-
0.4
V
74HC595
VIH
VIL
VOH
HIGH-level
input voltage
LOW-level
input voltage
VI = VIH or VIL
HIGH-level
output voltage all outputs
Q7S output
Qn bus driver outputs
VOL
VI = VIH or VIL
LOW-level
output voltage all outputs
Q7S output
Qn bus driver outputs
II
input leakage
current
VI = VCC or GND; VCC = 6.0 V
-
-
±1.0
-
±1.0
μA
IOZ
OFF-state
output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
-
-
±5.0
-
±10
μA
74HC_HCT595
Product data sheet
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Rev. 9 — 28 February 2017
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74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Min
Typ
Max
Min
Max
Unit
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
80
-
160
μA
CI
input
capacitance
-
3.5
-
-
-
pF
74HCT595
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
V
VOH
VI = VIH or VIL; VCC = 4.5 V
HIGH-level
output voltage all outputs
4.4
4.5
-
4.4
-
V
3.84
4.32
-
3.7
-
V
3.7
4.32
-
3.7
-
V
-
0
0.1
-
0.1
V
-
0.15
0.33
-
0.4
V
-
0.16
0.33
-
0.4
V
IO = -20 μA
Q7S output
IO = -4 mA
Qn bus driver outputs
IO = -6 mA
VOL
VI = VIH or VIL; VCC = 4.5 V
LOW-level
output voltage all outputs
IO = 20 μA
Q7S output
IO = 4.0 mA
Qn bus driver outputs
IO = 6.0 mA
II
input leakage
current
VI = VCC or GND; VCC = 5.5 V
-
-
±1.0
-
±1.0
μA
IOZ
OFF-state
output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND
-
-
±5.0
-
±10
μA
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
80
-
160
μA
ΔICC
per input pin;
additional
supply current other inputs at VCC or GND;
IO = 0 A; VI = VCC - 2.1 V;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE
-
150
675
-
735
μA
pin DS
-
25
113
-
123
μA
-
3.5
-
-
-
pF
CI
input
capacitance
74HC_HCT595
Product data sheet
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Rev. 9 — 28 February 2017
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74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
11 Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions
25 °C
Min
Typ
[1]
-40 °C to
+85 °C
-40 °C to
+125 °C
Max
Min
Max
Min
Max
Unit
74HC595
tpd
propagation SHCP to Q7S; see Figure 8
delay
VCC = 2 V
[2]
-
52
160
-
200
-
240
ns
-
19
32
-
40
-
48
ns
-
15
27
-
34
-
41
ns
VCC = 2 V
-
55
175
-
220
-
265
ns
VCC = 4.5 V
-
20
35
-
44
-
53
ns
VCC = 6 V
-
16
30
-
37
-
45
ns
-
47
175
-
220
-
265
ns
-
17
35
-
44
-
53
ns
-
14
30
-
37
-
45
ns
VCC = 2 V
-
47
150
-
190
-
225
ns
VCC = 4.5 V
-
17
30
-
38
-
45
ns
-
14
26
-
33
-
38
ns
VCC = 2 V
-
41
150
-
190
-
225
ns
VCC = 4.5 V
-
15
30
-
38
-
45
ns
VCC = 6 V
-
12
27
-
33
-
38
ns
VCC = 2 V
75
17
-
95
-
110
-
ns
VCC = 4.5 V
15
6
-
19
-
22
-
ns
VCC = 6 V
13
5
-
16
-
19
-
ns
VCC = 2 V
75
11
-
95
-
110
-
ns
VCC = 4.5 V
15
4
-
19
-
22
-
ns
VCC = 6 V
13
3
-
16
-
19
-
ns
VCC = 4.5 V
VCC = 6 V
STCP to Qn; see Figure 9
tPHL
[2]
MR to Q7S; see Figure 11
HIGH
to LOW
VCC = 2 V
propagation
delay
VCC = 4.5 V
VCC = 6 V
ten
enable time OE to Qn; see Figure 12
[3]
VCC = 6 V
tdis
tW
disable time OE to Qn; see Figure 12
pulse width
[4]
SHCP HIGH or LOW;
see Figure 8
STCP HIGH or LOW;
see Figure 9
MR LOW; see Figure 11
74HC_HCT595
Product data sheet
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74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Symbol Parameter Conditions
25 °C
Min
tsu
set-up time
Typ
[1]
-40 °C to
+85 °C
-40 °C to
+125 °C
Max
Min
Max
Min
Max
Unit
VCC = 2 V
75
17
-
95
-
110
-
ns
VCC = 4.5 V
15
6
-
19
-
22
-
ns
VCC = 6 V
13
5
-
16
-
19
-
ns
VCC = 2 V
50
11
-
65
-
75
-
ns
VCC = 4.5 V
10
4
-
13
-
15
-
ns
VCC = 6 V
9
3
-
11
-
13
-
ns
VCC = 2 V
75
22
-
95
-
110
-
ns
VCC = 4.5 V
15
8
-
19
-
22
-
ns
VCC = 6 V
13
7
-
16
-
19
-
ns
VCC = 2 V
3
-6
-
3
-
3
-
ns
VCC = 4.5 V
3
-2
-
3
-
3
-
ns
VCC = 6 V
3
-2
-
3
-
3
-
ns
VCC = 2 V
50
-19
-
65
-
75
-
ns
VCC = 4.5 V
10
-7
-
13
-
15
-
ns
VCC = 6 V
9
-6
-
11
-
13
-
ns
VCC = 2 V
9
30
-
4.8
-
4
-
MHz
VCC = 4.5 V
30
91
-
24
-
20
-
MHz
DS to SHCP; see Figure 10
SHCP to STCP;
see Figure 10
th
trec
fmax
hold time
recovery
time
maximum
frequency
DS to SHCP; see Figure 10
MR to SHCP; see Figure 11
SHCP or STCP; see Figure 8
and Figure 9
VCC = 6 V
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
35
108
-
28
-
24
-
MHz
[5] [6]
-
115
-
-
-
-
-
pF
[2]
-
25
42
-
53
-
63
ns
[2]
-
24
40
-
50
-
60
ns
-
23
40
-
50
-
60
ns
74HCT595; VCC = 4.5 V to 5.5 V
tpd
propagation SHCP to Q7S; see Figure 8
delay
STCP to Qn; see Figure 9
tPHL
HIGH
MR to Q7S; see Figure 11
to LOW
propagation
delay
ten
enable time OE to Qn; see Figure 12
[3]
-
21
35
-
44
-
53
ns
disable time OE to Qn; see Figure 12
[4]
-
18
30
-
38
-
45
ns
tdis
74HC_HCT595
Product data sheet
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© Nexperia B.V. 2017. All rights reserved.
10 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Symbol Parameter Conditions
25 °C
Min
tW
pulse width
tsu
set-up time
Typ
[1]
-40 °C to
+85 °C
-40 °C to
+125 °C
Max
Min
Max
Min
Max
Unit
SHCP HIGH or LOW;
see Figure 8
16
6
-
20
-
24
-
ns
STCP HIGH or LOW;
see Figure 9
16
5
-
20
-
24
-
ns
MR LOW; see Figure 11
20
8
-
25
-
30
-
ns
DS to SHCP; see Figure 9
16
5
-
20
-
24
-
ns
SHCP to STCP;
see Figure 9
16
8
-
20
-
24
-
ns
th
hold time
DS to SHCP; see Figure 10
3
-2
-
3
-
3
-
ns
trec
recovery
time
MR to SHCP; see Figure 11
10
-7
-
13
-
15
-
ns
fmax
maximum
frequency
SHCP and STCP;
see Figure 8 and Figure 9
30
52
-
24
-
20
-
MHz
CPD
power
fi = 1 MHz;
dissipation VI = GND to VCC - 1.5 V
capacitance
-
130
-
-
-
-
-
pF
[1]
[2]
[3]
[4]
[5]
[6]
[5] [6]
Typical values are measured at nominal supply voltage.
tpd is the same as tPHL and tPLH.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
CPD is used to determine the dynamic power dissipation (PD in μW).
2
2
PD = CPD × VCC × fi + Σ(CL × VCC × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
2
Σ(CL × VCC × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
All 9 outputs switching.
11.1 Waveforms and test circuit
1/fmax
VI
SHCP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Q7S output
VOL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 8. Shift clock pulse, maximum frequency and input to output propagation delays
74HC_HCT595
Product data sheet
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© Nexperia B.V. 2017. All rights reserved.
11 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
VI
SHCP input
VM
GND
1/fmax
t su
VI
STCP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Qn output
VOL
mna558
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 9. Storage clock to output propagation delays
VI
VM
SHCP input
GND
t su
t su
th
th
VI
VM
DS input
GND
VOH
VM
Q7S output
VOL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 10. Data set-up and hold times
74HC_HCT595
Product data sheet
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Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
12 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
VI
VM
MR input
GND
tW
t rec
VI
SHCP input
VM
GND
t PHL
VOH
VM
Q7S output
VOL
mna561
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 11. Master reset to output propagation delays
tr
tf
90 %
VM
OE input
10 %
tPLZ
tPZL
Qn output
VM
LOW-to-OFF
OFF-to-LOW
10 %
tPHZ
tPZH
90 %
Qn output
VM
HIGH-to-OFF
OFF-to-HIGH
outputs
enabled
outputs
enabled
outputs
disabled
msa697
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 12. Enable and disable times
Table 8. Measurement points
Input
Output
VM
VM
74HC595
0.5VCC
0.5VCC
74HCT595
1.3 V
1.3 V
Type
74HC_HCT595
Product data sheet
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Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
13 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
VI
negative
pulse
tW
90 %
VM
VM
10 %
0V
tf
tr
VI
positive
pulse
0V
tr
tf
90 %
VM
VM
10 %
tW
VCC
G
VI
VCC
VO
DUT
RT
RL
S1
open
CL
001aad983
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Figure 13. Test circuit for measuring switching times
Table 9. Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC595
VCC
6 ns
50 pF
1 kΩ
open
GND
VCC
74HCT595
3V
6 ns
50 pF
1 kΩ
open
GND
VCC
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
14 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
12 Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
w M
bp
0
2.5
detail X
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.05
0.039
0.016
0.028
0.020
0.01
0.01
0.004
0.028
0.012
0.244
0.041
0.228
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Figure 14. Package outline SOT109-1 (SO16)
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
15 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
D
SOT338-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
8
1
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.00
0.55
8o
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT338-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Figure 15. Package outline SOT338-1 (SSOP16)
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
16 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
D
SOT403-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Figure 16. Package outline SOT403-1 (TSSOP16)
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
17 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
B
D
A
A
E
A1
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
b
2
y
y1 C
v M C A B
w M C
7
L
1
8
Eh
e
16
9
15
10
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Figure 17. Package outline SOT763-1 (DHVQFN16)
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
18 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
13 Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14 Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
74HC_HCT595 v.9
20170228
Product data sheet
-
Modifications:
• The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT595 v.8
20160225
Modifications:
• Type numbers 74HC595N and 74HCT595N (SOT38-4) removed.
74HC_HCT595 v.7
20150126
Modifications:
• Table 7: Power dissipation capacitance condition for 74HCT595 is corrected.
74HC_HCT595 v.6
20111212
Modifications:
• Legal pages updated.
74HC_HCT595 v.5
20110628
74HC_HCT595 v.4
74HC_HCT595_CNV v.3
74HC_HCT595
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
74HC_HCT595 v.8
74HC_HCT595 v.7
74HC_HCT595 v.6
-
74HC_HCT595 v.5
Product data sheet
-
74HC_HCT595 v.4
20030604
Product specification
-
74HC_HCT595_CNV v.3
19980604
Product specification
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
19 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
15 Legal information
15.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Nexperia
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Notwithstanding any damages that
customer might incur for any reason whatsoever, Nexperia's aggregate and
cumulative liability towards customer for the products described herein shall
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
74HC_HCT595
Product data sheet
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification. Customers are responsible for the
design and operation of their applications and products using Nexperia
products, and Nexperia accepts no liability for any assistance with
applications or customer product design. It is customer’s sole responsibility
to determine whether the Nexperia product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
any liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
20 / 22
74HC595; 74HCT595
Nexperia
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
74HC_HCT595
Product data sheet
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
21 / 22
Nexperia
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
11.1
12
13
14
15
General description ............................................ 1
Features and benefits .........................................1
Applications .........................................................1
Ordering information .......................................... 2
Functional diagram ............................................. 2
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 4
Functional description ........................................5
Limiting values .................................................... 6
Recommended operating conditions ................ 6
Static characteristics .......................................... 7
Dynamic characteristics .....................................9
Waveforms and test circuit .............................. 11
Package outline .................................................15
Abbreviations .................................................... 19
Revision history ................................................ 19
Legal information .............................................. 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2017.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 28 February 2017
Document identifier: 74HC_HCT595
Mouser Electronics
Authorized Distributor
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