74LV164D,118

74LV164 8-bit serial-in/parallel-out shift register Rev. 4 — 9 December 2015 Product data sheet 1. General description The 74LV164 is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164. The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB) and either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into Q0, which is the logical AND-function of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge. A LOW on the master reset input (MR) overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. 2. Features and benefits         Wide operating voltage: 1.0 V to 5.5 V Optimized for low-voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce): < 0.8 V at VCC = 3.3 V and Tamb = 25 C Typical VOHV (output VOH undershoot): > 2 V at VCC = 3.3 V and Tamb = 25 C Gated serial data inputs Asynchronous master reset ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +80 C and from 40 C to +125 C. 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV164D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LV164DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LV164PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LV164BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5  3  0.85 mm SOT762-1 4. Functional diagram 65*     & 5 '   '6$ '6%   &3 05     4  4   4   4  4   4   4  4  DDF DDF Fig 1. Logic symbol Fig 2. IEC logic symbol   '6$ '6%  &3 05 %,76(5,$/ ,13$5$//(/ 287 6+,)75(*,67(5          4 4 4 4 4 4 4 4 DDF Fig 3. Functional diagram 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 2 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 5. Pinning information  9&& '6%   4 4  4   4 4   4  4 4    4 4  9&&  4 4  4  4   05   4 *1'   &3 &3   '6% *1'  WHUPLQDO LQGH[DUHD  9&&   '6$ '6$ 5.1 Pinning  4  05 DDF 7UDQVSDUHQWWRSYLHZ DDF (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to VCC. Fig 4. Pin configuration SO14, SSOP14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description DSA 1 data input SA DSB 2 data input SB Q0 3 output 0 Q1 4 output 1 Q2 5 output 2 Q3 6 output 3 GND 7 ground (0 V) CP 8 clock input (edge triggered LOW-to-HIGH) MR 9 master reset input (active LOW) Q4 10 output 4 Q5 11 output 5 Q6 12 output 6 Q7 13 output 7 VCC 14 supply voltage 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 3 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 6. Functional description 6.1 Function table Table 3. Function table[1] Operating mode Input Output MR CP DSA DSB Q0 Q1 to Q7 Reset (clear) L X X X L L to L Shift H  l l L q0 to q6 H  l h L q0 to q6 H  h l L q0 to q6 H  h h H q0 to q6 [1] H = HIGH voltage level; L = LOW voltage level;  = LOW-to-HIGH clock transition; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; q = lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7.0 V - 20 mA - 50 mA - 25 mA input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current VO = 0.5 V to (VCC + 0.5 V) ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation IIK Tamb = 40 C to +125 C SO14 package [2] - 500 mW (T)SSOP14 package [3] - 500 mW DHVQFN14 package [4] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 C. [3] Ptot derates linearly with 5.5 mW/K above 60 C. [4] Ptot derates linearly with 4.5 mW/K above 60 C. 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 4 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions [1] Min Typ Max Unit 1.0 3.3 5.5 V VCC supply voltage VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature 40 +25 +125 C t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V VCC = 3.6 V to 5.5 V - - 50 ns/V [1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 74LV164 Product data sheet Conditions VCC = 1.2 V 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - IO = 100 A; VCC = 1.2 V - 1.2 - - - V IO = 100 A; VCC = 2.0 V 1.8 2.0 - 1.8 - V IO = 100 A; VCC = 2.7 V 2.5 2.7 - 2.5 - V IO = 100 A; VCC = 3.0 V 2.8 3.0 - 2.8 - V IO = 100 A; VCC = 4.5 V 4.3 4.5 - 4.3 - V IO = 6 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V IO = 12 mA; VCC = 4.5 V 3.6 4.2 - 3.5 - V 0.3VCC V VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 5 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL 40 C to +85 C Conditions LOW-level output voltage Min Typ[1] 40 C to +125 C Unit Max Min Max VI = VIH or VIL IO = 100 A; VCC = 1.2 V - 0 - - - V IO = 100 A; VCC = 2.0 V - 0 0.2 - 0.2 V IO = 100 A; VCC = 2.7 V - 0 0.2 - 0.2 V IO = 100 A; VCC = 3.0 V - 0 0.2 - 0.2 V IO = 100 A; VCC = 4.5 V - 0 0.2 - 0.2 V IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V IO = 12 mA; VCC = 4.5 V - 0.35 0.55 - 0.65 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20.0 - 160 A ICC additional supply current per input; VI = VCC  0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 A CI input capacitance - 3.5 - - - pF [1] Typical values are measured at Tamb = 25 C. 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 9. Symbol Parameter tpd tPHL propagation delay HIGH to LOW propagation delay 40 C to +85 C Conditions Product data sheet Unit Min Max Min Max VCC = 1.2 V - 75 - - - ns VCC = 2.0 V - 26 39 - 49 ns CP to Qn; see Figure 6 [2] VCC = 2.7 V - 19 29 - 36 ns VCC = 3.3 V; CL = 15 pF - 12 - - - ns VCC = 3.0 V to 3.6 V [3] - 14 23 - 29 ns VCC = 4.5 V to 5.5 V [3] - 12 19 - 24 ns VCC = 1.2 V - 75 - - - ns VCC = 2.0 V - 26 39 - 49 ns VCC = 2.7 V - 19 29 - 36 ns MR to Qn; see Figure 7 VCC = 3.3 V; CL = 15 pF 74LV164 40 C to +125 C Typ[1] - 12 - - - ns VCC = 3.0 V to 3.6 V [3] - 14 23 - 29 ns VCC = 4.5 V to 5.5 V [3] - 12 19 - 24 ns All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 6 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register Table 7. Dynamic characteristics …continued GND = 0 V; For test circuit see Figure 9. Symbol Parameter tW pulse width 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 2.0 V 34 9 - 41 - ns VCC = 2.7 V 25 6 - 30 - ns VCC = 3.0 V to 3.6 V [3] 20 5 - 24 - ns VCC = 4.5 V to 5.5 V [3] 13 4 - 16 - ns 34 10 - 41 - ns CP; see Figure 6 MR; Figure 7 VCC = 2.0 V VCC = 2.7 V trec recovery time 25 8 - 30 - ns VCC = 3.0 V to 3.6 V [3] 20 6 - 24 - ns VCC = 4.5 V to 5.5 V [3] 13 5 - 16 - ns VCC = 1.2 V - 30 - - - ns VCC = 2.0 V 19 10 - 24 - ns MR to CP; see Figure 7 VCC = 2.7 V tsu set-up time 14 8 - 18 - ns VCC = 3.0 V to 3.6 V [3] 11 6 - 14 - ns VCC = 4.5 V to 5.5 V [3] 8 5 - 10 - ns VCC = 1.2 V - 15 - - - ns VCC = 2.0 V 22 5 - 26 - ns Dn to CP; see Figure 8 VCC = 2.7 V th 16 4 - 19 - ns VCC = 3.0 V to 3.6 V [3] 13 3 - 15 - ns VCC = 4.5 V to 5.5 V [3] 9 2 - 10 - ns VCC = 1.2 V - 10 - - - ns VCC = 2.0 V 5 3 - 5 - ns hold time Dn to CP see Figure 8 5 2 - 5 - ns VCC = 3.0 V to 3.6 V [3] 5 2 - 5 - ns VCC = 4.5 V to 5.5 V [3] 5 1 - 5 - ns VCC = 2.0 V 14 40 - 12 - MHz VCC = 2.7 V 19 58 - 16 - MHz VCC = 2.7 V fmax maximum frequency see Figure 6 VCC = 3.3 V; CL = 15 pF 74LV164 Product data sheet - 78 - - - MHz VCC = 3.0 V to 3.6 V [3] 24 70 - 20 - MHz VCC = 4.5 V to 5.5 V [3] 36 100 - 30 - MHz All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 7 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register Table 7. Dynamic characteristics …continued GND = 0 V; For test circuit see Figure 9. Symbol Parameter CPD [1] power dissipation capacitance 40 C to +85 C Conditions VCC = 3.3 V; CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] Min Max Min Max - 40 - - - Unit pF All typical values are measured at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL. [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [4] 40 C to +125 C Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching (CL  VCC2  fo) = sum of the outputs. 11. Waveforms IPD[ 9, &3LQSXW  90 *1' W: W 3+/ W 3/+ 92+ 90 4QRXWSXW DDF 92/ Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Propagation delay clock (CP) to output (Qn), clock pulse width and maximum clock frequency 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 8 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 9, 90 05LQSXW *1' W: WUHF 9, &3LQSXW 90 *1' W3+/ 92+ 90 4QRXWSXW 92/ DDF Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Pulse width master reset (MR), propagation delay master reset (MR) to output (Qn) and the master reset (MR) to clock (CP) recovery time 9, 90 &3LQSXW *1' W VX W VX WK WK 9, 90 'QLQSXW *1' 92+ 90 4QRXWSXW 92/ DDF Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 8. Data set-up and hold times inputs (Dn) to clock (CP) 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 9 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register Table 8. Measurement points Supply voltage Input Output VCC VM VM 1.2 V 0.5  VCC 0.5  VCC 2.0 V 0.5  VCC 0.5  VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5  VCC 0.5  VCC 9&& 9, 38/6( *(1(5$725 92 '87 &/ S) 57 5/ Nȍ DDD Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Table 9. Test circuit for measuring switching times Test data Supply voltage Input VCC VI tr , tf CL RL 1.2 V VCC  2.5 ns 50 pF 1 k tPHL, tPLH 2.0 V VCC  2.5 ns 50 pF 1 k tPHL, tPLH 2.7 V 2.7 V  2.5 ns 50 pF 1 k tPHL, tPLH 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF, 15 pF 1 k tPHL, tPLH 4.5 V to 5.5 V VCC  2.5 ns 50 pF 1 k tPHL, tPLH 74LV164 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 Test © Nexperia B.V. 2017. All rights reserved 10 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S  /  H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP                                                 LQFKHV        ș R R  1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 10. Package outline SOT108-1 (SO14) 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 11 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   GHWDLO; Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 11. Package outline SOT337-1 (SSOP14) 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 12 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 12. Package outline SOT402-1 (TSSOP14) 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 13 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register '+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP % ' 627 $ $ $ ( F GHWDLO; WHUPLQDO LQGH[DUHD WHUPLQDO LQGH[DUHD & H H Y Z E  & $ % &  \ \ & /   (K H   N   'K ; N   PP VFDOH 'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP PD[ QRP PLQ $  $ E       F ' 'K ( (K H H                N / Y      Z \   \  1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 2XWOLQH YHUVLRQ 627 5HIHUHQFHV ,(& -('(& -(,7$ VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH   02 Fig 13. Package outline SOT762-1 (DHVQFN14) 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 14 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV164 v.4 20151209 Product data sheet - 74LV164 v.3 Modifications: 74LV164 v.3 Modifications: • Type number 74LV164N (SOT27-1) removed. 20050204 Product data sheet The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors • Added: type number 74LV164BQ (DHVQFN14 package). 19980507 Product specification 74LV164 v.1 19970328 Product specification Product data sheet 74LV164 v.2 • 74LV164 v.2 74LV164 - - All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 74LV164 v.1 - © Nexperia B.V. 2017. All rights reserved 15 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LV164 Product data sheet Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 16 of 18 74LV164 Nexperia 8-bit serial-in/parallel-out shift register Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74LV164 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 December 2015 © Nexperia B.V. 2017. All rights reserved 17 of 18 Nexperia 74LV164 8-bit serial-in/parallel-out shift register 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 09 December 2015 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74LV164D 74LV164DB 74LV164N 74LV164PW 74LV164BQ,115 74LV164D,112 74LV164DB,112 74LV164DB,118 74LV164D,118 74LV164N,112 74LV164PW,112 74LV164PW,118