74LV165DB,118

74LV165 8-bit parallel-in/serial-out shift register Rev. 7 — 9 March 2016 Product data sheet 1. General description The 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When input PL is HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. The clock input is a gate-OR structure which allows one input to be used as an active LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated. 2. Features and benefits          Wide supply voltage range from 1.0 V to 5.5 V Synchronous parallel-to-serial applications Optimized for low voltage applications: 1.0 V to 3.6 V Synchronous serial input for easy expansion Latch-up performance exceeds 250 mA 5.5 V tolerant inputs/outputs Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Complies with JEDEC standards:  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V)  JESD8-1A (4.5 V to 5.5 V)  ESD protection:  HBM JESD22-A114-A exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C and from 40 C to +125 C 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV165D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV165DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LV165PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 4. Functional diagram  65* &>/2$'@ *>6+,)7@             •  '  '  '  ' ' ' '  '  ' ' 4 ' 4      3/    &3 &(   PQD Fig 1. & '6 DDD Logic symbol Fig 2.       IEC logic symbol   ' ' ' ' ' ' ' '  3/  '6  &3  &( 4  %,76+,)75(*,67(5 3$5$//(/,16(5,$/287 4  DDD Fig 3. Functional diagram 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 2 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register ' ' ' ' ' ' ' ' '6 &3 ' &( 6' 4 ' 6' 4 ' 6' 4 ' 6' 4 ' 6' 4 ' 6' 4 ' 6' 4 ' 6' &3 )) &3 )) &3 )) &3 )) &3 )) &3 )) &3 )) &3 )) 5' 5' 5' 5' 5' 5' 5' 5' 4 4 4 4 3/ DDD Fig 4. Logic diagram 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 3 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 5. Pinning information 5.1 Pinning /9 3/   9&& &3   &( '   ' '   ' '   ' '   ' 4   '6 *1'   4 DDD Fig 5. Pin configuration SO16 and (T)SSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description PL 1 parallel enable input (active LOW) CP 2 clock input (LOW-to-HIGH edge-triggered) Q7 7 complementary serial output from the last stage GND 8 ground (0 V) Q7 9 serial output from the last stage DS 10 serial data input D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs CE 15 clock enable input (active LOW) VCC 16 positive supply voltage 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 4 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 6. Functional description Function table[1] Table 3. Operating modes parallel load serial shift hold “do nothing” [1] Inputs Qn registers Output PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7 L X X X L L L to L L H L X X X H H H to H H L H L  l X L q0 to q5 q6 q6 H L  h X H q0 to q5 q6 q6 H H X X X q0 q1 to q6 q7 q7 H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care;  = LOW-to-HIGH clock transition. &3 &( '6 3/ ' ' ' ' ' ' ' ' 4 4 LQKLELW VHULDOVKLIW PQD ORDG Fig 6. Timing diagram 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 5 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)[1] Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current IO output current ICC IGND Conditions VI < 0.5 V or VI > VCC + 0.5 V Min Max Unit 0.5 +7 V - 20 mA 0.5 +7 V VO > VCC or VO < 0 - 50 mA 0.5 V < VO < VCC + 0.5 V - 25 mA supply current - +50 mA ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C SO16 package [2] - 500 mW (T)SSOP16 package [3] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 C. [3] Ptot derates linearly with 5.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage Conditions Min Typ Max Unit 1.0 3.3 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature 40 - +85 C t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V 0 - 500 ns/V VCC = 2.0 V to 2.7 V 0 - 200 ns/V VCC = 2.7 V to 3.6 V 0 - 100 ns/V VCC = 3.6 V to 5.5 V 0 - 50 ns/V 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 6 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage 40 C to +85 C Conditions 40 C to +125 C Min Typ[1] Max Min Max Unit VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.3 V to 2.7 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC VCC = 1.2 V - 1.2 VCC = 2.0 V 1.8 2.0 - 1.8 - V VCC = 2.7 V 2.5 2.7 - 2.5 - V VCC = 3.0 V 2.8 3.0 - 2.8 - V VCC = 4.5 V 4.3 4.5 - 4.3 - V VCC = 3.0 V; IO = 6 mA 2.40 2.82 - 2.20 - V VCC = 4.5 V; IO = 12 mA 3.60 4.20 - 3.50 - V VCC = 1.2 V - 0 - - - VCC = 2.0 V - 0 0.2 1.8 0.2 V VCC = 2.7 V - 0 0.2 2.5 0.2 V VCC = 3.0 V - 0 0.2 2.8 0.2 V VCC = 4.5 V - 0 0.2 4.3 0.2 V VI = VIH or VIL; IO = 100 A - standard outputs: VI = VIH or VIL LOW-level output voltage VOL VI = VIH or VIL; IO = 100 A standard outputs: VI = VIH or VIL VCC = 3.0 V; IO = 6 mA - 0.25 0.40 - 0.50 V VCC = 4.5 V; IO = 12 mA - 0.35 0.55 - 0.65 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20 - 160 A ICC additional supply current VI = VCC – 0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 A CI input capacitance - 3.5 - - - pF [1] Typical values are measured at Tamb = 25 C. 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 7 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit, see Figure 12 Symbol Parameter tpd propagation delay 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V - 115 - - - ns VCC = 2.0 V - 38 61 - 76 ns - 27 43 - 54 ns - 22 36 - 45 ns - 18 - - - ns - 15 24 - 30 ns VCC = 1.2 V - 110 - - - ns VCC = 2.0 V - 35 56 - 70 ns - 24 39 - 49 ns - 20 33 - 41 ns - 18 - - - ns - 14 22 - 27 ns VCC = 1.2 V - 90 - - - ns VCC = 2.0 V - 28 45 - 56 ns - 20 32 - 40 ns - 17 27 - 33 ns - 14 - - - ns - 11 18 - 22 ns 34 10 - 41 - ns CE, CP to Q7, Q7; see Figure 7 and Figure 8 [2] VCC = 2.7 V [3] VCC = 3.0 V to 3.6 V VCC = 3.3 V; CL = 15 pF [4] VCC = 4.5 V to 5.5 V PL to Q7, Q7; see Figure 8 VCC = 2.7 V [3] VCC = 3.0 V to 3.6 V VCC = 3.3 V; CL = 15 pF [4] VCC = 4.5 V to 5.5 V D7 to Q7, Q7; CL = 15 pF; see Figure 9 VCC = 2.7 V [3] VCC = 3.0 V to 3.6 V VCC = 3.3 V; CL = 15 pF [4] VCC = 4.5 V to 5.5 V tW pulse width CP input HIGH to LOW; see Figure 7 VCC = 2.0 V VCC = 2.7 V 25 8 - 30 - ns VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns VCC = 4.5 V to 5.5 V [4] 15 5 - 18 - ns 34 10 - 41 - ns PL input LOW; see Figure 8 VCC = 2.0 V VCC = 2.7 V 74LV165 Product data sheet 25 8 - 30 - ns VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns VCC = 4.5 V to 5.5 V [4] 15 5 - 18 - ns All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 8 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit, see Figure 12 Symbol Parameter 40 C to +85 C Conditions Min trec recovery time set-up time 40 C to +125 C Max Min Unit Max PL to CP, CE; see Figure 8 VCC = 1.2 V - 40 - - - ns VCC = 2.0 V 24 15 - 30 - ns VCC = 2.7 V tsu Typ[1] 18 11 - 23 - ns VCC = 3.0 V to 3.6 V [3] 17 10 - 21 - ns VCC = 4.5 V to 5.5 V [4] 12 7 - 15 - ns VCC = 1.2 V - 8 - - - ns VCC = 2.0 V 22 2 - 26 - ns DS to CP, CE; see Figure 10 16 1 - 19 - ns VCC = 3.0 V to 3.6 V [3] 13 1 - 15 - ns VCC = 4.5 V to 5.5 V [4] 9 0 - 10 - ns VCC = 1.2 V - 20 - - - ns VCC = 2.0 V 22 7 - 26 - ns VCC = 2.7 V CE to CP, CP to CE; see Figure 10 VCC = 2.7 V 16 5 - 19 - ns VCC = 3.0 V to 3.6 V [3] 13 4 - 15 - ns VCC = 4.5 V to 5.5 V [4] 9 3 - 10 - ns VCC = 1.2 V - 25 - - - ns VCC = 2.0 V 22 8 - 26 - ns Dn to PL; see Figure 11 VCC = 2.7 V th hold time 16 6 - 19 - ns VCC = 3.0 V to 3.6 V [3] 13 5 - 15 - ns VCC = 4.5 V to 5.5 V [4] 9 4 - 10 - ns VCC = 1.2 V - 20 - - - ns VCC = 2.0 V 22 7 - 26 - ns VCC = 2.7 V 16 5 - 19 - ns VCC = 3.0 V to 3.6 V [3] 13 4 - 15 - ns VCC = 4.5 V to 5.5 V [4] 9 3 - 10 - ns VCC = 1.2 V - 30 - - - ns VCC = 2.0 V 5 8 - 5 - ns DS to CP, CE; Dn to PL; see Figure 10 and Figure 11 CE to CP, CP to CE; see Figure 10 5 6 - 5 - ns VCC = 3.0 V to 3.6 V [3] 5 5 - 5 - ns VCC = 4.5 V to 5.5 V [4] 5 4 - 5 - ns VCC = 2.7 V 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 9 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register Table 7. Dynamic characteristics …continued GND (ground = 0 V); for test circuit, see Figure 12 Symbol Parameter fmax maximum frequency 40 C to +85 C Conditions Max Min Max VCC = 2.0 V 14 40 - 12 - MHz VCC = 2.7 V 19 60 - 16 - MHz 24 65 - 20 - MHz see Figure 7 [3] VCC = 3.3 V; CL = 15 pF VCC = 4.5 V to 5.5 V power dissipation capacitance Unit Min VCC = 3.0 V to 3.6 V CPD 40 C to +125 C Typ[1] VI = GND to VCC; VCC = 3.3 V [1] Typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPHL and tPLH. [3] Typical values are measured at VCC = 3.3 V. - 78 - - - MHz [4] 36 75 - 30 - MHz [5] - 35 - pF [4] Typical values are measured at VCC = 5.0 V. [5] CPD is used to determine the dynamic power dissipation PD = CPD  VCC2  fi + (CL  VCC2  fo) (PD in W), where: fi = input frequency in MHz; fo = output frequency in MHz;  (CL  VCC2  fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 11. Waveforms IPD[ 9, &3&(LQSXW 90 *1' W: W3+/ W3/+ 92+ 90 4RU4RXWSXW 92/ DDD Measurement points are given in Table 8. The changing to output assumes that internal Q6 is opposite state from Q7. Fig 7. Clock pulse (CP) and clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width and maximum clock frequency 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 10 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 9, 90 3/LQSXW *1' W: WUHP 9, &(&3LQSXW 90 *1' W3+/ 92+ 90 4RU4RXWSXW 92/ DDD Measurement points are given in Table 8. The changing to output assumes that internal Q6 is opposite state from Q7. Fig 8. Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock (CP) and clock enable (CE) recovery time 9, 90 'LQSXW *1' W3/+ W3+/ 92+ 90 4RXWSXW 92/ W3/+ W3+/ 92+ 90 4RXWSXW 92/ DDD Measurement points are given in Table 8. The changing to output assumes that internal Q6 is opposite state from Q7. Fig 9. Data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 11 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register  9, 90 &3&(LQSXW *1' WK WK WVX/ 9, WVX VWDEOH 90 '6LQSXW *1' WVX WK W: 9, 90 &3&(LQSXW *1' DDD Measurement points are given in Table 8. (1) CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. Set-up and hold times 9, 'QLQSXW 90 90 *1' WVX WK WVX WK 9, 3/LQSXW 90 90 *1' DDD Measurement points are given in Table 8. Fig 11. Set-up and hold times from the data inputs (Dn) to the parallel load input (PL) Table 8. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V  4.5 V 0.5VCC 0.5VCC 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 12 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register W: 9,  QHJDWLYH SXOVH 90 90  9 WI WU WU WI 9,  SRVLWLYH SXOVH 90 90  9 W: 9(;7 9&& * 9, 5/ 92 '87 57 5/ &/ DDH Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 12. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPHL, tPLH < 2.7 V VCC 2.5 ns 50 pF 1 k open 2.7 V to 3.6 V 2.7 V 2.5 ns 50 pF, 15 pF 1 k open  4.5 V VCC 2.5 ns 50 pF 1 k open 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 13 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S  /  H Z 0 ES   GHWDLO; PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP                                                 LQFKHV         ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 13. Package outline SOT109-1 (SO16) 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 14 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   GHWDLO; Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 14. Package outline SOT338-1 (SSOP16) 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 15 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 15. Package outline SOT403-1 (TSSOP16) 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 16 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV165 v.7 20160309 Product data sheet - 74LV165 v.6 Modifications: 74LV165 v.6 Modifications: 74LV165 v.5 Modifications: 74LV165 v.4 Modifications: 74LV165_CNV_3 74LV165 Product data sheet • Type number 74HC165N (SOT38-4) removed. 20140219 • Product data sheet 74LV165 v.5 - 74LV165 v.4 Typo corrected in Table 2 “Pin description” 20130909 • - Product data sheet Typo corrected in the header of Table 6 “Static characteristics” 20130830 Product data sheet - 74LV165_CNV_3 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Family data added, see Section 9 “Static characteristics” December 1998 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 - © Nexperia B.V. 2017. All rights reserved 17 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. 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Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LV165 Product data sheet Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 18 of 20 74LV165 Nexperia 8-bit parallel-in/serial-out shift register Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74LV165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 March 2016 © Nexperia B.V. 2017. All rights reserved 19 of 20 Nexperia 74LV165 8-bit parallel-in/serial-out shift register 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 09 March 2016 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74LV165D,112 74LV165DB,112 74LV165DB,118 74LV165D,118 74LV165PW,112 74LV165PW,118 74LV165D/AUJ