74LV4094PW,118

74LV4094 8-stage shift-and-store bus register Rev. 6 — 14 November 2018 Product data sheet 1. General description The 74LV4094 is a low voltage Si-gate CMOS device and is pin and functional compatible with 74HC4094; 74HCT4094. The 74LV4094 is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of 74LV4094 devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading 74LV4094 devices when the clock has a slow rise time. 2. Features and benefits • • • • • • • Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Applications • • Serial-to-parallel data conversion Remote control holding register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4094D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV4094DB -40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LV4094PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74LV4094 Nexperia 8-stage shift-and-store bus register 5. Functional diagram 3 1 CP 2 1 STR D OE QS1 9 QS2 10 QP0 4 QP1 5 QP2 6 QP3 7 QP4 14 QP5 13 QP6 12 QP7 11 EN3 SRG8 3 C1/ 2 1D 2D 4 3 5 6 7 14 13 12 11 9 10 15 Fig. 1. C2 15 001aaf112 001aaf111 Functional diagram Fig. 2. 2 3 1 15 D Logic symbol 8-STAGE SHIFT REGISTER CP QS2 QS1 STR 10 9 8-BIT STORAGE REGISTER OE 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 4 Fig. 3. 5 6 7 14 13 12 11 001aaf119 Logic diagram 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 2 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register STAGE 0 D D STAGES 1 TO 6 Q STAGE 7 D Q D CP Q QS1 CP FF 0 CP D FF 7 CP Q QS2 LE LATCH D Q D Q LE LE LATCH 0 LATCH 7 STR OE QP0 Fig. 4. QP1 QP2 QP3 QP4 QP6 QP5 QP7 001aag799 Logic diagram 6. Pinning information 6.1. Pinning 74LV4094 STR 1 16 VCC D 2 15 OE CP 3 14 QP4 QP0 4 13 QP5 QP1 5 12 QP6 QP2 6 11 QP7 QP3 7 10 QS2 GND 8 9 QS1 001aan680 Fig. 5. Pin configuration SOT109-1 (SO16), SOT338-1 (SSOP16) and SOT403-1 (TSSOP16) 6.2. Pin description Table 2. Pin description Symbol Pin Description STR 1 strobe input D 2 data input CP 3 clock input QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output GND 8 ground supply voltage QS1, QS2 9,10 serial output OE 15 output enable input VCC 16 supply voltage 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 3 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = HIGH-impedance OFF-state; NC = no change; ↑ = positive-going transition; ↓ = negative-going transition; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition. Inputs Parallel outputs Serial outputs CP OE STR D QP0 QPn QS1 QS2 ↑ L X X Z Z Q6S NC ↓ L X X Z Z NC Q7S ↑ H L X NC NC Q6S NC ↑ H H L L QPn -1 Q6S NC ↑ H H H H QPn -1 Q6S NC ↓ H H H NC NC NC Q7S CLOCK INPUT DATA INPUT STROBE INPUT OUTPUT ENABLE INPUT INTERNAL Q0S (FF 0) OUTPUT QP0 Z-state INTERNAL Q6S (FF 6) OUTPUT QP6 Z-state SERIAL OUTPUT QS1 SERIAL OUTPUT QS2 001aaf117 At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs. Fig. 6. Timing diagram 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 4 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK IO ICC Min Max -0.5 +7 V VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±50 mA output current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation [1] [2] Conditions Unit Tamb = -40 °C to +125 °C SO16 package [1] - 500 mW (T)SSOP16 package [2] - 500 mW For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI Min Typ Max Unit 1.0 3.3 3.6 V input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V [1] Conditions [1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 5 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage VIL LOW-level input voltage VOH Conditions -40 °C to 85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.2 V VCC 0.6 - VCC - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - 0.4 GND - GND V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V - 1.2 - - - V IO = -100 μA; VCC = 2.0 V 1.8 2.0 - 1.8 - V IO = -100 μA; VCC = 2.7 V 2.5 2.7 - 2.5 - V IO = -100 μA; VCC = 3.0 V 2.8 3.0 - 2.8 - V 2.40 2.82 - 2.20 - V IO = 100 μA; VCC = 1.2 V - 0 - - - V IO = 100 μA; VCC = 2.0 V - 0 0.2 - 0.2 V IO = 100 μA; VCC = 2.7 V - 0 0.2 - 0.2 V IO = 100 μA; VCC = 3.0 V - 0 0.2 - 0.2 V IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V HIGH-level output VI = VIH or VIL; all pins voltage IO = -100 μA; VCC = 1.2 V VI = VIH or VIL; pins QPn IO = -6 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL; all pins VI = VIH or VIL; pins QPn II input leakage current VI = VCC or GND; VCC = 3.6 V - - ±1.0 - ±1.0 μA IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 3.6 V - - ±5.0 - ±10.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - - 20.0 - 160 μA ΔICC additional supply current per input; VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V - - 500.0 - 850 μA CI input capacitance - 3.5 - - - pF [1] All typical values are measured at Tamb = 25 °C. 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 6 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 11. Symbol tpd Parameter propagation delay Conditions -40 °C to 85 °C Min Typ[1] VCC = 1.2 V - VCC = 2.0 V - VCC = 2.7 V Min 90 - - - ns 31 58 - 70 ns - 23 43 - 51 ns - 17 34 - 41 ns - 14 - - - ns VCC = 1.2 V - 80 - - - ns VCC = 2.0 V - 27 51 - 61 ns VCC = 2.7 V - 20 38 - 45 ns VCC = 3.0 V to 3.6 V - 14 30 - 36 ns - 13 - - - ns VCC = 1.2 V - 115 - - - ns VCC = 2.0 V - 39 75 - 90 ns VCC = 2.7 V - 29 55 - 66 ns - 22 44 - 53 ns - 18 - - - ns VCC = 1.2 V - 105 - - - ns VCC = 2.0 V - 36 68 - 82 ns - 26 50 - 60 ns - 20 40 - 48 ns - 17 - - - ns VCC = 1.2 V - 100 - - - ns VCC = 2.0 V - 34 65 - 77 ns VCC = 2.7 V - 25 48 - 56 ns - 19 38 - 45 ns VCC = 1.2 V - 65 - - - ns VCC = 2.0 V - 24 40 - 49 ns VCC = 2.7 V - 18 32 - 37 ns - 14 26 - 30 ns CP to QS1; see Fig. 7 CP to QS2; see Fig. 7 VCC = 3.3 V; CL = 15 pF CP to QPn; see Fig. 7 VCC = 3.0 V to 3.6 V [3] [2] [3] [2] [3] VCC = 3.3 V; CL = 15 pF STR to QPn; see Fig. 8 [2] VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] VCC = 3.3 V; CL = 15 pF OE to QPn; see Fig. 9 VCC = 3.0 V to 3.6 V tdis disable time OE to QPn; see Fig. 9 VCC = 3.0 V to 3.6 V 74LV4094 Product data sheet Max [2] VCC = 3.3 V; CL = 15 pF enable time Unit Max VCC = 3.0 V to 3.6 V ten -40 °C to +125 °C [2] [3] [2] [3] All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 7 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register Symbol tW Parameter pulse width Conditions -40 °C to 85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 2.0 V 34 9 - 41 - ns VCC = 2.7 V 25 6 - 30 - ns 20 5 - 24 - ns 34 9 - 41 - ns 25 6 - 30 - ns 20 5 - 24 - ns VCC = 1.2 V - 25 - - - ns VCC = 2.0 V 22 9 - 26 - ns 16 6 - 19 - ns 13 5 - 15 - ns VCC = 1.2 V - 50 - - - ns VCC = 2.0 V 43 17 - 51 - ns 31 13 - 38 - ns 25 10 - 30 - ns VCC = 1.2 V - -10 - - - ns VCC = 2.0 V 5 -4 - +5 - ns 5 -3 - +5 - ns 5 -2 - +5 - ns VCC = 1.2 V - -25 - - - ns VCC = 2.0 V 5 -9 - +5 - ns 5 -6 - +5 - ns 5 -5 - +5 - ns VCC = 2.0 V 14 52 - 12 - MHz VCC = 2.7 V 19 70 - 16 - MHz 24 87 - 20 - MHz - 95 - - - MHz - 83 - - - pF CP HIGH or LOW; see Fig. 7 VCC = 3.0 V to 3.6 V [3] STR HIGH; see Fig. 8 VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsu set-up time [3] D to CP; see Fig. 10 VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] CP to STR; see Fig. 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V th hold time [3] D to CP; see Fig. 10 VCC = 2.7 V VCC = 3.0 V to 3.6 V [3] CP to STR; see Fig. 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency [3] CP; see Fig. 7 VCC = 3.0 V to 3.6 V [3] VCC = 3.3 V; CL = 15 pF CPD [1] [2] [3] [4] power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC [4] All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL; ten is the same as tPZH and tPZL; tdis is the same as tPLZ and tPHZ. All typical values are measured at VCC = 3.3 V. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + ∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; 2 VCC = supply voltage in V; N = number of inputs switching; ∑(CL x VCC x fo) = sum of outputs. 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 8 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register 11.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW tPHL tPLH VOH QPn, QS1 output VM VOL tPHL tPLH VOH QS2 output VM VOL 001aaf113 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse width and the maximum frequency (CP) VI CP input VM GND tsu th VI STR input VM GND tW VOH QPn output tPHL tPLH VM VOL 001aaf114 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock set-up and hold times for strobe input 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 9 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register VI VM OE input GND tPZL tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL VM VX tPHZ tPZH VOH output HIGH-to-OFF OFF-to-HIGH GND VY VM outputs enabled outputs enabled outputs disabled 001aaf116 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Enable and disable times VI VM CP input GND t su t su th th VI VM D input GND VOH VM QPn, QS1, QS2 output VOL 001aaf115 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 10. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY < 2.7 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH - 0.1VCC 2.7 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 10 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 11. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ < 2.7 V VCC ≤ 2.5 ns 50 pF 1 kΩ open GND 2VCC 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 15 pF, 50 pF 1 kΩ open GND 2VCC 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 11 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 12. Package outline SOT109-1 (SO16) 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 12 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig. 13. Package outline SOT338-1 (SSOP16) 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 13 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 14. Package outline SOT403-1 (TSSOP16) 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 14 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV4094 v.6 20181114 Product data sheet - 74LV4094 v.5 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Fig. 6 corrected. 74LV4094 v.5 20160318 Modifications: • 74LV4094 v.4 20111219 Modifications: • 74LV4094 v.3 20110307 74LV4094 v.2 74LV4094 v.1 74LV4094 Product data sheet Product data sheet - 74LV4094 v.4 Type number 74LV4094N (SOT38-4) removed. Product data sheet - 74LV4094 v.3 Product data sheet - 74LV4094 v.2 20060629 Product data sheet - 74LV4094 v.1 19980623 Product specification - - Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 15 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 16 / 17 74LV4094 Nexperia 8-stage shift-and-store bus register Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 4 8. Limiting values............................................................. 5 9. Recommended operating conditions..........................5 10. Static characteristics..................................................6 11. Dynamic characteristics.............................................7 11.1. Waveforms and test circuit........................................ 9 12. Package outline........................................................ 12 13. Abbreviations............................................................ 15 14. Revision history........................................................15 15. Legal information......................................................16 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 14 November 2018 74LV4094 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 14 November 2018 © Nexperia B.V. 2018. All rights reserved 17 / 17 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74LV4094D,112 74LV4094DB,112 74LV4094DB,118 74LV4094D,118 74LV4094N,112 74LV4094PW,112 74LV4094PW,118