TP09-SR

TP09 Stable  6MHz, Low  Cost  Dual  Op  Amp     Description Features  Stable 6 MHz GBWP in VCM from 0-V to VDD  Excellent EMI Suppress Performance  Offset Voltage: ±400 μV Maximum  Offset Voltage Temperature Drift: 1 μV/°C  Input Bias Current: 1 pA Typical  THD+Noise: -115 dB at 1kHz, -99 dB at 10kHz  High CMRR/PSRR: 110/95 dB  Beyond the Rails Input Common-Mode Range  Outputs Swing to within 3 mV of Each Rail  No Phase Reversal for Overdriven Inputs  High Output Capability: 100mA  Supply Voltage Range: - Single +2.1 V to +6.0 V Supply - Or Dual ±1.05 V to ±3.0 V Supplies  –40°C to 125°C Operation Temperature Range  ESD Rating: 8KV – HBM, 2KV–CDM and 500V–MM  Green, Popular Type Package Applications  Multimedia Audio  Headphone Drivers  LCD Drivers  Photo Diode Pre-amp  Medical Equipments  Portable Devices  ASIC Input or Output  Sensor Interfaces The TP09 is CMOS dual RRIO op-amp with low offset, low power and stable high frequency response. They incorporate 3PEAK’s proprietary and patented design techniques to achieve very good AC performance with 6MHz bandwidth, 4.5V/μs slew rate and low distortion while drawing only 500μA of quiescent current per amplifier. The input common-mode voltage range extends 300mV beyond V– and V+, and the outputs swing rail-to-rail. The TP09 can be used as plug-in replacements for many commercially available op-amps to reduce power and improve input/output range and performance. The TP09 Op-amp is unity gain stable with any capacitive load. They operate from either single +2.1V to +6.0V supply or dual ±1.05V to ±3.0V supplies. Analog trim and calibration routine reduce input offset voltage to below 400μV, and proprietary precision temperature compensation technique makes offset voltage temperature drift at 1μV/°C. Adaptive biasing and dynamic compensation enables the TP09 to achieve ‘THD +Noise’ for 1kHz/10kHz 2VPP signal at -115dB/ -99dB. Beyond the rails input and rail-to-rail output characteristics allow the full power-supply voltage to be used for signal range. The combination of features makes the TP09 ideal choices for audio amplification of computers, sound ports, and other consumer Audio. The TP09 Op-amp is very stable, and it is capable of driving heavy capacitive loads such as those found in LCDs. The ability to swing rail-to-rail at the inputs and outputs enables designers to buffer CMOS DACs, ASICs, or other wide output swing devices in single-supply systems. 3PEAK and the 3PEAK logo are registered trademarks of 3PEAK INCORPORATED. All other trademarks are the property of their respective owners. Pin Configuration (Top View) Unity Gain Bandwidth vs. Temperature  10 GBW(MHz) 8 6 4                                           2        0 ‐50 ‐25 0 25 50 75 100 125 150 Temperature(℃)   www.3peakic.com Rev. A 1  TP09      Stable 6MHz, Low Cost Dual Op Amp Absolute Maximum Ratings Note 1 Supply Voltage: V+ – V–....................................7.0V – + Input Voltage............................. V – 0.3 to V + 0.3 Operating Temperature Range.......–40°C to 125°C ±20mA Maximum Junction Temperature................... 150°C SHDN Pin Voltage……………………………V– to V+ Storage Temperature Range.......... –65°C to 150°C Output Current: OUT...................................±100mA Lead Temperature (Soldering, 10 sec) ......... 260°C Input Current: +IN, –IN, SHDN Note 2.............. Output Short-Circuit Duration Note 3…............ Infinite Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input current should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads. ESD, Electrostatic Discharge Protection Symbol Parameter Condition Minimum Level Unit HBM Human Body Model ESD MIL-STD-883H Method 3015.8 8 kV MM Machine Model ESD JEDEC-EIA/JESD22-A115 500 V CDM Charged Device Model ESD JEDEC-EIA/JESD22-C101E 2 kV Order Information Model Name TP09 2  Order Number TP09-SR Rev. A Package 8-Pin SOIC Transport Media, Quantity Tape and Reel, 4000 Marking Information TP09 www.3peakic.com TP09          Stable  6MHz,  Dual  Low  Cost  Op  Amps Electrical Characteristics The specifications are at TA = 27°C. VS = +2.1 V to +6.0 V, or ±1.05 V to ±3.0 V, RL = 2kΩ, CL =100pF.Unless otherwise noted. SYMBOL VOS VOS TC PARAMETER CONDITIONS MIN TYP MAX UNITS -400 ±50 1 +400 2 μV μV/°C TA = 27 °C 1 10 pA TA = 85 °C 25 pA Input Offset Voltage VCM = Vss+0.1V Input Offset Voltage Drift -40°C to 125°C IB Input Bias Current IOS Input Offset Current 0.001 pA Input Voltage Noise f = 0.1Hz to 10Hz 8 μVPP f = 1kHz f = 1kHz Differential Common Mode VCM = 0V to 2.5V 19 nV/√Hz fA/√Hz Vn en in Input Voltage Noise Density Input Current Noise CIN Input Capacitance CMRR PSRR Common Mode Rejection Ratio Common-mode Input Voltage Range Power Supply Rejection Ratio AVOL VCM 90 2 7.76 6.87 110 V– -0.1 pF dB V+-0.1 V VCM = 0V, VS = 3V to 5V 80 95 dB Open-Loop Large Signal Gain RLOAD = 10kΩ 95 105 dB VOL, VOH Output Swing from Supply Rail RLOAD = 10kΩ ROUT Closed-Loop Output Impedance G = 1, f =1kHz, IOUT = 0 ISC Output Short-Circuit Current Sink or source current IO Output Current Sink or source current, Output 1V Drop VDD Supply Voltage 3 90 6 mV 0.024 Ω 100 mA 50 mA 2.1 6.0 V 800 μA IQ Quiescent Current per Amplifier VS = 5V 500 PM Phase Margin RLOAD = 1kΩ, CLOAD = 60pF 60 ° GM Gain Margin RLOAD = 1kΩ, CLOAD = 60pF 15 dB Gain-Bandwidth Product f = 1kHz AV = 1, VOUT = 1.5V to 3.5V, CLOAD = 60pF, RLOAD = 1kΩ 6 MHz 4.5 V/μs 280 8.5 9.5 kHz 0.0003 % 110 dB GBWP SR FPBW tS THD+N Xtalk Slew Rate Full Power Bandwidth Note 1 Settling Time, 0.1% Settling Time, 0.01% Total Harmonic Distortion and Noise Channel Separation AV = –1, 1V Step f = 1kHz, AV =1, RL = 2kΩ, VOUT = 1Vp-p f = 1kHz, RL = 2kΩ 3.6 μs Note 1: Full power bandwidth is calculated from the slew rate FPBW = SR/π • VP-P www.3peakic.com Rev. A 3  TP09           Stable 6MHz, Dual, Low Cost Op Amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. Offset Voltage Production Distribution Unity Gain Bandwidth vs. Temperature 450 Number = 9162 pcs 400 300 GBW(MHz) Population 350 250 200 150 100 50 0 ‐500 ‐400 ‐300 ‐200 ‐100 0 10 9 8 7 6 5 4 3 2 1 0 ‐50 100 200 300 400 0 50 100 150 Temperature(℃) Offset Voltage(μV)                         Open-Loop Gain and Phase Input Voltage Noise Spectral Density 200 120 100 1000 150 80 Gain(dB) 40 50 20 0 0 Noise(nV/√Hz) 100 60 100 10 ‐50 ‐20 ‐100 ‐40 ‐60 1 ‐150 0.1 10 1k 100k 1 10M 10 100 1k 10k 100k 1M 10M Frequency(Hz) Frequency (Hz)                Input Bias Current vs. Input Common Mode Voltage  Input Bias Current vs. Temperature 250 0 Input Bias Current(pA) Input Bias Current(pA) 200 150 100 50 0 ‐50 ‐5 ‐10 ‐15 ‐20 ‐25 ‐40 ‐20 0 20 40 60 80 100 120 140 0 Temperature(℃) 1 2 3 4 5 Common Mode Voltage(V)             4  Rev. A   www.3peakic.com TP09          Stable  6MHz,  Dual  Low  Cost  Op  Amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) Common Mode Rejection Ratio CMRR vs. Frequency 140 160 120 140 120 CMRR(dB) CMRR(dB) 100 80 60 100 80 60 40 40 20 20 0 0 0 1 2 3 4 Common-mode voltage(V)   0.1 5 10 1k 100k                     Short Circuit Current vs. Temperature  Quiescent Current vs. Temperature 140 1 0.9 120 ISOURCE 0.8 100 0.7 Current(mA) Supply Current(mA) 10M Frequency(Hz) 0.6 0.5 0.4 80 ISINK 60 40 0.3 0.2 20 0.1 0 0 ‐50 0 50 100 ‐50 150 Temperature(℃) 0 50 100 150 Temperature(℃)              Power-Supply Rejection Ratio Quiescent Current vs. Supply Voltage 1 120 0.9 100 Supply Current(mA) 0.8 PSRR(dB) 80 60 40 0.7 0.6 0.5 0.4 0.3 0.2 20 0.1 0 0 0.1 10 1k Frequency(Hz) www.3peakic.com 100k 10M 1.5              2 2.5 3 3.5 4 Supply Voltage(V) Rev. A 4.5 5   5  TP09           Stable 6MHz, Dual, Low Cost Op Amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) CMRR vs. Temperature  PSRR vs. Temperature 140 120 120 CMRR(-dB) PSRR(-dB) 100 80 60 100 80 60 40 40 20 20 0 0 ‐50 0 50 100 ‐50 150 0 50 100 150 Temperature(℃) Temperature(℃)               Large-Scale Step Response  EMIRR IN+ vs. Frequency 140              Gain= +1 RL= 10kΩ 2V/div 120 80 60 2V/div EMIRR IN+(dB) 100 40 20 0 1 10 100 1000 Frequency(MHz) Time (500μs/div)             2V/div Gain = + 10 ±V = ±2.5V Positive Over-Voltage Recovery 2V/div Negative Over-Voltage Recovery 2V/div 2V/div Gain = + 10 ±V = ±2.5V Time (2μs/div) 6  Rev. A Time (1μs/div) www.3peakic.com   TP09          Stable  6MHz,  Dual  Low  Cost  Op  Amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 0.1 Hz TO 10 Hz Input Voltage Noise Offset Voltage vs Common-Mode Voltage            20 5μS/div Offset voltage(μV) 0 ‐20 ‐40 ‐60 ‐80 ‐100 ‐120 0 Time (1s/div) 1 2 3 4 5 Common-mode voltage(V)             Positive Output Swing vs. Load Current Negative Output Swing vs. Load Current 140 0 120 ‐20 100 ‐40           Iout(mA) Iout(mA) -40℃ 80 60 25℃ 125℃ ‐60 ‐80 ‐100 40 -40℃ 25℃ 125℃ 20 0 0 1 2 3 Vout Dropout(V) www.3peakic.com 4 ‐120 ‐140 0 5              1 2 3 4 5 Vout Dropout(V) Rev. A 7  TP09           Stable 6MHz, Dual, Low Cost Op Amps Pin Functions –IN: Inverting Input of the Amplifier. Voltage range of this pin can go from V– – 0.3V to V+ + 0.3V. +IN: Non-Inverting Input of Amplifier. This pin has the same voltage range as –IN. +VS: Positive Power Supply. Typically the voltage is from 2.1V to 6V. Split supplies are possible as long as the voltage between V+ and V– is between 2.1V and 6V. A bypass capacitor of 0.1μF as close to the part as possible should be used between power supply pins or between supply pins and ground. N/C: No Connection. -VS: Negative Power Supply. It is normally tied to ground. It can also be tied to a voltage other than ground as long as the voltage between V+ and V– is from 2.1V to 6V. If it is not connected to ground, bypass it with a capacitor of 0.1μF as close to the part as possible. OUT: Amplifier Output. The voltage range extends to within millivolts of each supply rail. Operation The TP09 input signal range extends beyond the negative and positive power supplies. The output can even extend all the way to the negative supply. The input stage is comprised of two CMOS differential amplifiers, a PMOS stage and NMOS stage that are active over different ranges of common mode input voltage. The Class-AB control buffer and output bias stage uses a proprietary compensation technique to take full advantage of the process technology to drive very high capacitive loads. This is evident from the transient over shoot measurement plots in the Typical Performance Characteristics. Applications Information Low Supply Voltage and Low Power Consumption The TP09 of operational amplifier can operate with power supply voltages from 2.1 V to 6.0 V. Each amplifier draws only 500 μA quiescent current. The low supply voltage capability and low supply current are ideal for portable applications demanding high capacitive load driving capability and stable wide bandwidth. The TP09 is optimized for wide bandwidth low power applications. They have an industry leading high GBWP to power ratio and are unity gain stable for any capacitive load. When the load capacitance increases, the increased capacitance at the output pushed the non-dominant pole to lower frequency in the open loop frequency response, lowering the phase and gain margin. Higher gain configurations tend to have better capacitive drive capability than lower gain configurations due to lower closed loop bandwidth and hence higher phase margin. Low Input Referred Noise The TP09 provides a low input referred noise density of 19 nV/√Hz at 1 kHz. The voltage noise will grow slowly with the frequency in wideband range, and the input voltage noise is typically 8 μVP-P at the frequency of 0.1 Hz to 10 Hz. Low Input Offset Voltage The TP09 has a low offset voltage of 400 μV maximum which is essential for precision applications. The offset voltage is trimmed with a proprietary trim algorithm to ensure low offset voltage for precision signal processing requirement. Low Input Bias Current The TP09 is a CMOS OPA family and features very low input bias current in pA range. The low input bias current allows the amplifiers to be used in applications with high resistance sources. Care must be taken to minimize PCB Surface Leakage. See below section on “PCB Surface Leakage” for more details. PCB Surface Leakage 8  Rev. A www.3peakic.com TP09          Stable  6MHz,  Dual  Low  Cost  Op  Amps In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012 Ω. A 5 V difference would cause 5 pA of current to flow, which is greater than the TP09 OPA’s input bias current at +27°C (±1pA, typical). It is recommended to use multi-layer PCB layout and route the OPA’s -IN and +IN signal under the PCB surface. The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 1 for Inverting Gain application. 1. For Non-Inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common Mode input voltage. 2. For Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op-amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. Figure 1 Ground Sensing and Rail to Rail Output The TP09 has excellent output drive capability, delivering over 100 mA of output drive current. The output stage is a rail-to-rail topology that is capable of swinging to within 10mV of either rail. Since the inputs can go 300 mV beyond either rail, the op-amp can easily perform ‘true ground’ sensing. The maximum output current is a function of total supply voltage. As the supply voltage to the amplifier increases, the output current capability also increases. Attention must be paid to keep the junction temperature of the IC below 150°C when the output is in continuous short-circuit. The output of the amplifier has reverse-biased ESD diodes connected to each supply. The output should not be forced more than 0.5V beyond either supply, otherwise current will flow through these diodes. ESD The TP09 has reverse-biased ESD protection diodes on all inputs and output. Input and out pins can not be biased more than 300 mV beyond either supply rail. Feedback Components and Suppression of Ringing Care should be taken to ensure that the pole formed by the feedback resistors and the parasitic capacitance at the inverting input does not degrade stability. For example, in a gain of +2 configuration with gain and feedback resistors of 10k, a poorly designed circuit board layout with parasitic capacitance of 5 pF (part +PC board) at the amplifier’s inverting input will cause the amplifier to ring due to a pole formed at 8.1 MHz. An additional capacitor of 5 pF across the feedback resistor as shown in Figure 2 will eliminate any ringing. Careful layout is extremely important because low power signal conditioning applications demand high-impedance circuits. The layout should also minimize stray capacitance at the OPA’s inputs. However some stray capacitance may be unavoidable and it may be necessary to add a 2 pF to 10 pF capacitor across the feedback resistor. Select the smallest capacitor value that ensures stability. www.3peakic.com Rev. A 9  TP09           Stable 6MHz, Dual, Low Cost Op Amps Figure 2 Shut-down The single channel OPA versions have SHDN pins that can shut down the amplifier to less than 0.2 μA supply current. The SHDN pin voltage needs to be within 0.5 V of V– for the amplifier to shut down. During shutdown, the output will be in high output resistance state, which is suitable for multiplexer applications. When left floating, the SHDN pin is internally pulled up to the positive supply and the amplifier remains enabled. Driving Large Capacitive Load The TP09 of OPA is designed to drive large capacitive loads. Refer to Typical Performance Characteristics for “Phase Margin vs. Load Capacitance”. As always, larger load capacitance decreases overall phase margin in a feedback system where internal frequency compensation is utilized. As the load capacitance increases, the feedback loop’s phase margin decreases, and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in output step response. The unity-gain buffer (G = +1V/V) is the most sensitive to large capacitive loads. When driving large capacitive loads with the TP09 OPA family (e.g., > 200 pF when G = +1V/V), a small series resistor at the output (RISO in Figure 3) improves the feedback loop’s phase margin and stability by making the output load resistive at higher frequencies. Figure 3 Power Supply Layout and Bypass The TP09 OPA’s power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 μF to 0.1 μF) within 2 mm for good high frequency performance. It can also use a bulk capacitor (i.e., 1μF or larger) within 100mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. Ground layout improves performance by decreasing the amount of stray capacitance and noise at the OPA’s inputs and outputs. To decrease stray capacitance, minimize PC board lengths and resistor leads, and place external components as close to the op amps’ pins as possible. Proper Board Layout To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates a barrier to moisture accumulation and helps reduce parasitic resistance on the board. Keeping supply traces short and properly bypassing the power supplies minimizes power supply disturbances due to output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be 10  Rev. A www.3peakic.com TP09          Stable  6MHz,  Dual  Low  Cost  Op  Amps connected as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and the inputs of the amplifier. It is recommended that signal traces be kept at least 5mm from supply lines to minimize coupling. A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and other points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple effects, orient resistors so heat sources warm both ends equally. Input signal paths should contain matching numbers and types of components, where possible to match the number and type of thermocouple junctions. For example, dummy components such as zero value resistors can be used to match real resistors in the opposite input path. Matching components should be located in close proximity and should be oriented in the same manner. Ensure leads are of equal length so that thermal conduction is in equilibrium. Keep heat sources on the PCB as far away from amplifier input circuitry as is practical. The use of a ground plane is highly recommended. A ground plane reduces EMI noise and also helps to maintain a constant temperature across the circuit board. Instrumentation Amplifier The TP09 op-amp series is well suited for conditioning sensor signals in battery-powered applications. Figure 4 shows a two op-amp instrumentation amplifier, using the TP09 op-amp. The circuit works well for applications requiring rejection of Common Mode noise at higher gains. The reference voltage (VREF) is supplied by a low-impedance source. In single voltage supply applications, VREF is typically VDD/2. VOUT =(V1  V2 )(1  R1 2 R1  )  VREF R2 RG   Figure 4 Gain-of-100 Amplifier Circuit Figure 5 shows a Gain-of-100 amplifier circuit using two TP09 op-amp. It draws 500 uA total current from supply rail, and has a -3dB frequency at 100kHz. Figure 6 shows the small signal frequency response of the circuit. Figure 5: 100kHz, 500μA Gain-of-100 Amplifier www.3peakic.com Rev. A 11  TP09           Stable 6MHz, Dual, Low Cost Op Amps Figure 6: Frequency response of 100kHz, 500uA Gain-of-100 Amplifier 12  Rev. A www.3peakic.com TP09          Stable  6MHz,  Dual  Low  Cost  Op  Amps Package Outline Dimensions SOP-8   A2 C θ L1 A1 e E D Symbol E1 b Dimensions Dimensions In In Millimeters Inches Min Max Min Max A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 C 0.190 0.250 0.007 0.010 D 4.780 5.000 0.188 0.197 E 3.800 4.000 0.150 0.157 E1 5.800 6.300 0.228 0.248 e 1.270 TYP 0.050 TYP L1 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8°   www.3peakic.com Rev. A 13