PSMN2R0-30YLDX

PSMN2R0-30YLD N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 25 October 2018 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. NextPowerS3 portfolio utilising NXP’s unique “SchottkyPlus” technology delivers high efficiency, low spiking performance usually associated with MOSFETs with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits • • • • • • • • Ultra low QG, QGD and QOSS for high system efficiency, especially at higher switching frequencies Superfast switching with soft-recovery; s-factor > 1 Low spiking and ringing for low EMI designs Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at 25 °C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Power SO8 package; no glue, no wire bonds, qualified to 175 °C Wave solderable; exposed leads for optimal visual solder inspection 3. Applications • • • • • • On-board DC-to-DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 30 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - - 100 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 142 W Tj junction temperature -55 - 175 °C VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 2.1 2.5 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 1.61 2 mΩ [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit QGD gate-drain charge - 6.3 - nC QG(tot) total gate charge ID = 25 A; VDS = 15 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 21.8 - nC IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 15 V; Fig. 16 - 1.02 - Simplified outline Graphic symbol Source-drain diode S [1] softness factor Continuous current is limited by package. 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN2R0-30YLD Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 7. Marking Table 4. Marking codes Type number Marking code PSMN2R0-30YLD 2D030L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 30 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 142 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - 100 A VGS = 10 V; Tmb = 100 °C; Fig. 2 [1] - 100 A - 793 A IDM PSMN2R0-30YLD Product data sheet peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 2 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Tstg Conditions Min Max Unit storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage 1000 - V - 100 A - 793 A - 397 mJ HBM Source-drain diode IS source current Tmb = 25 °C [1] ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C Avalanche ruggedness EDS(AL)S [1] [2] non-repetitive drainID = 25 A; Vsup ≤ 30 V; RGS = 50 Ω; source avalanche energy VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 815 µs [2] Continuous current is limited by package. Protected by 100% test 03aa16 120 aaa-008403 200 ID (A) Pder (%) 150 80 (1) 100 40 50 0 0 50 100 150 Tmb (°C) 0 200 0 25 50 75 100 125 150 175 Tmb (°C) 200 (1) Capped at 100A due to package Fig. 1. Normalized total power dissipation as a function of mounting base temperature PSMN2R0-30YLD Product data sheet Fig. 2. Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 3 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology ID (A) aaa-008404 103 Limit RDSon = VDS / ID tp = 10 us 102 100 us 10 DC 1 ms 10 ms 100 ms 1 10-1 10-1 Fig. 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from Fig. 4 junction to mounting base - 0.92 1.06 K/W Rth(j-a) thermal resistance from Fig. 5 junction to ambient Fig. 6 - 50 - K/W - 125 - K/W aaa-008447 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 10-1 0.1 P δ= 0.05 0.02 10-2 10-6 Fig. 4. single shot 10-5 10-3 10-2 T t tp 10-4 tp T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 4 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology aaa-005751 aaa-005750 Fig. 5. PCB layout for thermal resistance junction to ambient 1” square pad; FR4 Board; 2oz copper Fig. 6. PCB layout for thermal resistance junction to ambient minimum footprint;FR4 board; 2oz copper 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C 1.2 1.7 2.2 V ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 150 °C - -4.4 - mV/K IDSS drain leakage current VDS = 24 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 24 V; VGS = 0 V; Tj = 125 °C - 1.7 - µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 2.1 2.5 mΩ VGS = 4.5 V; ID = 25 A; Tj = 150 °C; Fig. 10; Fig. 11 - - 4.2 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 1.61 2 mΩ VGS = 10 V; ID = 25 A; Tj = 150 °C; Fig. 10; Fig. 11 - - 3.3 mΩ f = 1 MHz - 0.9 - Ω ID = 25 A; VDS = 15 V; VGS = 10 V; Fig. 12; Fig. 13 - 46 - nC ID = 25 A; VDS = 15 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 21.8 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 41.5 - nC ID = 25 A; VDS = 15 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 6.8 - nC - 4.5 - nC Static characteristics V(BR)DSS IGSS RDSon RG gate leakage current drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gatesource charge PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 5 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit QGS(th-pl) post-threshold gatesource charge - 2.3 - nC QGD gate-drain charge VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 15 V; Fig. 12; Fig. 13 - 6.3 - nC - 2.5 - V Ciss input capacitance Coss output capacitance VDS = 15 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 14 - 2969 4157 pF Crss reverse transfer capacitance - 1477 2068 pF - 206 453 pF td(on) turn-on delay time - 19 - ns tr rise time - 31 - ns td(off) tf turn-off delay time - 24 - ns fall time - 19 - ns Qoss output charge VGS = 0 V; VDS = 15 V; f = 1 MHz; Tj = 25 °C - 31.6 - nC VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V; RG(ext) = 5 Ω Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.8 1.2 V trr reverse recovery time - 37.5 - ns Qr recovered charge IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 15 V; Fig. 16 [1] - 32 - nC ta reverse recovery rise time - 18.6 - ns tb reverse recovery fall time - 18.9 - ns S softness factor - 1.02 - [1] includes capacitive recovery 150 10 V ID (A) aaa-008405 4.5 V RDSon (mΩ) 5 VGS = 3 V 120 aaa-008406 6 4 90 2.8 V 3 60 2 2.6 V 30 1 2.4 V 0 Fig. 7. 0 0.5 1 1.5 2 VDS (V) 0 2.5 Output characteristics; drain current as a Fig. 8. function of drain-source voltage; typical values PSMN2R0-30YLD Product data sheet 0 2 6 8 10 12 14 VGS (V) 16 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 25 October 2018 4 © Nexperia B.V. 2018. All rights reserved 6 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology aaa-008407 200 ID (A) aaa-008408 20 RDSon (mΩ) 2.8 V 3V 16 150 12 100 8 50 0 Fig. 9. 150°C 0 0.8 1.6 Tj = 25°C 2.4 3.2 VGS (V) 0 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values VGS = 10 V 0 30 60 90 120 ID (A) 150 Fig. 10. Drain-source on-state resistance as a function of drain current; typical values VDS ID 10 V 1.6 VGS(pl) 1.2 VGS(th) VGS = 4.5 V 0.8 VGS QGS2 QGS1 0.4 0 -60 4.5 V 003aal037 2 a 3.5 V 4 -30 0 30 60 90 120 150 Tj (°C) 180 QGS QGD QG(tot) 003aaa508 Fig. 12. Gate charge waveform definitions Fig. 11. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 7 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology VGS (V) aaa-008409 10 aaa-008410 104 C (pF) Ciss 8 Coss 103 6 24 V 15 V 4 Crss 102 VDS = 6 V 2 0 0 10 20 30 40 50 QG (nC) 10 10-1 60 10 VDS (V) 003aal160 aaa-008411 103 102 Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Fig. 13. Gate-source voltage as a function of gate charge; typical values IS (A) 1 ID (A) 102 trr ta 0 10 0.25 IRM 1 10-1 tb 150°C 0 0.2 0.4 Tj = 25°C 0.6 0.8 IRM 1 VSD (V) t (s) 1.2 Fig. 16. Reverse recovery timing definition Fig. 15. Source current as a function of source-drain voltage; typical values PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 8 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 11. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) mm A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 9 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 12. Soldering Footprint information for reflow soldering SOT669 4.7 4.2 0.9 (3×) 0.25 (2×) 0.25 (2×) 0.6 (4×) 3.45 0.6 (3×) 2 3.5 2.55 0.25 (2×) SR opening = Cu + 0.075 1.1 2.15 3.3 SP opening = Cu - 0.050 0.7 (4×) 1.27 3.81 solder lands solder paste 125 µm stencil solder resist occupied area Dimensions in mm sot669_fr Fig. 18. Reflow soldering footprint for LFPAK56; Power-SO8 (SOT669) PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 10 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Wave soldering footprint information for LFPAK56 package SOT669 4.826 1.78 1.72 2.1 1.4 0.6 (x4) 1.27 0.635 solder lands Dimensions in mm Issue date 15-04-13 15-04-16 sot669_fw Fig. 19. Wave soldering footprint for LFPAK56; Power-SO8 (SOT669) PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 11 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology 13. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 12 / 13 PSMN2R0-30YLD Nexperia N-channel 30 V, 2.0 mΩ logic level MOSFET in LFPAK56 using NextPowerS3 Technology Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 2 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline.......................................................... 9 12. Soldering................................................................... 10 13. Legal information......................................................12 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 October 2018 PSMN2R0-30YLD Product data sheet All information provided in this document is subject to legal disclaimers. 25 October 2018 © Nexperia B.V. 2018. All rights reserved 13 / 13