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VC0738 Brief Data Sheet
VC0738BTAA
Brief Data Sheet
Revision 0.21
Notes1: The information is subject to change without notice. Before using this
document, please confirm that this is the latest version.
Notes2: Not all products and/or types are available in every country. Please
check with a Vimicro sales representative availability and additional
information.
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VC0738 Brief Data Sheet
Important Notice
Vimicro Corporation and its subsidiaries reserve the right to make corrections,
modifications, enhancements, improvements, and other changes to its products and
services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and
should verify that such information is current and complete. All products are sold
subject to Vimicro’s terms and conditions of sale supplied at the time of order
acknowledgment.
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granted under any Vimicro patent right, copyright, mask work right, or other Vimicro
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Reproduction of information in Vimicro data books or data sheets is permissible only if
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Resale of Vimicro products or services with statements different from or beyond the
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Revision Table
Date
Rev.
2014-4-1
0.10
2014-4-29
0.20
2014-7-25
0.21
Author
Wan Hongxing
Wan Hongxing
Wan Hongxing
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VC0738 Brief Data Sheet
Content of revision
The initial version
Update Ball function description
Update Feature List
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VC0738 Brief Data Sheet
Contents
1
INTRODUCTION ............................................................................................................................. 5
1.1 Overview ..................................................................................................... 5
1.2 Typical Applications: .................................................................................... 5
1.3 Key Specification......................................................................................... 7
1.3.1 Overview............................................................................................ 7
1.3.2 Process Core ..................................................................................... 7
1.3.3 Video Encoding and Decoding Protocols........................................... 7
1.3.4 Video Encoding and Decoding .......................................................... 8
1.3.5 Intelligent Video Analysis ................................................................... 8
1.3.6 Video and Graphic Processing .......................................................... 9
1.3.7 Graphic engine .................................................................................. 9
1.3.8 Audio Encoding and Decoding ........................................................ 10
1.3.9 Video Interfaces ............................................................................... 10
1.3.10 Audio Interfaces ............................................................................... 11
1.3.11 Ethernet Port .................................................................................... 11
1.3.12 SATA Port ......................................................................................... 11
1.3.13 USB Port .......................................................................................... 11
1.3.14 Peripherals ...................................................................................... 12
1.3.15 Memory Interfaces .......................................................................... 12
1.3.16 Physical Specifications .................................................................... 12
1.4 Boot Modes ............................................................................................... 13
2
HARDWARE .................................................................................................................................. 14
2.1 Package and Pinout .................................................................................. 14
2.1.1 Package........................................................................................... 14
2.1.2 Pin Maps.......................................................................................... 15
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VC0738 Brief Data Sheet
1 Introduction
1.1 Overview
The Vimicro VC0738BTAA is a multimedia processing SoC which is dedicated to
the application of digital video surveillance system, which integrates ARM9 processor,
a hardware H.264 video codec, a 2D graphics engine, some storage interfaces and
many peripheral interfaces.
VC0738BTAA supports H.264 encoding which may be two channels with full HD
1080P@60fps, eight channels with 720P@20fps, or maximum to eight
channels SD(D1 or 960H)@25fps, or 16 channels CIF@25fps. At the same time, the
integration of H.264 decoder can support one 1080P@60fps, or 4
channels 720P/SD(D1 or 960H)@25fps, or 16 channels CIF@25fps decoding.
Through the integration of 10M/100M Ethernet MAC with integrated Ethernet
PHY, VC0738BTAA can be connected to the Ethernet to realize the transmission and
control of communications and other functions of the video stream. VC0738BTAA can
also be connected to network through the USB, SDIO interface with WIFI or
3G interface module.
VC0738BTAA integrate 2 SATA interfaces, which can be connected to the hard
disk and other equipment to as storage of audio and video stream. VC0738BTAA can
also use a USB adapter, SDIO interface to connect to the SD card or other storage
device.
Display and graphics engine of VC0738BTAA can support full HD resolution of
1920X1080, and also support integration of HDMI, VGA, CVBS, LCD and other
video output interface circuit.
VC0738BTAA external 16/32bits DDR3 is compatible with JEDEC standard, which
support data rates of up to 1600 Mb/s (800 MHz) in TSMC 55GP.
As a high performance, high integration SOC, VC0738BTAA is used mainly for the
DVR. And also meet a simple scene HD IPC application and NVR application
1.2 Typical Applications:
The VC0738BTAA is a professional high-end system-on-chip (SoC) designed for
multi-channel 960H/D1 and high-definition (HD) digital video recorders (DVRs) and
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VC0738 Brief Data Sheet
network video recorders (NVRs).With a high-performance ARM926 processor, an
engine supporting up to 8-channel D1/16-channels CIF real-time encoding and
decoding, the VC0738BTAA meets the rising demand for HD and network
applications. The VC0738 also provides an outstanding video engine, various
encoding/decoding algorithms, and multi-channel HD output capability.
These features guarantee users a high-quality image experience. In addition, the
VC0738 supports various highly-integrated peripheral interfaces to meet customer
requirements for functionality, features, and image quality, while reducing the
engineering bill of material (EBOM) cost. The VC0738 is applicable to the following
typical scenarios:
DVR
DVR for 4xD1/960H@25fps+4xCIF/480H@25fps encoding + 4xD1/960H@25fps
decoding
DVR for 4x720P@25fps+4xD1@25fps encoding + 4x720P@25fps decoding
DVR for 8xD1/960H@25fps+8xCIF/480H@25fps encoding + 4xD1/960H@25fps
decoding
DVR for 8x720P@20fps+8xD1@20fps encoding + 1x720P@20fps decoding
DVR for 16xCIF@25fps encoding+16xQCIF@25fps encoding + 16xCIF@25fps
decoding
DVR for 16xD1@>20fps+16xCIF encoding + 16xD1@>20fps decoding
NVR
NVR for 4xD1/4x960H@25fps decoding
NVR for 4x720P@25fps decoding
NVR for 1x1080P@60fps decoding
IPC
IPC for 1x1080P@60fps real-time encoding
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VC0738 Brief Data Sheet
1.3 Key Specification
1.3.1 Overview
Figure 1-1
Show the logic block diagram
RS-485
RS-232
I2C
x2
...
BT.656 In (1~16) ch
BT.1302 In (1~16) ch
SMPTE-296M In(1~2) ch
BT.1120 In (1~2) ch
Audio In/Out
(16+1) ch
Video
Input
Audio Codec
Audio
Input
Audio
Ouput
DDR
DDR3
UART/IR
x4
PWM
x2
Video
Pre- & PostProcessing
SPI
x3
GPIO
JTAG
BT.656
Output
VGA
CVBS
MJPEG Codec
H.264 Codec
HDMI
CPU
ARM926 600Mhz
SDIO
x2
EPHY
GPU
USB
HOST
USB
Device
wireless
LCD
USB
OTG
SATA
x2
USB
Host/Device
Network
1.3.2 Process Core
The VC0738BTAA uses the ARM926 with the maximum frequency 600MHz
16K Bytes I-cache and 16K Bytes D-cache
2 32bit Timer, each 32bit timer can be divided into 2 16bit timer
1.3.3 Video Encoding and Decoding Protocols
H.264 Baseline Profile Level 4.2
H.264 Main Profile Level 4.2
H.264 High Profile Level 4.2
MJPEG/JPEG Baseline
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VC0738 Brief Data Sheet
1.3.4 Video Encoding and Decoding
H.264 encoding of multiple streams
-
H.264 Decoding of multiple streams
-
No B frame support
16xCIF@25fps + 16xQCIF@25fps
4xD1@25fps + 4xCIF@25fps
4x960H@25fps + 4x480H@25fps
4x720P@25fps + 4xD1@25fps
8xD1@25fps + 8xCIF@25fps
8x720P@20fps + 8xD1@20fps
1x1080P@30fps+ 1xD1@30fps + 1xCIF@30fps
1x1080P@60fps with 1/2 pixel resolution
CBR/VBR
No B frame support
4xD1@25fps
4x960H@25fps
4x720P@25fps
8xD1@25fps
8x960H@25fps
16xCIF@25fps
1x1080P@60fps
MJPEG/JPEG Encoding and Decoding
-
When recording with H.264, maximum support 1080P@5fps
When Only JPEG encoding, support maximum 5M@5fps
Decoding the same as encoding
1.3.5 Intelligent Video Analysis
Motion detection
Boundary security
Video diagnosis
Invisible watermark
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VC0738 Brief Data Sheet
1.3.6 Video and Graphic Processing
Video pre- and post-processing, including frame dropping, lens cover detection,
de-interlacing, image enhancement, edge enhancement, and 3D denoising
Anti-flicker for output videos and graphics
1/64x to 16x video scaling
1/64x to 16x graphic scaling
Flip/Mirror
On-screen display (OSD) overlay of whole video or graphic layer before encoding
POP
Alpha blending of video layers and graphics layers
Progressive conversion to interlaced (mainly used for standard BT656 and CVBS
output)
1.3.7 Graphic engine
Bit blit, stretch blit, pattern blit and fast clear
Line drawing
Rectangle fill and clear
Mono expansion for text rendering
Anti-aliased font support
ROP2, ROP3, ROP4
Alpha blending
90/180/270 degree rotation
Vertical and Horizontal mirror
Transparency by monochrome mask, chroma key or pattern mask
High quality 9-tap filter for scaling
32K x 32K coordinate system
Color space conversion between YUV and RGB for both BT709 and BT601
Clipping window
Color Index Input conversion Support
Filter Blit
Input Formats: (Only Filter Blit support YUV input)
-
A1R5G5B5
A4R4G4B4
A8R8G8B8
X1R5G5B5
X4R4G4B4
X8R8G8B8
RGB565
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VC0738 Brief Data Sheet
NV12 (semi-planer YUV420)
NV16 (semi-planer YUV422)
YUY2(package YUV422)
UYVY(package YUV422)
YV12(planer YUV420)
8-bit color index
1-bit monochrome
The output data Formats:
-
A1R5G5B5
A4R4G4B4
A8R8G8B8
X1R5G5B5
X4R4G4B4
X8R8G8B8
RGB565
YUV422 interlaced
1.3.8 Audio Encoding and Decoding
ADPCM,G711 and G726 hardware encoding with maximum 17 streams
G723 and G729 software encoding
Software decoding complying with various protocols
1.3.9 Video Interfaces
Video input interfaces
-
4xBT656@27/54/108MHz for 16 real-time inputs
4x960H@36/72/144MHz for 16 real-time inputs
2x720P@30fps/60fps for 2 real-time inputs (SMPTE-296M)
4x720P@30fps for 8 real-time inputs (one port mulplex two 720P bitstream)
2x1080P@148.5MHz for 2x1080P real-time inputs (one is DVP, one is
BT1120)
Video output interfaces
-
HDMI 1.3+VGA+CVBS outputs, The HDMI and VGA outputs can share the
same source
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-
VC0738 Brief Data Sheet
1xLCD and 1xBT656@27Mhz digital video output. The BT.656 and CVBS
outputs share the same source
Maximum 1080P@60fps for HDMI or VGA
Graphics layers can support ARGB8888, RGB unpacked in 32bits,
ARGB5555,RGB565 in 16bits, with the maximum resolution of 1920x1080
1.3.10 Audio Interfaces
The VC0738BTAA has three inter-IC sound (I2S) interfaces. The details are as
follows:
Two for inputs
One for output
Audio format support 8bit/16bits sampling, the sampling rate are 8K,16K,32K and
48K
Configurable master/slave mode
1.3.11 Ethernet Port
The VC0738BTAA has one built-in megabit media access port. The details are as
follows:
MII mode
10/100 Mbit/s full-duplex or half-duplex mode
Integrated EMAC PHY
1.3.12 SATA Port
The VC0738BTAA has two SATA ports. The details are as follows
Integrated SATA controller and PHY
Two serial advanced technology attachment 2.6 (SATA2.6) interfaces. Maximum
speed up to 3Gbps
Support external SATA PM extended SATA equipment
1.3.13 USB Port
The VC0738 has two universal serial bus 2.0(USB2.0) ports. The details are as
follows:
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VC0738 Brief Data Sheet
Integrated USB2.0 controller + PHY
One HOST
One OTG
1.3.14 Peripherals
The VC0738BTAA has the following peripheral interfaces:
Four universal asynchronous receiver transmitter (UART) interfaces
Two inter integrated circuit (I2C) interfaces
Three serial peripheral (SPI) interfaces
Two secure digital input/output 2.0 (SDIO2.0) interface
Two pulse width modulation (PWM) interfaces
Multiple general purpose input/output (GPIO) interfaces
1.3.15 Memory Interfaces
The VC0738BTAA has the following memory interfaces:
One external 16- or 32-bit DDR3 synchronous dynamic random access memory
controller interface
-
Maximum frequency of 800Mhz
Support up to 512MB
One-die termination (ODT)
Automatic power consumption control
SPI NOR flash interfaces
-
1 bit SPI NOR flash interfaces
Maximum capacity of 32 MB for CS
Built-in 16KB BOOTROM and 32KB SRAM
1.3.16 Physical Specifications
Power consumption
2.5 W maximum power consumption
Multi-level power-saving control
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Operating voltage
1.0 V core voltage
3.3/2.8/2.5/1.8V I/O voltage and 5 V margin voltage
1.5 V DDR3 SDRAM interface voltage
Operating temperature ranging from -20℃ to +85℃
Package
Wire bonding fine ball grid array 441 (FBGA441)
Body pitch: 0.8 mm (0.031 in.)
Body size: 19mm x 19 mm (0.75 in x 0.75 in.)
VC0738 Brief Data Sheet
1.4 Boot Modes
The VC0738BTAA can boot from:
BOOTROM as first level hardware boot
SPI flash as second level software boot
The debug interface (JTAG for boot code, UART, USB for OS debugging and
applications)
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VC0738 Brief Data Sheet
2 Hardware
2.1 Package and Pinout
2.1.1 Package
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VC0738 Brief Data Sheet
2.1.2 Pin Maps
A
B
C
D
E
F
G
H
J
K
L
M
1
VSS
UART0_TX
UART0_RTSN
I2C0_SCK
I2C0_SDA
UOTG_DP
UHOST_DP
TXN
RXN
VDD33_EPHY
SATA_TX0_P
VSS
2
UART0_RX
UART0_CTSN
I2S0_SDI
I2S01_MCLK
I2S0_WS
UOTG_DM
UHOST_DM
TXP
RXP
VDD33_EPHY
SATA_TX0_M
SATA_RX0_M
3
4
UART1_TX
DCVI0_DATA[7]
UART1_RX
DCVI0_DATA[6]
I2S0_SCLK DCVI2_DATA[7]
I2S2_MCLK DCVI2_DATA[6]
I2S2_SDO
I2S2_SCLK
UOTG_VBUS I2S2_WS
UOTG_ID
SPI0_SSN
TEST
SPI0_SCK
SPI0_MOSI SPI0_MISO
UOTG_VSSA UHOST_VDD33
UOTG_RREFEXTVSS
UOTG_VSSAC UHOST_RREFEXT
Figure 2-1
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5
DCVI0_DATA[5]
DCVI0_DATA[4]
DCVI2_DATA[5]
DCVI2_DATA[4]
6
DCVI0_DATA[3]
DCVI0_DATA[2]
DCVI2_DATA[3]
DCVI2_DATA[2]
7
DCVI0_DATA[1]
DCVI0_DATA[0]
DCVI2_DATA[1]
DCVI2_DATA[0]
8
DCVI0_CLK
VDD_IO_DCVI
VDD_IO_DCVI
DCVI2_CLK
9
DCVI1_CLK
VDD_IO_DCVI
VDD_IO_DCVI
DCVI3_CLK
10
DCVI1_DATA[7]
DCVI1_DATA[6]
DCVI3_DATA[7]
DCVI3_DATA[6]
11
DCVI1_DATA[5]
DCVI1_DATA[4]
DCVI3_DATA[5]
DCVI3_DATA[4]
12
DCVI1_DATA[3]
DCVI1_DATA[2]
DCVI3_DATA[3]
DCVI3_DATA[2]
GPIO[5]
GPIO[4]
GPIO[3]
VDD_IO_SYS
VDD_IO_SYS
UOTG_VDD33
UHOST_VSSA
VDD_IO_LCD
VDD_IO_LCD
VDD_IO_SYS
VDD_IO_SYS
VSS
VSS
VSS
VDD_IO_LCD
VDD_IO_LCD
GPIO[7]
GPIO[6]
GPIO[9]
GPIO[8]
GPIO[11]
GPIO[10]
GPIO[13]
GPIO[12]
GPIO[24]
VSS
VSS
VSS
GPIO[25]
VSS
VSS
VSS
GPIO[26]
VSS
VSS
VSS
GPIO[27]
VSS
VSS
VSS
Pin Allocation of FBGA (left-top)
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N
P
R
T
U
V
W
Y
AA
AB
AC
SATA_RX0_P
SATA_RX1_P
VSS
SATA_TX1_P
VDD_IO_DDR
VDD_IO_DDR
DDR_A2
DDR_A9
DDR_A7
DDR_A0
VSS
1
VSS
SATA_RX1_M
SATA_TX1_M
VSS
VDD_IO_DDR
VDD_IO_DDR
DDR_A13
DDR_RSTN
DDR_A5
DDR_A3
DDR_BA0
2
UHOST_VSSAC VSS_EPHY
RTX
VSS_EPHY
SATA_VP25 SATA_VP25
SATA_VP25 SATA_VP25
VDD_IO_DDR VDD_IO_DDR
VDD_IO_DDR VDD_IO_DDR
VDD_IO_DDR VDD_IO_DDR
VDD_IO_DDR VDD_IO_DDR
VDD_IO_DDR DDR_CASN
DDR_BA2
DDR_ODT
DDR_CSN
DDR_WEN
3
4
Figure 2-2
VDD_IO_DDR
VDD_IO_DDR
DDR_DQ1
DDR_RASN
5
VSS
SATA_REXT
VSS
VSS
VDD_IO_DDR
VDD_IO_DDR
VSS
VSS
VSS
VSS
VDD_IO_DDR
VDD_IO_DDR
VSS
VSS
DDR_DQ3
VSS
6
VSS
VSS
VSS
DDR_DQ0
7
15
HDMI_RBIAS
AVSS33_HDMI
HDMI_CEC
VDD_IO_HDMI
16
AVSS33_ESD
AVSS33_ESD
HDMI_DSCL
VDD_IO_LCD
17
AVDD33_ESD
AVDD33_ESD
HDMI_DSDA
VDD_IO_LCD
18
HDMI_TX2N
HDMI_TX2P
HDMI_HPD
VSS
GPIO[15]
GPIO[14]
VDD_IO_LCD
VDD_IO_LCD
GPIO[17]
GPIO[16]
GPIO[19]
GPIO[18]
GPIO[0]
VSS
VSS
VSS
GPIO[1]
VSS
VSS
VSS
GPIO[2]
VSS
VSS
VSS
GPIO[21]
GPIO[20]
EMAC_RXDV
EMAC_TXD2
EMAC_TXER
EMAC_MDIO
EMAC_RCK
GPIO[23]
GPIO[22]
EMAC_TXD1
EMAC_TXD3
EMAC_TXEN
EMAC_MDC
EMAC_TCK
Vimicro Copyright© 1999-2014
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VSS
VDD_IO_DDR
VSS
VSS
VDD_CORE
VSS
VDD_CORE
DDR_PLL_VDD
VDD_CORE
DDR_PLL_VDD
DDR_DQ22
DDR_DQ20
DDR_DM1
DDR_DQ2
8
DDR_DQ18
DDR_DQ16
DDR_DQ13
VSS
9
DDR_DM3
DDR_DQ26
VSS
DDR_DQ11
10
DDR_DQ29
DDR_DQ28
DDR_DQ15
DDR_DQ9
11
DDR_DQS2_P
DDR_DQ25
DDR_DQS0_P
VSS
12
Pin Allocation of FBGA (left-bottom)
13
14
DCVI1_DATA[1]AVDD33_HDMI
DCVI1_DATA[0]VSS
DCVI3_DATA[1]HDMI_VSS3IO
DCVI3_DATA[0]HDMI_VSS3IO
Figure 2-3
VC0738 Brief Data Sheet
19
HDMI_TX1N
HDMI_TX1P
EMAC_COL
EMAC_CRS
20
HDMI_TX0N
HDMI_TX0P
EMAC_RXD0
EMAC_RXD1
EMAC_RXER
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
VDD_IO_SYS
VGA0_HSYNC
VGA1_HSYNC
21
HDMI_TXCN
HDMI_TXCP
EMAC_RXD2
EMAC_RXD3
EMAC_TXD0
SDIO0_DATA[3]
RSTN
SDIO0_LOCKN
SDIO0_DETECTN
VSSA_PLL0
VGA1_VSYNC
VGA0_VSYNC
22
VDD_IO_SYS
JTG_TCK
JTG_TMS
JTG_RTCK
SDIO0_CMD
SDIO0_DATA[1]
VSS
VDD_IO_SYS
XCLKOUT
VDDA_PLL1
VDDA_PLL3
VSSA_PLL1
23
VSS
JTG_TDI
JTG_TDO
JTG_TRSTN
SDIO0_CLK
SDIO0_DATA[0]
SDIO0_DATA[2]
VDD_IO_SYS
XCLKIN
VDDA_PLL0
VDDA_PLL2
VSSA_PLL2
Pin Allocation of FBGA (right-top)
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A
B
C
D
E
F
G
H
J
K
L
M
www.vimicro.com
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
DDR_PLL_VDD DDR_PLL_VSS DDR_PLL_VSS DDR_PLL_VSS DDR_DTO[0]
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
DDR_DTO[1]
DDR_DQS3_P
DDR_DQS2_N
VSS
DDR_DQS0_N
13
DDR_DQ31
DDR_DQS3_N
DDR_DQS1_N
DDR_DQS1_P
14
DDR_DQ30
DDR_DQ24
DDR_DQ12
VSS
15
DDR_DQ21
DDR_DQ19
DDR_DM0
VSS
18
DDR_DM2
DDR_DQ27
VSS
DDR_DQ8
16
Figure 2-4
DDR_DQ23
DDR_DQ17
DDR_DQ14
DDR_DQ10
17
DDR_ZQ
DDR_ATO
VSS
DDR_DQ4
19
VC0738 Brief Data Sheet
VSS
VDAC0_PGND1
VDAC0_PVDD1
VDAC0_REXT
VDAC1_PVDD1
VDAC1_PVDD1
VDAC1_PGND1
VSS
VSS
DDR_DQ7
DDR_DQ6
20
VDDA_PLL4
VDAC0_PGND1
VDAC0_PVDD2
VDAC1_REXT
VDAC1_PVDD2
VDAC1_PVDD1
VDAC1_PGND1
DDR_VREF
DDR_CKE
DDR_DQ5
VSS
21
VSSA_PLL4
VDAC0_OUTP2
VDAC0_VDREF
VDAC1_VDREF
VDAC1_OUTP2
DDR_A14
DDR_A8
DDR_A4
DDR_BA1
DDR_CLK_N
DDR_CLK_P
22
VSSA_PLL3
VDAC0_OUTP1
VDAC0_OUTP0
VDAC1_OUTP0
VDAC1_OUTP1
DDR_A1
DDR_A11
DDR_A6
DDR_A12
DDR_A10
VSS
23
N
P
R
T
U
V
W
Y
AA
AB
AC
Pin Allocation of FBGA (right-bottom)
Table 2-1 Signal Description of VC0738BTAA
Pin Name
Pin
Pin
No.
Type
I/O
State
Drive
Power
After
Strength
Or
Reset
(mA)
Range(v)
Release
Pin Description
RSTN
G21
I,Sh
4mA
VDD_IO_SYS
I,RSTN
Reset Signal Input
XCLKIN
J23
I,Sh
4mA
VDD_IO_SYS
I,XCLKIN
External Crystal Input for System
Clock
XCLKOUT
J22
O
4mA
VDD_IO_SYS
O,XCLKOU
External Crystal Ouput for System
T
Clock
TEST
H3
I,PD
4mA
VDD_IO_SYS
I,TEST
Test Mode Enable
JTG_TCK
B22
B,PD,
4mA
VDD_IO_SYS
I,JTG_TCK,
JTAG Test Clock, share with
PD
LCD_DE, share with
Sh
emacphy_padc_dpx_led, share
with GPIO0[0]
JTG_TDI
B23
B,PD
4mA
VDD_IO_SYS
I,JTG_TDI,P
JTAG Test Data Input, share with
D
LCD_HSYNC, share with
emacphy_padc_lnk_led, share
with GPIO0[1]
JTG_TDO
C23
B,PD
4mA
VDD_IO_SYS
O,JTG_TDO
JTAG Test Data Output, share
,PD
with LCD_VSYNC, share with
emacphy_padc_spd_led, share
with GPIO0[2]
Vimicro Copyright© 1999-2014
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JTG_TMS
C22
B,PD
8mA
VDD_IO_SYS
VC0738 Brief Data Sheet
I,JTG_TMS,
JTAG Test Mode Select, share
PD
with LCD_PCLK, share with
sata_p0_act_led, share with
GPIO0[3]
JTG_TRSTN
D23
B,PU
4mA
VDD_IO_SYS
I,JTG_TRST
JTAG Test Reset, active low,
N,PU
share with SDIO1_CLK, share
with sata_p1_act_led, share with
GPIO0[4]
JTG_RTCK
D22
B,PD
4mA
VDD_IO_SYS
O,JTG_RTC
PWM0 output, share with
K,PD
SDIO1_CMD, share with PWM0,
share with GPIO0[5]
GPIO[0]
J13
B,PD
8mA
VDD_IO_LCD
I,GPIO[0],P
GPIO[0], share with
D
LCD_DATA[0], share with PWM1,
share with UM_OUT[0]
GPIO[1]
J14
B,PD
8mA
VDD_IO_LCD
I,GPIO[1],P
GPIO[1], share with
D
LCD_DATA[1], share with
UM_OUT[1]
GPIO[2]
J15
B,PD
8mA
VDD_IO_LCD
I,GPIO[2],P
GPIO[2], share with
D
LCD_DATA[2], share with
UM_OUT[2]
GPIO[3]
H6
B,PD
8mA
VDD_IO_LCD
I,GPIO[3],P
GPIO[3], share with
D
LCD_DATA[3], share with
UART2_TX, share with
UM_OUT[3]
GPIO[4]
G6
B,PD
8mA
VDD_IO_LCD
I,GPIO[4],P
GPIO[4], share with
D
LCD_DATA[4], share with
UART2_RX, share with
UM_OUT[4]
GPIO[5]
F6
B,PD
8mA
VDD_IO_LCD
I,GPIO[5],P
GPIO[5], share with
D
LCD_DATA[5], share with
UART3_TX, share with
UM_OUT[5]
GPIO[6]
G9
B,PD
8mA
VDD_IO_LCD
I,GPIO[6],P
GPIO[6], share with
D
LCD_DATA[6], share with
UART3_RX, share with
UM_OUT[6]
GPIO[7]
F9
B,PD
8mA
VDD_IO_LCD
I,GPIO[7],P
GPIO[7], share with
D
LCD_DATA[7], share with
SPI1_SCK, share with
UM_OUT[7]
GPIO[8]
G10
Vimicro Copyright© 1999-2014
B,PD
8mA
VDD_IO_LCD
I,GPIO[8],P
GPIO[8], share with
D
LCD_DATA[8], share with
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VC0738 Brief Data Sheet
SPI1_SSN, share with
UM_OUT[8]
GPIO[9]
F10
B,PD
8mA
VDD_IO_LCD
I,GPIO[9],P
GPIO[9], share with
D
LCD_DATA[9], share with
SPI1_MOSI, share with
UM_OUT[9]
GPIO[10]
G11
B,PD
8mA
VDD_IO_LCD
I,GPIO[10],P
GPIO[10], share with
D
LCD_DATA[10], share with
SPI1_MISO, share with
UM_OUT[10]
GPIO[11]
F11
B,PD
8mA
VDD_IO_LCD
I,GPIO[11],P
GPIO[11], share with
D
LCD_DATA[11], share with
SPI2_SCK, share with
UM_OUT[11]
GPIO[12]
G12
B,PD
8mA
VDD_IO_LCD
I,GPIO[12],P
GPIO[12], share with
D
LCD_DATA[12], share with
SPI2_SSN, share with
UM_OUT[12]
GPIO[13]
F12
B,PD
8mA
VDD_IO_LCD
I,GPIO[13],P
GPIO[13], share with
D
LCD_DATA[13], share with
SPI2_MOSI, share with
UM_OUT[13]
GPIO[14]
G13
B,PD
8mA
VDD_IO_LCD
I,GPIO[14],P
GPIO[14], share with
D
LCD_DATA[14], share with
SPI2_MISO, share with
UM_OUT[14]
GPIO[15]
F13
B,PD
8mA
VDD_IO_LCD
I,GPIO[15],P
GPIO[15], share with
D
LCD_DATA[15], share with
UM_OUT[15]
GPIO[16]
G15
B,PD
8mA
VDD_IO_LCD
I,GPIO[16],P
GPIO[16], share with
D
LCD_DATA[16], share with
UM_OUT[16]
GPIO[17]
F15
B,PD
8mA
VDD_IO_LCD
I,GPIO[17],P
GPIO[17], share with
D
LCD_DATA[17], share with
I2S1_SCLK, share with
UM_OUT[17]
GPIO[18]
G16
B,PD
8mA
VDD_IO_LCD
I,GPIO[18],P
GPIO[18], share with
D
LCD_DATA[18], share with
I2S1_WS, share with
UM_OUT[18]
GPIO[19]
F16
Vimicro Copyright© 1999-2014
B,PD
8mA
VDD_IO_LCD
I,GPIO[19],P
GPIO[19], share with
D
LCD_DATA[19], share with
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VC0738 Brief Data Sheet
I2S1_SDI, share with
UM_OUT[19]
GPIO[20]
G17
B,PD
8mA
VDD_IO_LCD
I,GPIO[20],P
GPIO[20], share with
D
LCD_DATA[20], share with
SATA_P0_CP_DET, share with
UM_OUT[20]
GPIO[21]
F17
B,PD
8mA
VDD_IO_LCD
I,GPIO[21],P
GPIO[21], share with
D
LCD_DATA[21], share with
SATA_P1_CP_DET, share with
UM_OUT[21]
GPIO[22]
G18
B,PD
8mA
VDD_IO_LCD
I,GPIO[22],P
GPIO[22], share with
D
LCD_DATA[22], share with
SATA_P0_CP_POD, share with
UM_OUT[22]
GPIO[23]
F18
B,PD
8mA
VDD_IO_LCD
I,GPIO[23],P
GPIO[23], share with
D
LCD_DATA[23], share with
SATA_P1_CP_POD, share with
UM_OUT[23]
GPIO[24]
J9
B,PD
8mA
VDD_IO_DCV
I,GPIO[24],P
GPIO[24], share with
I
D
SDIO0_DATA[4], share with
SIF_PADC_CS_RSTN, share with
UM_OUT[24]
GPIO[25]
J10
B,PD
8mA
VDD_IO_DCV
I,GPIO[25],P
GPIO[25], share with
I
D
SDIO0_DATA[5], share with
CLK_OUT1, share with
UM_OUT[25]
GPIO[26]
J11
B,PD
8mA
VDD_IO_DCV
I,GPIO[26],P
GPIO[26], share with
I
D
SDIO0_DATA[6], share with
SIF_VSYNC, share with
UM_OUT[26]
GPIO[27]
J12
B,PD
8mA
VDD_IO_DCV
I,GPIO[27],P
GPIO[27], share with
I
D
SDIO0_DATA[7], share with
SIF_HSYNC, share with
UM_OUT[27]
GPIO[28]
F20
B,PD
8mA
VDD_IO_LCD
I,GPIO[28],P
GPIO[28], share with
D
SDIO1_DATA[0], share with
I2C1_SCK, share with
UM_OUT[28]
GPIO[29]
G20
B,PD
8mA
VDD_IO_LCD
I,GPIO[29],P
GPIO[29], share with
D
SDIO1_DATA[1], share with
I2C1_SDA, share with
UM_OUT[29]
Vimicro Copyright© 1999-2014
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GPIO[30]
H20
B,PD
8mA
VDD_IO_LCD
VC0738 Brief Data Sheet
I,GPIO[30],P
GPIO[30], share with
D
SDIO1_DATA[2], share with
UM_OUT[30]
GPIO[31]
J20
B,PD
8mA
VDD_IO_LCD
I,GPIO[31],P
GPIO[31], share with
D
SDIO1_DATA[3], share with
UM_OUT[31]
I2C0_SCK
D1
B,Sh,
4mA
VDD_IO_SYS
PU
I2C0_SDA
E1
B,PU
4mA
VDD_IO_SYS
I,GPIO0[6],P
I2C0 Serial Clock, PULL UP IN
U
PCB, share with GPIO0[6]
I,GPIO0[7],P
I2C0 Serial Data, PULL UP IN
U
PCB, share with
GPIO0[7]
UART0_TX
UART0_RX
UART0_RTS
B1
A2
C1
B,PD
B,PU
B,PD
4mA
4mA
4mA
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
N
UART0_CTS
B2
B,PU
4mA
VDD_IO_SYS
N
UART1_TX
UART1_RX
SPI0_SCK
A3
B3
H4
B,PD
B,PU
B,Sh,
4mA
4mA
8mA
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
PD
SPI0_SSN
SPI0_MOSI
SPI0_MISO
SDIO0_CLK
G4
J3
J4
E23
B,PD
B,PD
B,PD
B,Sh,
SDIO0_DATA
E22
F23
B,PD
B,PD
8mA
8mA
8mA
8mA
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
8mA
8mA
VDD_IO_SYS
VDD_IO_SYS
[0]
SDIO0_DATA
F22
B,PD
8mA
VDD_IO_SYS
[1]
SDIO0_DATA
G23
[2]
Vimicro Copyright© 1999-2014
B,PD
UART0 Serial Transmit Port,
D
share with GPIO0[8]
I,GPIO0[9],P
UART0 Serial Receive Port, share
U
with GPIO0[9]
I,GPIO0[10],
UART0 Request to Send, active
PD
low, share with GPIO0[10]
I,GPIO0[11],
UART0 Clear to Send, active low,
PU
share with GPIO0[11]
I,GPIO0[12],
UART0 Serial Transmit Port,
PD
share with GPIO0[12]
I,GPIO0[13],
UART0 Serial Receive Port, share
PU
with GPIO0[13]
I,GPIO0[14],
SPI0 Clock, share with GPIO0[14]
PD
PD
SDIO0_CMD
I,GPIO0[8],P
8mA
VDD_IO_SYS
I,GPIO0[15],
SPI0 Slave Select, share with
PD
GPIO0[15]
I,GPIO0[16],
SPI0 Master Output and Slave
PD
Input, share with GPIO0[16]
I,GPIO0[17],
SPI0 Master Input and Slave
PD
Output, share with GPIO0[17]
I,GPIO0[18],
SDIO0 Clock , share with
PD
GPIO0[18]
I,GPIO0[19],
SDIO0 Command/Response,
PD
share with GPIO0[19]
I,GPIO0[20],
SDIO0 Data 0, share with
PD
GPIO0[20]
I,GPIO0[21],
SDIO0 Data 1, share with
PD
GPIO0[21]
I,GPIO0[22],
SDIO0 Data 2, share with
PD
GPIO0[22]
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SDIO0_DATA
F21
B,PD
8mA
VDD_IO_SYS
[3]
SDIO0_LOCK
H21
B,PU
8mA
VDD_IO_SYS
N
VC0738 Brief Data Sheet
I,GPIO0[23],
SDIO0 Data 3, share with
PD
GPIO0[23]
I,GPIO0[24],
SDIO0 write protect of card
PU
socket, share with CLK_OUT0,
share with GPIO0[24]
SDIO0_DETE
J21
B,PU
8mA
VDD_IO_SYS
I,GPIO0[25],
SDIO0 card-detection of card
PU
socket, share with GPIO0[25]
VDD_IO_DCV
I,GPIO2[0],P
1st port video input clock, share
I
U
with SIF_PCLK, share with
CTN
DCVI0_CLK
A8
B,PU
4mA
GPIO2[0]
DCVI0_DATA
B7
B,PU
4mA
[0]
VDD_IO_DCV
I,GPIO2[1],P
1st port video input data 0, share
I
U
with SIF_DATA[0], share with
GPIO2[1]
DCVI0_DATA
A7
B,PU
4mA
[1]
VDD_IO_DCV
I,GPIO2[2],P
1st port video input data 1, share
I
U
with SIF_DATA[1], share with
GPIO2[2]
DCVI0_DATA
B6
B,PU
4mA
[2]
VDD_IO_DCV
I,GPIO2[3],P
1st port video input data 2, share
I
U
with SIF_DATA[2], share with
GPIO2[3]
DCVI0_DATA
A6
B,PU
4mA
[3]
VDD_IO_DCV
I,GPIO2[4],P
1st port video input data 3, share
I
U
with SIF_DATA[3], share with
GPIO2[4]
DCVI0_DATA
B5
B,PU
4mA
[4]
VDD_IO_DCV
I,GPIO2[5],P
1st port video input data 4, share
I
U
with SIF_DATA[4], share with
GPIO2[5]
DCVI0_DATA
A5
B,PU
4mA
[5]
VDD_IO_DCV
I,GPIO2[6],P
1st port video input data 5, share
I
U
with SIF_DATA[5], share with
GPIO2[6]
DCVI0_DATA
B4
B,PU
4mA
[6]
VDD_IO_DCV
I,GPIO2[7],P
1st port video input data 6, share
I
U
with SIF_DATA[6], share with
GPIO2[7]
DCVI0_DATA
A4
B,PU
4mA
[7]
VDD_IO_DCV
I,GPIO2[8],P
1st port video input data 7, share
I
U
with SIF_DATA[7], share with
GPIO2[8]
DCVI1_CLK
A9
B,PU
4mA
VDD_IO_DCV
I,GPIO2[9],P
2nd port video input clock, share
I
U
with SIF_PADC_CS_PWDN,
share with GPIO2[9]
DCVI1_DATA
B13
B,PU
4mA
[0]
VDD_IO_DCV
I,GPIO2[10],
2nd port video input data 0, share
I
PU
with SIF_DATA[8], share with
GPIO2[10]
DCVI1_DATA
A13
[1]
Vimicro Copyright© 1999-2014
B,PU
4mA
VDD_IO_DCV
I,GPIO2[11],
2nd port video input data 1, share
I
PU
with SIF_DATA[9], share with
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VC0738 Brief Data Sheet
GPIO2[11]
DCVI1_DATA
B12
B,PU
4mA
[2]
VDD_IO_DCV
I,GPIO2[12],
2nd port video input data 2, share
I
PU
with SIF_DATA[10], share with
GPIO2[12]
DCVI1_DATA
A12
B,PU
4mA
[3]
VDD_IO_DCV
I,GPIO2[13],
2nd port video input data 3, share
I
PU
with SIF_DATA[11], share with
GPIO2[13]
DCVI1_DATA
B11
B,PU
4mA
[4]
VDD_IO_DCV
I,GPIO2[14],
2nd port video input data 4, share
I
PU
with SIF_DATA[12], share with
GPIO2[14]
DCVI1_DATA
A11
B,PU
4mA
[5]
VDD_IO_DCV
I,GPIO2[15],
2nd port video input data 5, share
I
PU
with SIF_DATA[13], share with
GPIO2[15]
DCVI1_DATA
B10
B,PU
4mA
[6]
VDD_IO_DCV
I,GPIO2[16],
2nd port video input data 6, share
I
PU
with SIF_DATA[14], share with
GPIO2[16]
DCVI1_DATA
A10
B,PU
4mA
[7]
VDD_IO_DCV
I,GPIO2[17],
2nd port video input data 7, share
I
PU
with SIF_DATA[15], share with
GPIO2[17]
DCVI2_CLK
DCVI2_DATA
D8
D7
B,PU
B,PU
4mA
4mA
[0]
DCVI2_DATA
C7
B,PU
4mA
[1]
DCVI2_DATA
D6
B,PU
4mA
[2]
DCVI2_DATA
C6
B,PU
4mA
[3]
DCVI2_DATA
D5
B,PU
4mA
[4]
DCVI2_DATA
C5
B,PU
4mA
[5]
DCVI2_DATA
D4
B,PU
4mA
[6]
DCVI2_DATA
C4
B,PU
4mA
[7]
DCVI3_CLK
DCVI3_DATA
D9
D13
[0]
Vimicro Copyright© 1999-2014
B,PU
B,PU
4mA
4mA
VDD_IO_DCV
I,GPIO2[18],
3rd port video input clock, share
I
PU
with GPIO2[18]
VDD_IO_DCV
I,GPIO2[19],
3rd port video input data 0, share
I
PU
with GPIO2[19]
VDD_IO_DCV
I,GPIO2[20],
3rd port video input data 1, share
I
PU
with GPIO2[20]
VDD_IO_DCV
I,GPIO2[21],
3rd port video input data 2, share
I
PU
with GPIO2[21]
VDD_IO_DCV
I,GPIO2[22],
3rd port video input data 3, share
I
PU
with GPIO2[22]
VDD_IO_DCV
I,GPIO2[23],
3rd port video input data 4, share
I
PU
with GPIO2[23]
VDD_IO_DCV
I,GPIO2[24],
3rd port video input data 5, share
I
PU
with GPIO2[24]
VDD_IO_DCV
I,GPIO2[25],
3rd port video input data 6, share
I
PU
with GPIO2[25]
VDD_IO_DCV
I,GPIO2[26],
3rd port video input data 7, share
I
PU
with GPIO2[26]
VDD_IO_DCV
I,GPIO3[0],P
4th port video input clock, share
I
U
with GPIO3[0]
VDD_IO_DCV
I,GPIO3[1],P
4th port video input data 0, share
I
U
with GPIO3[1]
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DCVI3_DATA
C13
B,PU
4mA
[1]
DCVI3_DATA
D12
B,PU
4mA
[2]
DCVI3_DATA
C12
B,PU
4mA
[3]
DCVI3_DATA
D11
B,PU
4mA
[4]
DCVI3_DATA
C11
B,PU
4mA
[5]
DCVI3_DATA
D10
B,PU
4mA
[6]
DCVI3_DATA
C10
B,PU
4mA
[7]
I2S2_MCLK
I2S2_SCLK
I2S2_WS
D3
E4
F4
B,PD
B,PD
B,PD
8mA
8mA
8mA
VC0738 Brief Data Sheet
VDD_IO_DCV
I,GPIO3[2],P
4th port video input data 1, share
I
U
with GPIO3[2]
VDD_IO_DCV
I,GPIO3[3],P
4th port video input data 2, share
I
U
with GPIO3[3]
VDD_IO_DCV
I,GPIO3[4],P
4th port video input data 3, share
I
U
with GPIO3[4]
VDD_IO_DCV
I,GPIO3[5],P
4th port video input data 4, share
I
U
with GPIO3[5]
VDD_IO_DCV
I,GPIO3[6],P
4th port video input data 5, share
I
U
with GPIO3[6]
VDD_IO_DCV
I,GPIO3[7],P
4th port video input data 6, share
I
U
with GPIO3[7]
VDD_IO_DCV
I,GPIO3[8],P
4th port video input data 7, share
I
U
with GPIO3[8]
VDD_IO_SYS
I,GPIO3[9],P
Audio input0 Codec Master Clock,
D
share with GPIO3[9]
I,GPIO3[10],
Audio input0 Bit Clock, share with
PD
GPIO3[10]
I,GPIO3[11],
Audio input0 Word Select For
PD
ADC, share with
VDD_IO_SYS
VDD_IO_SYS
GPIO3[11]
I2S2_SDO
I2S01_MCLK
I2S0_SCLK
I2S0_WS
E3
D2
C3
E2
B,PD
B,PD
B,PD
B,PD
8mA
8mA
8mA
8mA
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
I,GPIO3[12],
Audio output Serial Data Output to
PD
DAC, share with GPIO3[12]
I,GPIO3[13],
Audio input0 Codec Master Clock,
PD
share with GPIO3[13]
I,GPIO3[14],
Audio input0 Bit Clock, share with
PD
GPIO3[14]
I,GPIO3[15],
Audio input0 Word Select For
PD
ADC, share with
GPIO3[15]
I2S0_SDI
EMAC_COL
EMAC_CRS
EMAC_RXD0
EMAC_RXD1
EMAC_RXD2
C2
C19
D19
C20
D20
C21
Vimicro Copyright© 1999-2014
B,PD
B,PD
B,PD
B,PD
B,PD
B,PU
8mA
8mA
8mA
8mA
8mA
8mA
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
I,GPIO3[16],
Audio input0 Serial Data Input
PD
From ADC, share with GPIO3[16]
I,GPIO1[0],P
Collision detected, share with
D
GPIO1[0]
I,GPIO1[1],P
Carrier sensor, share with
D
GPIO1[1]
I,GPIO1[2],P
Receive data bit0, share with
D
GPIO1[2]
I,GPIO1[3],P
Receive data bit1, share with
D
GPIO1[3]
I,GPIO1[4],P
Receive data bit2, share with
U
GPIO1[4]
Page 24
of 32
www.vimicro.com
EMAC_RXD3
EMAC_RXER
EMAC_RXDV
EMAC_TXD0
EMAC_TXD1
EMAC_TXD2
EMAC_TXD3
EMAC_TXER
EMAC_TXEN
EMAC_MDIO
EMAC_MDC
EMAC_RCK
EMAC_TCK
UHOST_RRE
D21
E20
H17
E21
H18
J17
J18
K17
K18
L17
L18
M17
M18
M4
B,PU
B,PD
B,PD
B,PD
B,PD
B,PU
B,PU
B,PU
B,PD
B,PU
B,PU
B,PD
B,PD
AIO
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VDD_IO_SYS
VC0738 Brief Data Sheet
I,GPIO1[5],P
Receive data bit3, share with
U
GPIO1[5]
I,GPIO1[6],P
Receive error, share with
D
GPIO1[6]
I,GPIO1[7],P
Receive data valid, share with
D
GPIO1[7]
I,GPIO1[8],P
Transmit data bit0, share with
D
GPIO1[8]
I,GPIO1[9],P
Transmit data bit1, share with
D
GPIO1[9]
I,GPIO1[10],
Transmit data bit2, share with
PU
GPIO1[10]
I,GPIO1[11],
Transmit data bit3, share with
PU
GPIO1[11]
I,GPIO1[12],
Transmit error, share with
PU
GPIO1[12]
I,GPIO1[13],
Transmit enable, share with
PD
GPIO1[13]
I,GPIO1[14],
Management data I/O, share with
PU
GPIO1[14]
I,GPIO1[15],
Management Clock, share with
PU
GPIO1[15]
I,GPIO1[16],
Receive Clock, share with
PD
GPIO1[16]
I,GPIO1[17],
Transmit Clock, share with
PD
GPIO1[17]
USB HOST
External Resistor
For Current Reference (43.2Ohm,
FEXT
+- 1%)
UHOST_DP
G1
AIO
USB HOST
D+ Port
UHOST_DM
G2
AIO
USB HOST
D- Port
UOTG_RREF
L3
AIO
USB OTG
External Resistor
For Current Reference (43.2Ohm,
EXT
+- 1%)
UOTG_DP
F1
AIO
USB OTG
D+ Port
UOTG_DM
F2
AIO
USB OTG
D- Port
UOTG_ID
G3
AIO
USB Mini-Receptacle Identifier
UOTG_VBUS
F3
AIO
USB 5-V Power Supply Pin
ETH_TXP
H2
AIO
Transmit D+ Port, TXP
ETH_TXN
H1
AIO
Transmit D- Port, TXN
ETH_RXP
J2
AIO
Receive D+ Port, RXP
ETH_RXN
J1
AIO
Receive D- Port, RXN
Vimicro Copyright© 1999-2014
Page 25
of 32
www.vimicro.com
ETH_RTX
P3
VC0738 Brief Data Sheet
AIO
External 6K-Ohm 1% resistor to
ground, RTX
P6
AO
SATA Port0 External Resistor
N1
AI
SATA Port0 Data Input+
M2
AI
SATA Port0 Data Input-
SATA_TX0_P
L1
AO
SATA Port0 Data Output+
SATA_TX0_
L2
AO
SATA Port0 Data Output-
P1
AI
SATA Port1 Data Input+
P2
AI
SATA Port1 Data Input-
SATA_TX1_P
T1
AO
SATA Port1 Data Output+
SATA_TX1_
R2
AO
SATA Port1 Data Output-
SATA_SRES
REF
SATA_RX0_
P
SATA_RX0_
M
M
SATA_RX1_
P
SATA_RX1_
M
M
DDR_CSN
AC3
O
VDDQ_DDR
O,DDR_CS
DDR SDRAM Chip Select
N
DDR_A[0]
AB1
O
VDDQ_DDR
O,DDR_A[0]
DDR SDRAM Memory Address 0
DDR_A[1]
V23
O
VDDQ_DDR
O,DDR_A[1]
DDR SDRAM Memory Address 1
DDR_A[2]
W1
O
VDDQ_DDR
O,DDR_A[2]
DDR SDRAM Memory Address 2
DDR_A[3]
AB2
O
VDDQ_DDR
O,DDR_A[3]
DDR SDRAM Memory Address 3
DDR_A[4]
Y22
O
VDDQ_DDR
O,DDR_A[4]
DDR SDRAM Memory Address 4
DDR_A[5]
AA2
O
VDDQ_DDR
O,DDR_A[5]
DDR SDRAM Memory Address 5
DDR_A[6]
Y23
O
VDDQ_DDR
O,DDR_A[6]
DDR SDRAM Memory Address 6
DDR_A[7]
AA1
O
VDDQ_DDR
O,DDR_A[7]
DDR SDRAM Memory Address 7
DDR_A[8]
W22
O
VDDQ_DDR
O,DDR_A[8]
DDR SDRAM Memory Address 8
DDR_A[9]
Y1
O
VDDQ_DDR
O,DDR_A[9]
DDR SDRAM Memory Address 9
DDR_A[10]
AB23
O
VDDQ_DDR
O,DDR_A[1
DDR SDRAM Memory Address 10
0]
DDR_A[11]
W23
O
VDDQ_DDR
O,DDR_A[1
DDR SDRAM Memory Address 11
1]
DDR_A[12]
AA23
O
VDDQ_DDR
O,DDR_A[1
DDR SDRAM Memory Address 12
2]
DDR_A[13]
W2
O
VDDQ_DDR
O,DDR_A[1
DDR SDRAM Memory Address 13
3]
DDR_A[14]
V22
O
VDDQ_DDR
O,DDR_A[1
DDR SDRAM Memory Address 14
4]
DDR_CLK_IN
AB22
V
Vimicro Copyright© 1999-2014
O
VDDQ_DDR
O,DDR_CLK
DDR SDRAM Clock Inverse,
_INV
DDR_CLK_N
Page 26
of 32
www.vimicro.com
VC0738 Brief Data Sheet
DDR_CLK
AC22
O
VDDQ_DDR
O,DDR_CLK
DDR SDRAM Clock, DDR_CLK_P
DDR_CKE
AA21
O
VDDQ_DDR
O,DDR_CK
DDR SDRAM Clock Enable
E
DDR_CASN
DDR_RASN
AA4
AC5
O
O
VDDQ_DDR
VDDQ_DDR
O,DDR_CA
DDR SDRAM Column Address
SN
Select
O,DDR_RA
DDR SDRAM Row Address Select
SN
DDR_WEN
AC4
O
VDDQ_DDR
O,DDR_WE
DDR SDRAM Write Enable
N
DDR_DQM[0]
DDR_DQM[1]
DDR_DQM[2]
DDR_DQM[3]
DDR_BA[0]
AB18
AB8
Y16
Y10
AC2
O
O
O
O
O
VDDQ_DDR
VDDQ_DDR
VDDQ_DDR
VDDQ_DDR
VDDQ_DDR
O,DDR_DQ
DDR SDRAM Data Read/Write
M[0]
Mask 0 , DDR_DM[0]
O,DDR_DQ
DDR SDRAM Data Read/Write
M[1]
Mask 1 , DDR_DM[1]
O,DDR_DQ
DDR SDRAM Data Read/Write
M[2]
Mask 2 ,DDR_DM[2]
O,DDR_DQ
DDR SDRAM Data Read/Write
M[3]
Mask 3 , DDR_DM[3]
O,DDR_BA[
DDR SDRAM Bank Access 0
0]
DDR_BA[1]
AA22
O
VDDQ_DDR
O,DDR_BA[
DDR SDRAM Bank Access 1
1]
DDR_BA[2]
AB3
O
VDDQ_DDR
O,DDR_BA[
DDR SDRAM Bank Access 2
2]
DDR_DQ[0]
AC7
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 0
0]
DDR_DQ[1]
AB5
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 1
1]
DDR_DQ[2]
AC8
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 2
2]
DDR_DQ[3]
AB6
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 3
3]
DDR_DQ[4]
AC19
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 4
4]
DDR_DQ[5]
AB21
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 5
5]
DDR_DQ[6]
AC20
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 6
6]
DDR_DQ[7]
AB20
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 7
7]
DDR_DQ[8]
AC16
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 8
8]
DDR_DQ[9]
AC11
Vimicro Copyright© 1999-2014
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 9
Page 27
of 32
www.vimicro.com
VC0738 Brief Data Sheet
9]
DDR_DQ[10]
AC17
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 10
10]
DDR_DQ[11]
AC10
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 11
11]
DDR_DQ[12]
AB15
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 12
12]
DDR_DQ[13]
AB9
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 13
13]
DDR_DQ[14]
AB17
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 14
14]
DDR_DQ[15]
AB11
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 15
15]
DDR_DQ[16]
AA9
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 16
16]
DDR_DQ[17]
AA17
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 17
17]
DDR_DQ[18]
Y9
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 18
18]
DDR_DQ[19]
AA18
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 19
19]
DDR_DQ[20]
AA8
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 20
20]
DDR_DQ[21]
Y18
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 21
21]
DDR_DQ[22]
Y8
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 22
22]
DDR_DQ[23]
Y17
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 23
23]
DDR_DQ[24]
AA15
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 24
24]
DDR_DQ[25]
AA12
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 25
25]
DDR_DQ[26]
AA10
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 26
26]
DDR_DQ[27]
AA16
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 27
27]
DDR_DQ[28]
AA11
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 28
28]
DDR_DQ[29]
Y11
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 29
29]
DDR_DQ[30]
Y15
Vimicro Copyright© 1999-2014
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 30
Page 28
of 32
www.vimicro.com
VC0738 Brief Data Sheet
30]
DDR_DQ[31]
Y14
B
VDDQ_DDR
B,DDR_DQ[
DDR SDRAM Data 31
31]
DDR_DQS[0]
DDR_DQS[1]
DDR_DQS[2]
DDR_DQS[3]
DDR_DQS_I
AB12
AC14
Y12
Y13
AC13
B
VDDQ_DDR
B
VDDQ_DDR
B
VDDQ_DDR
B
VDDQ_DDR
B
VDDQ_DDR
NV[0]
DDR_DQS_I
AB14
B
VDDQ_DDR
NV[1]
DDR_DQS_I
AA13
B
VDDQ_DDR
NV[2]
DDR_DQS_I
AA14
B
VDDQ_DDR
NV[3]
DDR_RSTN
DDR_ODT
Y2
AB4
O
VDDQ_DDR
O
VDDQ_DDR
B,DDR_DQ
DDR SDRAM Data Strobe byte 0 ,
S[0]
DDR_DQS0_P
B,DDR_DQ
DDR SDRAM Data Strobe byte 1 ,
S[1]
DDR_DQS1_P
B,DDR_DQ
DDR SDRAM Data Strobe byte 2 ,
S[2]
DDR_DQS2_P
B,DDR_DQ
DDR SDRAM Data Strobe byte 3 ,
S[3]
DDR_DQS3_P
B,DDR_DQ
DDR SDRAM Data Strobe Inverse
S_INV[0]
byte 0 , DDR_DQS0_N
B,DDR_DQ
DDR SDRAM Data Strobe Inverse
S_INV[1]
byte 1 , DDR_DQS1_N
B,DDR_DQ
DDR SDRAM Data Strobe Inverse
S_INV[2]
byte 2 , DDR_DQS2_N
B,DDR_DQ
DDR SDRAM Data Strobe Inverse
S_INV[3]
byte 3 , DDR_DQS3_N
O,DDR_RS
DDR SDRAM Reset Signal, only
TN
for DDR3
O,DDR_OD
DDR SDRAM On Die Termination,
T
only for DDR2
DDR_ZQ
Y19
B
VDDQ_DDR
B,DDR_ZQ
DDR SDRAM ZQ
DDR_DLL_D
V17
O
VDDQ_DDR
O,DDR_DLL
DDR DLL Digital Test Output 0, for
_DTO[0]
Test
O,DDR_DLL
DDR DLL Digital Test Output 1, for
_DTO[1]
Test
B,DDR_DLL
DDR DLL Analog Test Output, for
_ATO
Test
I,GPIO1[18],
VGA0 HSYNC, share with
PD
GPIO1[18]
I,GPIO1[19],
VGA0 VSYNC, share with
PD
GPIO1[19]
TO[0]
DDR_DLL_D
V18
O
VDDQ_DDR
TO[1]
DDR_DLL_A
AA19
B
VDDQ_DDR
TO
VGA0_HSYN
L20
B,PD
8mA
C
VGA0_VSYN
M21
B,PD
C
VDAC0_OUT
8mA
R23
AO
VDAC0 OUT0 +
P23
AO
VDAC0 OUT1 +
P22
AO
VDAC0 OUT2 +
T20
AIO
VDAC0
P0
VDAC0_OUT
P1
VDAC0_OUT
P2
VDAC0_REX
Reference External
T
Vimicro Copyright© 1999-2014
Page 29
of 32
www.vimicro.com
VDAC0_VDR
R22
AIO
M20
B,PD
VC0738 Brief Data Sheet
VDAC0
VD Reference
EF
VGA1_HSYN
8mA
C
VGA1_VSYN
L21
B,PD
8mA
C
I,GPIO1[20],
VGA1 HSYNC, share with
PD
GPIO1[20]
I,GPIO1[21],
VGA1 VSYNC, share with
PD
GPIO1[21]
T23
AO
VDAC1 OUT0 +
U23
AO
VDAC1 OUT1 +
U22
AO
VDAC1 OUT2 +
T21
AIO
VDAC1
Reference External
T22
AIO
VDAC0
VD Reference
HDMI_TX2P
B18
AO
Channel 2 TX+
HDMI_TX2N
A18
AO
Channel 2 TX-
HDMI_TX1P
B19
AO
Channel 1 TX+
HDMI_TX1N
A19
AO
Channel 1 TX-
HDMI_TX0P
B20
AO
Channel 0 TX+
HDMI_TX0N
A20
AO
Channel 0 TX-
HDMI_TXCP
B21
AO
TX Clock+
HDMI_TXCN
A21
AO
TX Clock-
HDMI_RBIAS
A15
AI
12KOhm risistor to Ground，+/-1%
HDMI_CEC
C15
B,PD
VDAC1_OUT
P0
VDAC1_OUT
P1
VDAC1_OUT
P2
VDAC1_REX
T
VDAC1_VDR
EF
HDMI_DSCL
HDMI_DSDA
HDMI_HPD
C16
C17
C18
B,PU
B,PU
B,PD
8mA
8mA
8mA
8mA
VDD_IO_HDM
I,GPIO1[22],
Custom Electronics Control Wire,
I
PD
share with GPIO1[22]
VDD_IO_HDM
I,GPIO1[23],
I2C Master Clock, share with
I
PU
GPIO1[23]
VDD_IO_HDM
I,GPIO1[24],
I2C Master Data, share with
I
PU
GPIO1[24]
VDD_IO_HDM
I,GPIO1[25],
Hot Plug Detect, share with
I
PD
GPIO1[25]
VDDA_PLL0
K23
PWR
1.0v
PLL0 Analog Power,1.0V
VDDA_PLL1
K22
PWR
1.0v
PLL1 Analog Power,1.0V
VDDA_PLL2
L23
PWR
1.0v
PLL2 Analog Power,1.0V
VDDA_PLL3
L22
PWR
1.0v
PLL3 Analog Power,1.0V
VDDA_PLL4
N21
PWR
1.0v
PLL4 Analog Power,1.0V
VSSA_PLL0
K21
GND
0v
PLL0 Analog Ground
VSSA_PLL1
M22
GND
0v
PLL1 Analog Ground
VSSA_PLL2
M23
GND
0v
PLL2 Analog Ground
Vimicro Copyright© 1999-2014
Page 30
of 32
www.vimicro.com
VC0738 Brief Data Sheet
VSSA_PLL3
N23
GND
0v
PLL3 Analog Ground
VSSA_PLL4
N22
GND
0v
PLL4 Analog Ground
UHOST_VDD
K4
PWR
3.3v
USB HOST PHY
3.3v
A33
UHOST_
M6
GND
0v
N3
GND
0v
L6
PWR
3.3v
K3
GND
0v
M3
GND
0v
USB OTG PHY
Analog Power
USB OTG PHY
Analog Ground
USB OTG PHY
PLL Analog
Ground
C
VDD33_EPH
PLL Analog
3.3v , UOTG_VSSA33
VSSA33
UOTG_VSSA
USB HOST PHY
3.3v
VDDA33
UOTG_
Analog
Ground
AC
UOTG_
USB HOST PHY
Ground , UHOST_VSSA
VSSA33
UHOST_VSS
Analog Power
K1, K2
PWR
3.3v
ETHERNET PHY Analog Power
supply:3.3v
Y
VSS_EPHY
N4, P4
GND
0v
ETHERNET PHY Analog Ground
SPHY_VP25
T3，T4，R3，R4
GND
2.5v
SATA PHY Analog Power high
voltage supply:2.5v, SATA_VP25
VDAC0_PVD
R20
PWR
3.3v
VDAC0 Analog Power,3.3v
R21
PWR
3.3v
VDAC0 Analog Power,3.3v
P20,P21
GND
0v
VDAC0 Analog Ground
U20,V20,V21
PWR
3.3v
VDAC1 Analog Power,3.3v
U21
PWR
3.3v
VDAC1 Analog Power,3.3v
W20,W21
GND
0v
VDAC1 Analog Ground
A17,B17
PWR
3.3v
HDMI ESD Analog Power 3.3v
A16,B16
GND
0v
HDMI ESD Analog Gound
A14
PWR
3.3v
HDMI Analog Power 3.3v
B15
GND
0v
HDMI Analog Gound
C14,D14
GND
0v
DVSS,ESD Ground
N10-N15, N17,
PWR
1.0v
Core power,1.0v
D1
VDAC0_PVD
D2
VDAC0_PGN
D1
VDAC1_PVD
D1
VDAC1_PVD
D2
VDAC1_PGN
D1
AVDD33_ES
D
AVSS33_ES
D
AVDD33_HD
MI
AVSS33_HD
MI
HDMI_VSS3I
O
VDD_CORE
Vimicro Copyright© 1999-2014
Page 31
of 32
www.vimicro.com
VC0738 Brief Data Sheet
P10-P15,
P17-P18,
R10-R15,
R17-R18,
T17-T18,
U10-U18
VDD_IO_SYS
PWR
3.3v
System Digital I/O power,3.3v
B8-B9, C8-C9
PWR
1.8v,3.3v
DCVI Digital I/O power
D15
PWR
5.0v
HDMI Digital I/O power
D16,D17,F7,F8,
PWR
2.8v,3.3v
LCD Digital I/O power
PWR
1.5v
DRAM Power,1.5v
V11-V13,
PWR
2.5v
DDR PLL Power,2.5v
V14-V16
GND
0v
DDR PLL Ground
Y21
PWR
1/2
DRAM REF Power , DDR_VREF
A22, J6-J7, H7,
K6, H22-23,
K20,
VDD_IO_DCV
I
VDD_IO_HD
MI
VDD_IO_LCD
G7,G8,F14,G14
VDD_IO_DD
U1-U4, U6-U7,
R
V1-V4,
V6-V8, W3-W4,
Y3-Y5, AA3,
AA5
DDR_PLL_V
DD
DDR_PLL_V
SS
VREF_DDR
VDDQ_DDR
VSS
A1,AC1,A23,AC
GND
0v
System Digital I/O ground
23,B14,D18,G22
,K7,K9-15,L7,L4
,L9-L15,M1,M7,
M9-15,N6-N7,N
2,N9,P7,P9,R1,
R6-7,R9,T2,T6-7
,U8-9,V9-10,Y67,AA6-7,AB7,A
C6,AC9,AB10,A
C12,AB13,AC15
,AB16,AC18,AB
19,Y20,AA20,A
C21,N18,N20,G
22,D18,B14
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