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VC0882 Data Book
VC0882
Data Book
Revision 0.92
Notes1: The information is subject to change without notice. Before using this
document, please confirm that this is the latest version.
Notes2: Not all products and/or types are available in every country. Please
check with a Vimicro sales representative availability and additional
information.
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Important Notice
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modifications, enhancements, improvements, and other changes to its products and
services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and
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Revision Table
Date
Rev.
2011-1-20
0.10
2011-4-01
0.21
2011-5-01
0.90
Author
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VC0882 Data Book
Content of revision
Original version
Modify version
Release Version
Approval
IC team
Yanghui
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CONTENTS
1 OVERVIEW ...........................................................................8
2 FEATURE DESCRIPTION ..................................................10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
System Block Diagram........................................................................... 10
Highlight Feature .................................................................................... 11
CPU Subsystem ..................................................................................... 11
Memory Subsystem ............................................................................... 13
Video Subsystem ................................................................................... 14
Storage Subsystem ................................................................................ 18
Peripheral Subsystem ............................................................................ 19
Power Management ............................................................................... 21
PAD and PAD Control ............................................................................ 22
3 PIN DESCRIPTION AND PACKAGE INFO ........................24
3.1
3.2
3.3
Ball Map ................................................................................................. 24
Pin description ....................................................................................... 28
Package Information .............................................................................. 52
4 CPU SUBSYSTEM ..............................................................57
4.1
4.2
4.3
4.4
4.5
CORTEX-A8 Features ........................................................................... 57
Clock and Reset .................................................................................... 59
Interrupt controller .................................................................................. 60
Timer ...................................................................................................... 61
EFUSE ................................................................................................... 62
5 MEMORY SUBSYTEM ........................................................65
5.1
5.2
5.3
5.4
5.5
Interconnection ...................................................................................... 65
DDR Controller ...................................................................................... 66
Sram Controller ...................................................................................... 67
Rom Controller ....................................................................................... 68
DMAC (Direct Memory Access Controller) ............................................. 68
6 VIDEO SUBSYSTEM ..........................................................71
6.1
Video Encoder ....................................................................................... 71
Supported standards and tools................................................................... 71
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6.2
6.3
6.4
6.5
6.6
6.7
6.8
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Encoding Features ..................................................................................... 72
Pre-processing features ............................................................................. 73
Video stabilization features......................................................................... 74
Connectivity features .................................................................................. 74
Video Decoder ....................................................................................... 75
Video standard and profiles ........................................................................ 75
Decoder features ........................................................................................ 77
Post-processing features ............................................................................ 79
Connectivity features .................................................................................. 82
Camera Interface ................................................................................... 83
Face Detection ....................................................................................... 84
LCD interface ......................................................................................... 86
TV Encoder ............................................................................................ 87
Display Engine ....................................................................................... 88
GPU ....................................................................................................... 91
General Features ....................................................................................... 91
Full-featured 3D Graphics Pipeline............................................................. 91
Full-featured 2D Graphic Pipeline .............................................................. 92
7 STORAGE SUBSYSTEM....................................................95
7.1
7.2
7.3
7.4
7.5
USB OTG............................................................................................... 95
USB HOST ............................................................................................ 96
SDIO Controller ..................................................................................... 97
NAND Flash Controller .......................................................................... 97
SPI (Serial Peripheral Interface) ............................................................ 99
8 PERIPHERAL SUBSYSTEM ............................................102
8.1
8.2
8.3
8.4
8.5
8.6
Audio Module ....................................................................................... 102
UART ................................................................................................... 103
IIC Module ........................................................................................... 104
PWM .................................................................................................... 105
KeyPad ................................................................................................ 105
Touch Panel Interface .......................................................................... 106
9 ELECTRICAL PARAMETERS AND TIMING ....................109
9.1
9.2
9.3
Absolute Maximum Ratings ................................................................. 109
Recommended Operating Conditions ................................................... 110
DC Characteristics ................................................................................ 112
Analog IO .................................................................................................. 112
Standard Digital IO .................................................................................... 112
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MEMORY IO ............................................................................................. 114
USB Analog IO .......................................................................................... 115
9.4
CIF Interface Timing ............................................................................. 116
9.5
SPI Interface Timing ............................................................................. 117
SPI in Slave Mode ..................................................................................... 117
SPI in Master Mode ................................................................................... 118
9.6
I2C Interface Timing .............................................................................. 119
9.7
SDIO Interface Timing.......................................................................... 121
9.8
NFC Interface Timing ........................................................................... 123
9.9
AUD Interface Timing ........................................................................... 126
9.10 LCD Interface Timing ........................................................................... 127
LCD Serial Interface ................................................................................. 127
Data Output for DPI Panel ........................................................................ 128
Interface Timing with DBI Panel ............................................................... 129
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Chapter 01
Overview
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1 Overview
The Vimicro VC0882, is a high performance, low power, multimedia application and
high integrated system-on-chip (SOC) targeted at Application Processor (AP) of
Tablet PC and Smart Phone. It is implemented on TSMC 65nm low power process
technology.
The embedded microprocessor in VC0882 is based on 1.3Ghz ARM Cortex-A8 with
NEON coprocessor. Also it is integrated with the high performance video decoder up
to 1080P with 30fps for H.264, H.263, RMVB, MPEG4, MPEG2,VC1 etc. And it can
support H.264, MPEG4, H.263 video encoder up to 30fps for 720p.
VC0882 is embedded for 2D and 3D graphic acceleration processor (GPU) to support
display and gaming. This GPU delivers the scalable ultra-threaded unified shader
architecture up to 15MTriangle rate per second. Also it supports the industry standard
API such as Open GL ES1.1 and 2.0, Open VG1.0
Camera interface supports multiple formats from parallel sensors, ccir656 interface
and raw image data. Display engine can deal with overlay of 4 display layers plus
background and HW cursors. The video subsystem also supports SDTV and HDTV
with 10-bit 3-channel 250Mhz analog Video DAC output. 24 bits LCD interface is
applied with most of post processing and 1920x1080 maximum display sizes for all of
panels and HDMI Bridge. It also supports the face detection function through the
cooperation of hardware and software.
VC0882 can support most of high-level operation systems such as Android OS and
Linux. And it integrates the state-of-the-art power management technologies for
dynamic voltage control with multi power domains.
Integrated DDR controller can be compatible to external LPDDR, DDR2 and DDR3
with the data rates up to 667Mb/s. It supports 6 high performance and low power PLLs
for flexible clock switch. VC0882 includes 3 SDIO/MMC card interfaces and
8bits/16bits NAND Flash with ECC, 2 PWMs, 3 UART interfaces, 2 SPI controller
interfaces. One USB OTG 2.0 and one USB Host 2.0 can implement the data transfer
between SOC and PC. Also, VC0882 contains the embedded 10-bit SAR ADC with
4-wire touch panel interface and carries one high quality 24-bit stereo ADC and DAC
for audio processing. It can support the EFUSE function to program electrical fuse IP.
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Chapter 02
Feature
Description
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2 Feature Description
2.1 System Block Diagram
Figure 2-1 System Diagram of 445BGA
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2.2 Highlight Feature
- Embedded up to 1.3Ghz ARM CORTEX-A8 CPU with v7-A instruction set
- Embedded up to 720p H.264, MPEG-4, H-263 video encoder with 30fps
- Embedded up to 1080p H.264, SVC, MPEG-4, MPEG-2, MPEG-1, H.263,
VC-1, JPEG, RV, VP6 and DivX video decoder with 30fps
- Embedded with graphic 3D engine for compliant with the OpenGL ES 2.0;
OpenGL ES1.1; OpenVG 1.1
- Embedded with Data rates of up to 667 Mb/s (333 MHz) for LPDDR, DDR2
and DDR3
- Embedded 6 PLLs for flexible clock switch
- Support parallel cameral sensor interface with max 4Kx4K resolution
- Support LCD interface for DBI, DPI and HDMI bridge
- Support NTSC and PAL SDTV and YPbPr analog signals output on 480i /480p
/576i /576p /720p /1080i /1080p systems
- Embedded 8 bit/16 bit NAND Flash controller with up to 48 bits ECC
- Supports 4 SDIO devices
- One USB host and one USB OTG compliant with USB2.0 specification
- Contains a high-quality 24-bit audio stereo ADC and a high-quality 24-bit
stereo DAC
- Support Touch Panel Interface with10-bit SAR ADC: DNL - 1 LSB, INL 2 LSB
- Embedded with multi-power domains and smart DVFS scheme
- Power consumption value: 108mW for audio playing, 183mW for screen
display, 630mW for 1080P player and 800uW for sleep mode
2.3 CPU Subsystem
Embedded ARM CORTEX-A8
-
Full implementation of the ARM architecture v7-A instruction set
64-bit high-speed Advanced Microprocessor Bus
Programmable CPU frequency up to 1.3Ghz for typical case
memory interface supporting multiple outstanding transactions
A pipeline for executing ARM integer instructions
A NEON pipeline for executing Advanced SIMD and VFP instruction sets
Dynamic branch prediction with branch target address cache, global history
buffer, and 8-entry return stack
- Memory Management Unit (MMU) and separate instruction and data
Translation
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Look-aside Buffers (TLBs) of 32 entries each
Level 1 32KB instruction cache and 32KB data caches
Level 2 128KB cache
Level 2 cache with parity and Error Correction Code (ECC) configuration
option
Embedded Trace Macrocell (ETM) support for non-invasive debug
Static and dynamic power management including Intelligent Energy
Management (IEM)
ARMv7 debug with watch point and breakpoint registers and a 32-bit
Advanced
Peripheral Bus (APB) slave interface to a CoreSight debug system.
Interrupt Controller
- Hierarchical interrupt scheme which process 1st level interrupts in Interrupt
Controller while handling 2nd level interrupt in the associated sub-modules
- Support both FIQ and IRQ
- Support up to 32 interrupts
- Using interrupt source based MASK scheme and source pending registers to
avoid losing interrupts
- Programmable interrupt prioritization
Timers
-
3 general purpose timers, 4 dual timers and 1 watchdog timer
Programmable timer period and timer operation mode
Individual interrupt for each timer
Unique 24MHz clock for all timer
CLOCK & RST
-
Supports 1 oscillator (or crystal): 26 MHz XCLK
Embeds 6 high performance, low power PLLs
Includes configurable clock dividers to produce desired clock frequencies
Implements clock gating technology to save power
Inserts clock multiplexers to enhance flexibility
Seamlessly dynamic clock switching between XCLK and all 6 PLLs
Integrates pmu hardware reset, watchdog reset, global software reset and
each module’s individual software reset
- Inserts clock multiplexers to enhance flexibility
EFUSE
- Support to manage the electrical fuse IP by APB bus in normal mode or by
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PAD on ATE test mode
Embedded power switch
Support to program to 1 bit at a time according to the configured address
Software can read 1-8 bytes at a time according to configured address and
configured read byte length
Provide power down and standby mode
Asynchronous signal interface
2.4 Memory Subsystem
DDR controller
-
Compatible with JEDEC standard LPDDR, DDR2, DDR3
Data rates of up to 667 Mb/s (333 MHz)
Compatible with the AMBA 3 AXI protocol
Compatible with the AMBA 3 APB protocol
Supported AXI burst type: incremental and wrap
Register programmable timing parameters support DDR2/DDR3/LPDDR1
components from DRAM various vendors
Support LPDDR1/DDR2 read/write command interrupt access
Advanced features such ODT, ZQ Calibration and additive latency
Support for two CSs (chip select) with shared clock pins, command pins,
address pins and data pins
Support for DDR device density ranging from 64Mbit to 2Gbit
Support 16bit/32bit LPDDR1/DDR2/DDR3 device
Supports autonomous DDR power down entry and exit based on
programmable idle periods
Support for self refresh entry on software command and automatic exit on
DRAM access command arrival
Automated Read DQS recognition and Automated Dynamic DQS Drift
Compensation
Built-in DQS Gate Training
Support DDR3 DLL-off Mode
Support LPDDR1 Deep Power Down Mode
DMA Controller
- Compliance to the AMBA 3.0 Specification---AXI protocol for integration into
SoC implementation.
- One DMA channel which can support unidirectional transfer for software
request
- Support memory-to-memory transfers
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- Support Software link list descriptor-based DMA transfers
- Support programming max burst length
SRAM Controller
- Embedded 32Kbyte SRAM in chip
- Supports 14 bit address and 16 bit data
Acts as single-port SRAM for test program and as dual-port SRAM
ROM Controller
- Embedded with 64Kbyte ROM
- Supports with 14 bit address and 64 bit data
- For system boot only
2.5 Video Subsystem
Camera Interface
-
-
Support master type sensor module and 8-bit parallel data output from sensor
Support two camera sensors (only one works at the same time)
Support max sensor resolution: 4096x4096 and 100Mhz max pixel clock
Support max output image size (to memory): 4096x4096
Support parallel interface for SYNC mode or ITU-R BT656 mode
Support YCbCr422-format data/RAW image data/JPEG compressed
data/RGB data (Bypass post-processing for RAW data/JPEG data/RGB
data)
Support two post-processing paths for capture and display
Support up-scaling and down-scaling for capture path/preview path
Capture path support slice mode and frame mode
Support auto-focus
Special Effect
o Mono color
o Sepia
o Special color
o Negative
o Four blocks
o Grid color
Display Engine
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-
Support 4 display layers plus background and HW cursor
Support HW cursor with max resolution 64x64
Using Pipeline architecture to implement overlay & alpha-blending operation
Support up-scaling for overlay pixel data up to 1920x1080
Support brightness/contrast/hue/saturation adjustment
Support programmable gamma correction
Support dithering for less than 24-bit color display
Provide capture path to implement the function as “capture with frame”
Max panel resolution: 1600x1200 for TV/1920x1080 for LCD panel and Max
pixel rate up to 162MHz
- Support BT601 and BT609 color domain
- Programmable bits-per-pixel when output to LCDIF module: 16/18/24-bpp
such as YUV422, RGB565, RGB666, RGB888, and etc.
- Support programmable multi-cycle output mode: 1/2/3/4 cycles per pixel
Face Detection
- Includes the calculation of integral and LAB (Locally Assembled Binary) in
hardware and some functions implemented by software
- Support maximum sizer image width is 320 pixels, height is 240 pixels,
minimum sizer image width is 24 pixels, height is 24 pixels and no limitation
for original image size
- About process 5~10 QVGA frames in a second
- Support detection of smile faces, but not wink faces and report the eyes
position.
- Support the face in profile angle is -20 ~ 20 degrees, pitching angle is -30 ~ 30
degrees.
- Support detection of black skin faces, color eyes and white hair
Video Encoder
- Supports H.264 baseline Levels 1-3.1, I-Slice and P-Slice CAVLC encoding,
contained intra prediction, image size up to 1280x1024
- Supports MPEG-4 Levels 1-5, I-VOP and P-VOP, Max MV range +-16 pixels,
image size up to 1280x1024
- Supports H.263 Profile 0 Level 10-70
- Supports JPEG baseline image size up to 4672x3504
- Supports cropping and rotation (90 or 270 degrees) functions
Video Decoder
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- Supports to decode H.264, SVC, MPEG-4, MPEG-2, MPEG-1, H.263, VC-1,
JPEG, RV, VP6 and DivX profile and level for up to 1920x1080
- Supports most of post-processing, up-scaling, down-scaling, dithering,
alpha-blending, color conversion, de-interlacing.
- Also supports contrast, brightness, saturation, cropping, digital zoom, picture
in picture, image rotation etc.
3D Graphic Engine
- OpenGL ES 2.0 compliant, including extensions; OpenGL ES1.1; OpenVG 1.1
- IEEE 32-bit floating-point pipeline supports long shader instructions (maximum
256 instruction)
- Up to 256 threads per shader
- Up to 16 programmable Scalable Ultra-threaded, unified vertex and pixel
shaders
- FSAA mechanisms: MSAA 4x, high quality FSAA 16x
- Vertex processing supported format: BYTE, UBYTE, SHORT, USHORT, INT,
UINT, DEC, UDEC, FLOAT,FLOAT16,D3DCOLOR, FIXED16DOT16
- Up to 8 programmable elements per vertex
- Dependent texture operation with high-performance
- Alpha blending
- Support for 4 vertex shader and 8 pixel shader simultaneous textures
2D Graphic Engine
-
Bit blit, stretch blit, pattern blit and fast clear
Line drawing and Rectangle fill and clear
Mono expansion for text rendering
Anti-aliased font support
ROP2, ROP3, ROP4
Alpha blending
90/180/270 degree rotation and Vertical and Horizontal mirror
Transparency by monochrome mask, chroma key or pattern mask
High quality 9-tap filter for scaling
32K x 32K coordinate system
Color space conversion between YUV and RGB for both BT709 and BT601
Clipping window
Color Index Input conversion Support
Filter Blit
Input Formats: (Only Filter Blit support YUV input)
A1R5G5B5
A4R4G4B4
A8R8G8B8
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X1R5G5B5
X4R4G4B4
X8R8G8B8
RGB565
NV12 (semi-planer YUV420)
NV16 (semi-planer YUV422)
YUY2(package YUV422)
UYVY(package YUV422)
YV12(planer YUV420)
8-bit color index
1-bit monochrome
- The output data Formats:
A1R5G5B5
A4R4G4B4
A8R8G8B8
X1R5G5B5
X4R4G4B4
X8R8G8B8
RGB565
LCD Interface
- Supports Display Bus Interface (DBI) output mode, compliant to the MIPI
Alliance Display Bus Interface protocol v2.0
- Supports accessing (including writing and reading) in through mode
- Supports dual LCD panels work at different time(DBI & DBI, DBI&DPI)
- Supports up to 24 bits per pixel (BPP)
- Display size programmable up to 1080p(1920*1080) with configured interlaced
or progressed mode
- Supports Display Pixel Interface (DPI) output mode, compliant to the MIPI
Alliance Display Pixel Interface protocol V2.0
- Display size programmable up to 1080p(1920 x1080) with configured
interlaced or progressed mode;
- Support for 12 & 16&18BPP&24BPP modes for RGB parallel output format
(RGB444 , RGB565, RGB666,RGB888);
- Support programmable pixel clock and asynchronous reset signal ;
- Support flexible 3-wire and 4-wire serial interface(including write operation
and read operation of panel registers)
- Support parallel dpi interface with up to 24 bits interface;
- Support CCIR656 interface (PAL mode and NTSC mode, 8 bit interface only);
- Support CCIR601 interface.
- Support UPS051&UPS052 interface (8 bit interface only).
- Support 24BPP modes for UPS051&UPS052 interface.
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- Support 16BPP modes for CCIR656 and 24BPP modes for CCIR601.
- Programmable 24-bit/18-bit/16-bit/12-bit/8-bit digital output interface
- Supports various RGB format (RGB888, RGB565, RGB666, RGB555), YUV
format (YUV444, YUV422) with 1X, 2X, 3X, 4X multiplexed output.
- Support Max pixel rate up to 150MHz in DPI mode
TV Encoder
- Support NTSC-M/J/4.43 and PAL- /B/D/G/H/M/N/I/Nc SDTV Composite signal
(480i/576i) output.
- Support YPbPr analog signals output on 480i /480p /576i /576p /720p /1080i
/1080p systems
- Embedded with 10 bits Video DAC for analog signal output
2.6 Storage Subsystem
NAND Flash Controller
- Compliant to open NAND Flash Interface (ONFI) 1.0 Specification
- Hardware BCH (Bose, Chaudhuri & Hocquenghem Type of code) encoder
and decoder are included
- Error detection/correction capability of 4/8/16 bits per 512 bytes
- Error detection/correction capability of 24/32/40/48 bits per 1024 bytes
- 8-bit parallel architecture and calculation based on 1-bit length
- Support SLC, MLC and TLC NAND flash
- Support interlaced storage of ECC and user data
- Support Asynchronous Interface Bus Operation, Clock Frequency 50M for
8-bit interface and Clock Frequency 100M for 16-bit interface
- Support booting from NAND flash with built-in bootloader
SDIO Host
- Supports 3 SD IO devices
- Compatible with SD Memory Card Spec 2.0 and supports SDHC up to 32GB
card
- Compatible with SDIO Card Spec 2.0
- Compatible with JESD84-A43 standard (MMC 4.3), up to 8-bit data bus
- Support for SD Memory, SDIO, SD Combo, miniSD, MMC, MMC plus, MMC
RS and Trans-Flash cards
- Support dual voltage cards typically operating at 1.8V and 3.3V
- Support programmable protocol bus clock for different cards, up to 52MHz
USB Host
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- High-speed single-port USB host controller. Support one USB downstream
port.
- Fully compliant with the USB 2.0 specification, Enhanced Host Controller
Interface (EHCI) Specification, Revision 1.0, and the Open Host Controller
Interface (OHCI) Specification Release 1.0a.
- Supports high-speed, 480-Mbps transfers using an EHCI Host Controller, as
well as full and low speeds through one integrated OHCI Host Controllers.
- The supported peripherals are determined by OS software.
- Also supported: USB-HDD, USB-DVDRW, USB Mouse, USB Keyboard, USB
Modem.
USB OTG
- USB 2.0 high-speed dual-role controller:
- Operates either as the host/peripheral in point-to-point communications with
another USB function or as a function controller for a USB peripheral
- Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and
with the On-The-Go supplement to the USB 2.0 specification
- Supports point-to-point communications with one high-, full- or low-speed
device
2.7 Peripheral Subsystem
PWM
- Supports up to 2 channels
- The pulse ratio of the output waveform ranges from 0/256 to 255/256
The frequency of the output waveform ranges from 6KHz to 12MHz
UART
-
Support 3 UART controllers.
Functional compatible with the 16550A
Full-duplex operation.
Fully programmable serial interface, Data bit: 7-bit or 8-bit, Parity bit: None,
Even, Odd, or Stick check, Stop bit: 1-bit or 2-bit.
Break condition detection and generation.
Programmable integer and fractional divisor for baud rate generation.
Programmable Baud rate computation method support up to 12Mbps baud
rate.
Loop-back mode for self test.
Slow infrared asynchronous interface that conforms to the Infrared Data
Association (IrDA) specification.
Modem control functions with DSR, DCD, RI and DTR signals.
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SPI
-
Support 2 SPI controllers;
Provide master/slave modes selectable by control registers;
Full duplex synchronous serial data transfer;
The max transfer speed in master mode is 54MHz
The max transfer speed in slave mode is 27MHz
I2C
-
Master mode only
Compliant to Philips I2C-Bus Specification v2.1
Supports for standard mode (up to 100Kbps) and fast mode (up top 400Kbps)
Support 7-bit and 10-bit device addressing modes
Max transfer length of each transaction is 65535 for read or write operation
Arbitration lost detection and bus busy detection
Touch Panel Interface
-
Master mode only
Embedded 10-bit SAR ADC: DNL - 1 LSB, INL - 2 LSB
Support control function of resistive 4-wire touch panel
Support pen down detect
Support 4-channel analog input measurement
multi-touch supported in Software including zoom in & out and rotation
Audio Codec
- Master mode only
- Contains a high-quality 24-bit stereo ADC and a high-quality 24-bit stereo DAC
- Provides 6 mono differential line inputs with boost gain stage (0/4/8/12/16/20
dB), they can be used either for line in or microphone in application
- Provides 1 stereo single-end 16/32 Ohm headphone output
- Provides 2 mono differential line output that but can’t be driven simultaneously
- Provides 1 mono differential BTL 16/32 Ohm receiver output
- Provides a stereo differential speaker output and one of them can also be
configured to the mono differential BTL 8 ohm output
- Provides 2 microphone bias output
- Supports audio sampling rates (Fs) from 8KHz to 96KHz (88.2KHz not
supported)
- Supports the Automatic Gain Control (AGC) function to better sound recording
performances
- Provides 2 I2S/PCM Interfaces of master mode through VC0882 PADs, so as
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to connect external devices of slave mode
- Includes two 32-bit stereo digital mixer (produce Y = A + B result)
- Supports 6 memory formats of audio raw data: Stereo-32bit, Stereo-16bit,
Stereo-8bit, Mono-32bit, Mono-16bit, and Mono-8bit
2.8 Power Management
-
-
-
Robust power on/off control and sequence
AP Software is allowed to control variable voltage output of abundant power
supply devices in PMIC via I2C interface.
AP is partitioned into multi power domains to allow power off of inactive domains
and down-scaling of supply voltage when the domain can work with low
frequency.
AP is divided into two Power domains: PMU (always-on domain) & PSO
(shut-off domain). PMU power domain includes PMU logic and all digital IO
domains. These digital IO should be powered on/off with PMU logic power at the
same time, including DDR memory IO. PSO power domain is divided into four
voltage domains to support individual power on/off control, down/up scaling of
voltage level for each voltage domain depending on applications. These four
voltage domains are ARM, GPU, Video Codec, Other Core. Each voltage
domain has its own supply from PMIC with variable voltage output.
AP has the following power modes to support low power design.
Power
modes
PMU
domain
PSO
domain
-
POWER
OFF
Off
NORMAL
IDLE
HALT
SLEEP
On
On
On
On
Off
On
On
with ARM
clock
gating
On
Off
With
all
module
clock
gating
Static and dynamic clock gating to decrease dynamic power consumption in AP
chip.
Seamless clock switch to support low power mode in AP chip.
DVFS(Dynamic Voltage & Frequency Scaling) Technology allows adaptive
down/up scaling of clock frequency and voltage level inside one scenario or
between scenarios to reduce further dynamic power and also leakage power
consumption. Temperature & Process change can also be compensated for by
Vimicro Copyright© 1999-2011
Page 21 of 131
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VC0882 Data Book
hardware.
2.9 PAD and PAD Control
-
Support 1.7v ~ 3.6v normal digital I/O
Support 2.4v ~ 3.6v normal analog I/O and 5v special analog I/O
Support 1.4v ~ 1.9v high-speed MDDR/DDR2/DDR3 I/O
4mA/8mA/12mA/16mA drive strength of I/O
Schmitt trigger input for special signals such as clock, reset
16bit strap pins for Software
Up to 59 GPIO interrupt controllers and 8 Hardware interrupt controllers
Multi IO power domain to support connecting to external devices with different
voltage supply
Vimicro Copyright© 1999-2011
Page 22 of 131
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VC0882 Data Book
Chapter 03
Pin Description
And
Package information
Vimicro Copyright© 1999-2011
Page 23 of 131
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VC0882 Data Book
3 Pin Description and Package info
3.1 Ball Map
1
2
DDR_DQS
DDR_DQ
3
4
DDR_DQ
5
6
7
8
DDR_DQ
DDR_DQ
SPI0_MIS
SPI0_SC
DDR_DQ10
A
_INV0
M1
DDR_DQ
DDR_DQ
KEYPAD
KEYPA
0
D2
8
2
0
O
LK
DDR_DQ
DDR_DQ
DDR_DQ
SPI0_MO
SPI0_SS
UART1_S
KEYPAD
KEYPA
M0
S0
15
5
7
SI
0N
DO
3
D6
DDR_DQS
DDR_DQ
AUD1_SD
UART0_S
UART1_
UART1_
UART1_
UART1_
KEYPAD
KEYPA
7
D11
KEYPAD
KEYPA
9
D12
VSSA_PL
VSSA_P
L12_1
LL12_3
AUD0_SD
AUD0_S
O_DAC
CK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEYPAD4
_INV1
S1
O_DAC
DO
DCDN
DSRN
CTSN
SDI
DDR_DQ1
DDR_DQ
AUD1_SDI
AUD1_W
UART0_
UART1_
UART1_
UART1_
2
11
_ADC
S
SDI
RIN
DTRN
RTSN
DDR_DQ1
DDR_DQ
VDD_IO_D
VDD_IO_
AUD1_S
PWM0
PWM1
VSS
4
9
DR
DDR
CK
DDR_DQ
VDD_IO_D
VDD_IO_
VDD_CO
KEYPAD5
D
E
AUD0_WS
DR
DDR
VSS
VSS
DDR_DQ
DDR_DQ1
RE_PMU
EF
DDR_A5
VSS
VSS
VSS
DDR_A7
VSS
VSS
VSS
DDR_RST
J
DI_ADC
DDR_VR
3
DDR_A3
VSS
AUD0_S
DDR_DQ4
6
H
11
KEYPAD1
C
G
10
DDR_DQ13
B
F
9
DDR_ZQ
DDR_OD
N
T0
DDR_BA
K
DDR_A13
DDR_A9
VSS
VSS
VSS
0
DDR_CS
L
DDR_A0
DDR_A2
VSS
VSS
VSS
0N
DDR_CL
M
DDR_CLK
DDR_CK
VSS
VSS
K_INV
VSS
E0
Figure 3-1
Vimicro Copyright© 1999-2011
Pin Allocation of 445BGA (left-top)
Page 24 of 131
www.vimicro.com
DDR_A
DDR_A
DDR_RA
VSS
N
1
12
DDR_A
DDR_A
11
10
DDR_A
DDR_B
4
A1
DDR_A
DDR_A
VC0882 Data Book
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DDR_WE
VSSA_AU
VSSA_A
VSSA_A
N
D_PA
UD_PA
UD
AUDC_S
AUDC_SP
AUDC_
USBOTG
PKOUTL
KOUTL_
MICBIA
_RREFEX
_P
N
S1
T
AUDC_S
AUDC_SP
VSSA_A
VSSA_A
PKOUTL
KOUTL_
UD
UD
_P
N
AUDC_H
AUDC_V
USBOTG
SOUTR
CAP
_VBUS
AUDC_H
VDDA_
SOUTL
AUD_HP
SN
DDR_CA
VSS
P
VSS
VSS
SN
VSS
R
VSS
VDD_IO_
VSS
VDD_IO_
DDR_BA
VSS
T
8
6
DDR
DDR
DDR_D
DDR_D
VDD_IO_
VDD_IO_
Q23
Q21
DDR
DDR
DDR_D
DDR_D
VDD_CO
VDD_COR
Q16
Q18
RE_GPU
E_GPU
2
DDR_ODT1
U
DDR_CKE1
V
DDR_D
DDR_D
DDR_CS1
VSSA_A
DDR_A14
W
Q27
Q29
VSSA_A
DDR_A15
N
UD
UD_PA
AUDC_S
DDR_D
DDR_D
VDD_CO
VDDA_A
VDDA_AU
AUDC_LI
AUDC_L
PKOUTR
Y
Q25
Q31
RE_PMU
UD_RCV
D_OPA
NER2_P
INER1_N
_N
VDDA_A
DDR_D
DDR_D
VDD_CO
VDDA_A
VDDA_AU
QS2
QM3
RE_PMU
UD_VIN
D_OPA
AUDC_S
UD_VOU
AA
PKOUTR
INER1_P
T
3
AUDC_R
DDR_D
DDR_DQ2
DDR_DQ3
QM2
8
0
QS_INV
DDR_DQ
DDR_DQ19
AUDC_LI
AUDC_LI
CVOUT_
22
P
DDR_D
DDR_DQ2
4
6
QS_INV
AC
QS3
DDR_DQ
DDR_DQ20
CVOUT_
3
4
Figure 3-2
Vimicro Copyright© 1999-2011
5
AUDC_LI
USBOTG
USBHOS
NEOUT1_
_DMINU
T_DMIN
P
S
US
NEL1_N
N
2
T_DPLUS
AUDC_LI
17
3
1
USBHOS
_DPLUS
N
AUDC_R
DDR_DQ2
USBOTG
NEOUT1_
NEL1_P
2
DDR_D
SBHOST3
_P
DDR_D
AB
VDDA_U
AUDC_L
6
7
8
9
Pin Allocation of 445BGA (left-bottom)
Page 25 of 131
10
11
www.vimicro.com
12
KEYPA
13
I2C_SCK
14
15
X32K_O
16
XCLKO
17
D8
0
UT0
KEYPA
KEYPA
I2C_SCK
18
XCLK
X32K_IN
VC0882 Data Book
19
20
21
22
NF_DAT
NF_DAT
NF_CE
NF_DAT
A2
A8
N2
A11
NF_DAT
NF_DAT
NF_DA
A10
A1
TA3
VDD_IO_
NF_DA
NF_DAT
NF
TA12
A13
NF_CLE
UT
IN
23
NF_WEN
A
NF_WPN
B
NF_RB0
C
XCLK
X32K_O
XCLK_O
_OUT
D10
D13
1
UT1
NF_CEN1
UT0
NF_REN
1
KEYPA
I2C_SDA
PMIC_IR
JTG_TD
JTG_TR
JTG_T
NF_CEN0
D14
0
KEYPA
I2C_SDA
D15
1
VSSA_P
VSSA_P
LL12_4
LL12_2
VDD_C
VDD_C
Q
NF_CEN3
O
STN
CK
EN_VDD
JTG_TM
JTG_T
NF_DAT
NF_DAT
NF_DAT
NF_AL
NF_DAT
NF_DATA
_CORE
S
DI
A0
A4
A9
E
A14
6
VSSA_P
VSSA_P
VDD_IO
VDDA_P
VDDA_P
VDDA_P
NF_DA
NF_DAT
NF_DATA
LL12_5
LL12_6
_SYS
LL12_1
LL12_3
LL12_4
TA5
A7
15
VDD_C
VDD_C
VDD_C
VDDA_P
VDDA_P
TEST
D
RSTN
ORE_AR
ORE_AR
ORE_AR
ORE_AR
E
VDDA_
ORE_AR
LL12_5
M
M
M
M
LL12_6
M
GPIO_A5
VDD_C
ORE_AR
ORE_AR
ORE_AR
ORE_AR
M
M
M
M
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GPIO_J30
G
SD2_CLK
H
GPIO_J2
12
9
GPIO_A
GPIO_A
1
0
SD2_DA
SD2_C
SD2_DA
SD2_DAT
TA0
MD
TA2
A1
SD2_DA
SD2_D
SD2_DA
SD2_RST
TA3
ATA4
TA5
N
SD2_DET
VDD_I
SD2_DA
SD2_DAT
ECTN
O_SD23
TA6
A7
VDD_IO_
VDD_I
LCD_SD
LCD
O_LCD
A
GPIO_A3
RE_PMU
VDD_C
F
GPIO_A
GPIO_A2
VDD_CO
VDD_C
GPIO_J28
7
2
GPIO_A4
VDD_C
GPIO_J2
PLL12_
VSS
VSS
VSS
VSS
J
VSS
K
VSS
L
VDD_CO
VSS
RE_VIDE
VSS
LCD_RDN
O
Figure 3-3
Vimicro Copyright© 1999-2011
Pin Allocation of 445BGA (right-top)
Page 26 of 131
M
www.vimicro.com
VC0882 Data Book
VDD_CO
VSS
VSS
VSS
VSS
RE_VIDE
LCD_D
LCD_DA
LCD_DA
LCD_DA
ATA18
TA23
TA13
TA21
LCD_D
LCD_DA
LCD_DA
ATA12
TA14
TA16
LCD_D
LCD_DA
LCD_WR
LCD_PCL
ATA5
TA10
N
K
LCD_DA
LCD_DA
TA8
TA9
VSS
N
O
CS_VSY
VSS
VSS
VSS
VSS
VSS
LCD_SCK
NC
VSSA_US
VSSA_U
VSSA_V
VSSA_V
CS_DAT
VSS
B
SB
DAC
DAC
P
R
A5
CS_DAT
LCD_D
CS_SDA
A6
LCD_RS
ATA4
T
TP_VRE
LCD_D
LCD_DA
LCD_DA
LCD_DA
F
ATA2
TA22
TA20
TA19
VSS_TP3
LCD_D
LCD_DA
LCD_DA
LCD_DA
3
ATA0
TA17
TA15
TA11
TP_KEYS
VSSA_T
LCD_C
LCD_DA
LCD_DA
LCD_DA
CAN
P33
S0N
TA6
TA7
TA3
TP_BAT_
VDDA_T
CS_RS
LCD_DA
LCD_RST
TA1
0N
U
VDDA_
VDD_CO
VDD_CO
VDD_CO
USBOTG
RE_COR
RE_COR
RE_COR
USBOTG_
V
ID
33
E
E
E
VSSA_U
VSSA_V
VSSA_V
VDD_EF
VDD_I
VSSA_US
O_SD0
B
SB
DAC
DAC
USE
W
1
USBHOST
VDAC_
VDAC_O
SD0_DA
SD1_DA
SD1_C
_RREFEX
CS_PWD0
OUTG
UTB
TA1
TA1
MD
TEMP
P33
TN0
VDAC_
VDAC_R
SD1_DA
SD1_DA
SD1_D
TP_BAT_
VDD_TP
VDD_I
Y
T
VDAC_V
CS_HSYN
CS_DATA
A
CS_SCK
REFIN
OUTR
SET
TA0
TA2
ATA3
VDAC_C
VDD_V
SD0_CM
SD0_DA
SD0_DA
OMP
DAC
D
TA0
TA2
ID
33
TP_XINP
TP_YINP
O_CS
C
7
CS_DA
CS_DATA
CS_DATA
TA1
0
3
CS_DATA
CS_DATA
A
SD1_D
ETECT
A
CS_CLK
B
N
TP_BA
VDAC_V
VDDA_
SD0_CL
SD0_DE
SD0_DA
SD1_C
TP_YIN
TP_XINN
REFOUT
VDAC
K
TECTN
TA3
LK
T_VOL
N
A
CS_PCLK
4
2
C
T
12
13
14
15
Figure 3-4
16
17
18
19
20
21
Pin Allocation of 445BGA (right-bottom)
Vimicro Copyright© 1999-2011
Page 27 of 131
22
23
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VC0882 Data Book
3.2 Pin description
Table 3-1 Signal Description of 445BGA
Pin Name
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
VDD_IO_SYS
I,RSTN
Reset Signal Input
RSTN
E17
I,Sh
XCLKIN
A17
I,Sh
VDD_IO_SYS
I,XCLKIN
External Crystal Input for System Clock
XCLKOUT
A16
O
VDD_IO_SYS
O,XCLKOUT
External Crystal Ouput for System Clock
A15
B，
4
VDD_IO_SYS
I,XCLK_32K_IN
External 32.768K Clock Input,Share with GPIO_A26
8
VDD_IO_SYS
I,GPIO_A22,PD
32.768K Clock Output 0,Share with GPIO_A22
8
VDD_IO_SYS
I,GPIO_A23,PD
32.768K Clock Output 1,Share with GPIO_A23
8
VDD_IO_SYS
I,GPIO_A27,PD
System Clock Output 0,Share with GPIO_A27
8
VDD_IO_SYS
I,GPIO_A24,PD
System Clock Output 1,GPIO_A24
4
VDD_IO_SYS
I,TEST
Test Mode Enable
4
VDD_IO_SYS
I,GPIO_A28,PD
4
VDD_IO_SYS
8
VDD_IO_SYS
I,GPIO_A0,PD
8
VDD_IO_SYS
I,GPIO_A1,PD
8
VDD_IO_SYS
I,GPIO_A2,PD
8
VDD_IO_SYS
I,GPIO_A3,PD
8
VDD_IO_SYS
I,GPIO_A4,PU
8
VDD_IO_SYS
I,GPIO_A5,PU
8
VDD_IO_SYS
I,GPIO_A12,PU
X32K_IN
Sh,
4
Pin Description
PD
X32K_OUT0
X32K_OUT1
XCLK_OUT0
XCLK_OUT1
TEST
PMIC_IRQ
EN_VDD_CO
A14
B,P
D
B15
B,P
D
B16
B,P
D
B17
B,P
D
D14
I,PD
C14
B,P
D
D15
RE
B,P
D
GPIO_A0
GPIO_A1
GPIO_A2
GPIO_A3
GPIO_A4
GPIO_A5
GPIO_A12
H22
B,P
D
H21
B,P
D
G20
B,P
D
H20
B,P
D
G19
B,P
U
H19
B,P
U
G21
B,P
U
Vimicro Copyright© 1999-2011
Interrupt Source and Wakeup Source from PMIC,Share with
GPIO_A28
O,EN_VDD_CO
Enable Power Supply To Digital Core, except Video Codec
RE
Core and 3D Core,Share with GPIO_A29
GPIO_A0,Share
with
NF_CEN8(NAND
Chip
Enable
Chip
Enable
Chip
Enable
Chip
Enable
Chip
Enable
Chip
Enable
8),Share with UMOUT0(ASIC debug)
GPIO_A1,Share
with
NF_CEN9(NAND
9),Share with UMOUT1(ASIC debug)
GPIO_A2,Share
with
NF_CEN10(NAND
10),Share with UMOUT2(ASIC debug)
GPIO_A3,Share
with
NF_CEN11(NAND
11),Share with UMOUT3(ASIC debug)
GPIO_A4,Share
with
NF_CEN12(NAND
12),Share with UMOUT4(ASIC debug)
GPIO_A5,Share
with
NF_CEN13(NAND
13),Share with UMOUT5(ASIC debug)
GPIO_A12,Share with SPI0_SS1N(SPI0 Slave Select 1,
only in SPI0 Master Mode),UMOUT12(ASIC debug)
Page 28 of 131
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Pin Name
VC0882 Data Book
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
4
VDD_IO_SYS
I,JTG_TCK,PU
JTAG Test Clock,Share with GPIO_A17
4
VDD_IO_SYS
I,JTG_TMS,PU
JTAG Test Mode Select,Share with GPIO_A18
4
VDD_IO_SYS
4
VDD_IO_SYS
I,JTG_TDI,PU
JTAG Test Data Input,Share with GPIO_A20
4
VDD_IO_SYS
B,JTG_TDO
JTAG Test Data Output,Share with GPIO_A21
4
VDD_IO_SYS
I,GPIO_C0,PD
PWM0 output,Share with GPIO_C0
4
VDD_IO_SYS
I,GPIO_C1,PD
PWM1 output,Share with GPIO_C1
8
VDD_IO_SYS
I,GPIO_C16,PU
I2C0 Serial Clock,Share with GPIO_C16
8
VDD_IO_SYS
I,GPIO_C17,PU
I2C0 Serial Data,Share with GPIO_C17
8
VDD_IO_SYS
I,GPIO_C18,PU
I2C1 Serial Clock,Share with GPIO_C18
8
VDD_IO_SYS
I,GPIO_C19,PU
I2C1 Serial Data,Share with GPIO_C19
4
VDD_IO_SYS
I,GPIO_C2,PU
UART0 Serial Data Output,Share with GPIO_C2
4
VDD_IO_SYS
I,GPIO_C3,PU
UART0 Serial Data Input,Share with GPIO_C3
4
VDD_IO_SYS
I,GPIO_C4,PU
4
VDD_IO_SYS
I,GPIO_C5,PU
4
VDD_IO_SYS
I,GPIO_C6,PU
C17
JTG_TCK
Pin Description
B,
PU,
Sh
JTG_TMS
D16
B,
PU
C16
JTG_TRSTN
B,
PD,
Sh
JTG_TDI
D17
PU
C15
JTG_TDO
PWM0
PWM1
E6
E7
B,
PU
C13
B,
PU
B14
B,
PU
D13
B,
PU
C4
UART0_SDO
UART1_DSR
B,P
D
I2C_SDA1
UART0_SDI
B,P
D
A13
I2C_SCK1
B,
PU
I2C_SCK0
I2C_SDA0
B,
B,
PU
D5
B,
PU
C6
N
B,
PU
UART1_DCD
C5
N
B,
PU
UART1_RIN
D6
B,
PU
Vimicro Copyright© 1999-2011
I,JTG_TRSTN,P
D
JTAG Test Reset,Share with GPIO_A19
UART1 Data Set Ready,Share with UART3_SDO(UART3
Serial Data Output),Share with GPIO_C4
UART1 Data Carrier Detect,Share with UART3_SDI(UART3
Serial Data Input),Share with GPIO_C5
UART1 Ring Indicator,Share with UART3_CTSN(UART3
Clear to Send),Share with GPIO_C6
Page 29 of 131
www.vimicro.com
Pin Name
UART1_DTR
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
VDD_IO_SYS
I,GPIO_C7,PD
D7
N
B,
PD
UART1_CTS
C7
N
B,
PU
UART1_RTSN
UART1_SDO
UART1_SDI
D8
B,
PD
B9
B,
PU
C8
B,
PU
A8
SPI0_SCLK
B,
PU
B8
SPI0_SS0N
B,
PU
B7
SPI0_MOSI
B,
PU
A7
SPI0_MISO
B,
PU
A10
KEYPAD0
B,P
U
A9
KEYPAD1
B,P
U
A11
KEYPAD2
B,P
U
B10
KEYPAD3
B,P
U
Pin Description
UART1
4
U
Terminal
Request
Ready,Share
to
Send),Share
4
VDD_IO_SYS
I,GPIO_C8,PU
UART1 Clear to Send,Share with GPIO_C8
4
VDD_IO_SYS
I,GPIO_C9,PD
UART1 Request to Send,Share with GPIO_C9
4
VDD_IO_SYS
I,GPIO_C10,PU
UART1 Serial Data Output,Share with GPIO_C10
4
VDD_IO_SYS
I,GPIO_C11,PU
UART1 Serial Data Input,Share with GPIO_C11
12
VDD_IO_SYS
I,GPIO_C20,PU
SPI0 Serial Clock,Share with GPIO_C20
8
VDD_IO_SYS
I,GPIO_C21,PU
SPI0 Slave Select 0,Share with GPIO_C21
8
VDD_IO_SYS
I,GPIO_C22,PU
SPI0 Master Out Slave In,Share with GPIO_C22
8
VDD_IO_SYS
I,GPIO_C23,PU
SPI0 Master In Slave Out,Share with GPIO_C23
Keypad
4
VDD_IO_SYS
I,GPIO_D0,PU
with
with
0,Share with TRACE_DATA0(Trace data0 for ARM
debug),Share with UMOUT16(ASIC debug),Share with
GPIO_D0
Keypad
4
VDD_IO_SYS
I,GPIO_D1,PU
1,Share with TRACE_DATA1(Trace data1 for ARM
debug),Share with UMOUT17(ASIC debug),Share with
GPIO_D1
Keypad
4
VDD_IO_SYS
I,GPIO_D2,PU
2,Share with TRACE_DATA2(Trace data2 for ARM
debug),Share with UMOUT18(ASIC debug),Share with
GPIO_D2
Keypad
4
VDD_IO_SYS
I,GPIO_D3,PU
3,Share with TRACE_DATA3(Trace data3 for ARM
debug),Share with UMOUT19(ASIC debug),Share with
GPIO_D3
Keypad
B,P
Data
UART3_RTSN(UART3
GPIO_C7
C9
KEYPAD4
VC0882 Data Book
4
VDD_IO_SYS
Vimicro Copyright© 1999-2011
I,GPIO_D4,PU
4,Share with TRACE_DATA4(Trace data4 for ARM
debug),Share with UMOUT20(ASIC debug),Share with
GPIO_D4
Page 30 of 131
www.vimicro.com
Pin Name
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
VDD_IO_SYS
I,GPIO_D5,PU
D9
KEYPAD5
U
B11
KEYPAD6
B,P
U
C10
KEYPAD7
B,P
U
A12
KEYPAD8
B,P
U
D10
KEYPAD9
B,P
U
B12
KEYPAD10
B,P
U
C11
KEYPAD11
B,P
U
D11
KEYPAD12
B,P
U
B13
KEYPAD13
B,P
U
C12
KEYPAD14
B,P
U
D12
KEYPAD15
B,P
U
F11
AUD0_SCK
B,P
B,
PD
VC0882 Data Book
Pin Description
Keypad
4
5,Share with TRACE_DATA5(Trace data5 for ARM
debug),Share with UMOUT21(ASIC debug),Share with
GPIO_D5
Keypad
4
VDD_IO_SYS
I,GPIO_D6,PU
6,Share with TRACE_DATA6(Trace data6 for ARM
debug),Share with UMOUT22(ASIC debug),Share with
GPIO_D6
Keypad
4
VDD_IO_SYS
I,GPIO_D7,PU
7,Share with TRACE_DATA7(Trace data7 for ARM
debug),Share with UMOUT23(ASIC debug),Share with
GPIO_D7
Keypad
4
VDD_IO_SYS
I,GPIO_D8,PU
8,Share with TRACE_DATA8(Trace data8 for ARM
debug),Share with UMOUT24ASIC debug),Share with
GPIO_D8
Keypad
4
VDD_IO_SYS
I,GPIO_D9,PU
9,Share with TRACE_DATA9(Trace data9 for ARM
debug),Share with UMOUT25(ASIC debug),Share with
GPIO_D9
Keypad 10,Share with TRACE_DATA10(Trace data10 for
4
VDD_IO_SYS
I,GPIO_D10,PU
ARM debug),Share with UMOUT26(ASIC debug),Share
with GPIO_D10
Keypad 11,Share with TRACE_DATA11(Trace data11 for
4
VDD_IO_SYS
I,GPIO_D11,PU
ARM debug),Share with UMOUT27(ASIC debug),Share
with GPIO_D11
Keypad 12,Share with TRACE_DATA12(Trace data12 for
4
VDD_IO_SYS
I,GPIO_D12,PU
ARM debug),Share with UMOUT28(ASIC debug),Share
with GPIO_D12
Keypad 13,Share with TRACE_DATA13(Trace data13 for
4
VDD_IO_SYS
I,GPIO_D13,PU
ARM debug),Share with UMOUT29(ASIC debug),Share
with GPIO_D13
Keypad 14,Share with TRACE_DATA14(Trace data14 for
4
VDD_IO_SYS
I,GPIO_D14,PU
ARM debug),Share with UMOUT30(ASIC debug),Share
with GPIO_D14
Keypad 15,Share with TRACE_DATA15(Trace data15 for
4
VDD_IO_SYS
I,GPIO_D15,PU
ARM debug),Share with UMOUT31(ASIC debug),Share
with GPIO_D15
Audio0 Bit Clock,Share with GPIO_D17
8
VDD_IO_SYS
Vimicro Copyright© 1999-2011
I,GPIO_D17,PD
Page 31 of 131
www.vimicro.com
Pin Name
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
4
VDD_IO_SYS
I,GPIO_D18,PD
4
VDD_IO_SYS
I,GPIO_D19,PD
Audio0 Serial Data Input From ADC,Share with GPIO_D19
4
VDD_IO_SYS
I,GPIO_D20,PD
Audio0 Serial Data
8
VDD_IO_SYS
I,GPIO_D22,PD
Audio1 Bit Clock,Share with GPIO_D22
4
VDD_IO_SYS
I,GPIO_D23,PD
4
VDD_IO_SYS
I,GPIO_D24,PD
Audio1 Serial Data Input From ADC,Share with GPIO_D24
4
VDD_IO_SYS
I,GPIO_D25,PD
Audio1 Serial Data
4
VDD_IO_CS
I,GPIO_H0,PD
Sensor Data 0,Share with GPIO_H0
4
VDD_IO_CS
I,GPIO_H1,PD
Sensor Data 1,Share with GPIO_H1
4
VDD_IO_CS
I,GPIO_H2,PD
Sensor Data 2,Share with GPIO_H2
4
VDD_IO_CS
I,GPIO_H3,PD
Sensor Data 3,Share with GPIO_H3
4
VDD_IO_CS
I,GPIO_H4,PD
Sensor Data 4,Share with GPIO_H4
4
VDD_IO_CS
I,GPIO_H5,PD
Sensor Data 5,Share with GPIO_H5
4
VDD_IO_CS
I,GPIO_H6,PD
Sensor Data 6,Share with GPIO_H6
4
VDD_IO_CS
I,GPIO_H7,PD
Sensor Data 7,Share with GPIO_H7
4
VDD_IO_CS
I,GPIO_H8,PD
Sensor HSYNC Input,Share with GPIO_H8
4
VDD_IO_CS
I,GPIO_H9,PD
Sensor VSYNC Input,Share with GPIO_H9
F9
AUD0_WS
AUD0_SDI_A
B,
PD
F8
DC
B,
PD
AUD0_SDO_
F10
DAC
E5
AUD1_SDI_A
B,
PD
AUD1_SCK
AUD1_WS
B,
PD
D4
B,
PD
D3
DC
B,
PD
AUD1_SDO_
C3
DAC
CS_DATA0
CS_DATA1
AB21
AB20
CS_HSYNC
AB22
B,
PD
B,
PD
R18
B,
PD
T18
B,
PD
AA22
B,
PD
AA21
B,
PD
P18
CS_VSYNC
B,
PD
AC21
CS_DATA7
B,
PD
CS_DATA4
CS_DATA6
B,
PD
AC22
CS_DATA5
B,
PD
CS_DATA2
CS_DATA3
VC0882 Data Book
B,
PD
Vimicro Copyright© 1999-2011
Pin Description
Audio0 Word Select For Both ADC & DAC,Share with
GPIO_D18
Output to DAC,Share with GPIO_D20
Audio1 Word Select For Both ADC & DAC,Share with
GPIO_D23
Output to DAC,Share with GPIO_D25
Page 32 of 131
www.vimicro.com
Pin Name
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
AC23
CS_PCLK
VC0882 Data Book
Pin Description
B,
PD,
4
VDD_IO_CS
I,GPIO_H10,PD
Sensor Pixel Clock,Share with GPIO_H10
16
VDD_IO_CS
I,GPIO_H11,PD
Sensor Master Clock,Share with GPIO_H11
4
VDD_IO_CS
I,GPIO_H12,PU
Sensor0 Reset,Share with GPIO_H12
4
VDD_IO_CS
I,GPIO_H13,PD
Sensor0 Power Down,Share with GPIO_H13
4
VDD_IO_CS
I,GPIO_H18,PU
Sensor Interface I2C Serial Clock,Share with GPIO_H18
4
VDD_IO_CS
I,GPIO_H19,PU
Sensor Interface I2C Serial Data,Share with GPIO_H19
8
VDD_IO_LCD
I,GPIO_I0,PD
LCD Data 0,Share with GPIO_I0
8
VDD_IO_LCD
I,GPIO_I1,PD
LCD Data 1,Share with GPIO_I1
8
VDD_IO_LCD
I,GPIO_I2,PD
LCD Data 2,Share with GPIO_I2
8
VDD_IO_LCD
I,GPIO_I3,PD
LCD Data 3,Share with GPIO_I3
8
VDD_IO_LCD
I,GPIO_I4,PD
LCD Data 4,Share with GPIO_I4
8
VDD_IO_LCD
I,GPIO_I5,PD
LCD Data 5,Share with GPIO_I5
8
VDD_IO_LCD
I,GPIO_I6,PD
LCD Data 6,Share with GPIO_I6
8
VDD_IO_LCD
I,GPIO_I7,PD
LCD Data 7,Share with GPIO_I7
8
VDD_IO_LCD
I,GPIO_I8,PD
LCD Data 8,Share with GPIO_I8
8
VDD_IO_LCD
I,GPIO_I9,PD
LCD Data 9,Share with GPIO_I9
8
VDD_IO_LCD
I,GPIO_I10,PD
LCD Data 10,Share with GPIO_I10
8
VDD_IO_LCD
I,GPIO_I11,PD
LCD Data 11,Share with GPIO_I11
Sh
CS_CLK
CS_RSTN0
CS_PWD0
CS_SCK
CS_SDA
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
LCD_DATA8
LCD_DATA9
LCD_DATA10
AB23
PD
Y20
B,
PU
Y21
B,
PD
AA23
B,
PU
T19
B,
PU
V20
B,
PD
Y22
B,
PD
U20
B,
PD
W23
B,
PD
T20
B,
PD
R20
B,
PD
W21
B,
PD
W22
B,
PD
T22
B,
PD
T23
B,
PD
R21
B,
PD
V23
LCD_DATA11
B,
B,
PD
Vimicro Copyright© 1999-2011
Page 33 of 131
www.vimicro.com
Pin Name
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
8
VDD_IO_LCD
I,GPIO_I12,PD
LCD Data 12,Share with GPIO_I12
8
VDD_IO_LCD
I,GPIO_I13,PD
LCD Data 13,Share with GPIO_I13
8
VDD_IO_LCD
I,GPIO_I14,PD
LCD Data 14,Share with GPIO_I14
8
VDD_IO_LCD
I,GPIO_I15,PD
LCD Data 15,Share with GPIO_I15
8
VDD_IO_LCD
I,GPIO_I16,PD
LCD Data 16,Share with GPIO_I16
8
VDD_IO_LCD
I,GPIO_I17,PD
LCD Data 17,Share with GPIO_I17
8
VDD_IO_LCD
I,GPIO_I18,PD
LCD Data 18,Share with GPIO_I18
8
VDD_IO_LCD
I,GPIO_I19,PD
LCD Data 19,Share with GPIO_I19
8
VDD_IO_LCD
I,GPIO_I20,PD
LCD Data 20,Share with GPIO_I20
8
VDD_IO_LCD
I,GPIO_I21,PD
LCD Data 21,Share with GPIO_I21
8
VDD_IO_LCD
I,GPIO_I22,PD
LCD Data 22,Share with GPIO_I22
8
VDD_IO_LCD
I,GPIO_I23,PD
LCD Data 23,Share with GPIO_I23
8
VDD_IO_LCD
I,GPIO_I24,PU
P20
N22
B,
PD
P21
B,
PD
V22
B,
PD
P22
B,
PD
V21
B,
PD
N20
B,
PD
U23
B,
PD
U22
B,
PD
N23
B,
PD
U21
B,
PD
N21
B,
PD
W20
B,
PU
T21
B,
PD
R22
LCD_WRN
B,
PU
M23
LCD_RDN
B,
PU
Y23
LCD_RST0N
B,
PD
LCD_CS0N
LCD_RS
VC0882 Data Book
B,
PD
Pin Description
LCD
Select
0
for
Main
Panel
(DBI),Share
with
LCD_CSX(LCD Serial Bus Chip Select(DPI)),Share with
GPIO_I24
8
VDD_IO_LCD
I,GPIO_I26,PD
LCD Register/Data Select (DBI),Share with LCD_DE(LCD
Data Enable (DPI)),Share with GPIO_I26
LCD Write Strobe
8
VDD_IO_LCD
I,GPIO_I27,PU
(DBI),Share with LCD_VSYNC(LCD
Vertical Sync (DPI)),Share with VGA_VSYNC(VGA Vertical
Sync),Share with GPIO_I27
LCD Read Strobe (DBI),Share with LCD_HSYNC(LCD
8
VDD_IO_LCD
I,GPIO_I28,PU
Horizontal
Sync
(DPI)),Share
with
VGA_HSYNC(VGA
Horizontal Sync),Share with GPIO_I28
LCD Panel Reset 0,Share with GPIO_I29
4
VDD_IO_LCD
Vimicro Copyright© 1999-2011
I,GPIO_I29,PD
Page 34 of 131
www.vimicro.com
Pin Name
LCD_PCLK
LCD_SDA
LCD_SCK
SD0_DATA0
SD0_DATA1
SD0_DATA2
SD0_DATA3
SD0_CLK
SD0_CMD
SD0_DETECT
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
16
VDD_IO_LCD
I,GPIO_I30,PD
LCD Pixel Clock (DPI),Share with GPIO_I30
4
VDD_IO_LCD
I,GPIO_I31,PU
LCD SPI Serial Bus Data Out (DPI),Share with GPIO_I31
4
VDD_IO_LCD
I,GPIO_H20,PU
LCD SPI Serial Bus Clock
I,GPIO_K0,PU
SDIO0 Card Data 0,Share with GPIO_K0
I,GPIO_K1,PU
SDIO0 Card Data 1,Share with GPIO_K1
I,GPIO_K2,PU
SDIO0 Card Data 2,Share with GPIO_K2
I,GPIO_K3,PU
SDIO0 Card Data 3,Share with GPIO_K3
I,GPIO_K4,PD
SDIO0 Card Clock,Share with
I,GPIO_K5,PU
SDIO0 Card Command/Response ,Share with GPIO_K5
I,GPIO_K6,PU
SDIO0 Card Detect, Low Active,Share with GPIO_K6
R23
B,
PD
M22
B,
PU
P23
B,
PU
AB15
B,P
U
Y15
B,P
U
AB16
B,P
U
AC16
B,P
U
AC14
B,
PD
AB14
B,
PU
AC15
N
B,
PU
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
AA15
Y16
B,P
U
AA16
B,P
U
AA17
B,P
U
AC17
SD1_DETECT
B,P
U
SD1_CLK
SD1_CMD
B,
PD
Y17
B,
PU
AB17
N
B,
PU
J20
SD2_DATA0
VC0882 Data Book
B,P
U
8
8
8
8
16
8
4
8
8
8
8
16
8
4
8
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD0
1
VDD_IO_SD2
3
Vimicro Copyright© 1999-2011
I,GPIO_K8,PU
I,GPIO_K9,PU
I,GPIO_K10,PU
I,GPIO_K11,PU
Pin Description
(DPI),Share with GPIO_H20
GPIO_K4
SDIO1 Card Data,Share with SPI2_SCLK(SPI2 Serial
Clock),Share with GPIO_K8
SDIO1 Card Data,Share with SPI2_SS0N(SP2 Slave Select
0),Share with GPIO_K9
SDIO1 Card Data,Share with SPI2_MOSI(SPI2 Master Out
Slave In),Share with GPIO_K10
SDIO1 Card Data,Share with SPI2_MISO(SPI2 Master In
Slave Out),Share with GPIO_K11
I,GPIO_K12,PD
SDIO1 Card Clock ,Share with GPIO_K12
I,GPIO_K13,PU
SDIO1 Card Command / Response ,Share with GPIO_K13
I,GPIO_K14,PU
SDIO1 Card Detect, Low Active,Share with GPIO_K14
SDIO2 Card Data 0,Share with GPIO_K20
I,GPIO_K20,PU
Page 35 of 131
www.vimicro.com
Pin Name
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD2_DATA4
SD2_DATA5
SD2_DATA6
SD2_DATA7
SD2_CLK
SD2_CMD
SD2_RSTN
SD2_DETECT
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
J23
B,P
U
J22
B,P
U
K20
B,P
U
K21
B,P
U
K22
B,P
U
L22
B,P
U
L23
B,P
U
H23
B,
PD
J21
B,
PU
K23
B,P
U
L20
N
B,
PU
NF_CEN0
NF_CEN1
NF_CEN2
NF_CEN3
NF_CLE
C18
PU
B18
B,
PU
A21
B,
PU
C19
B,
PU
A18
B,
PD
D21
NF_ALE
B,
PD
A23
NF_WEN
B,
B,
PU
8
8
8
8
8
8
8
16
8
4
4
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VDD_IO_SD2
3
VC0882 Data Book
Pin Description
I,GPIO_K21,PU
SDIO2 Card Data 1,Share with GPIO_K21
I,GPIO_K22,PU
SDIO2 Card Data 2,Share with GPIO_K22
I,GPIO_K23,PU
SDIO2 Card Data 3,Share with GPIO_K23
I,GPIO_K24,PU
SDIO2 Card Data 4,Share with GPIO_K24
I,GPIO_K25,PU
SDIO2 Card Data 5,Share with GPIO_K25
I,GPIO_K26,PU
SDIO2 Card Data 6,Share with GPIO_K26
I,GPIO_K27,PU
SDIO2 Card Data 7,Share with GPIO_K27
I,GPIO_K16,PD
SDIO2 Card Clock ,Share with GPIO_K16
I,GPIO_K17,PU
SDIO2 Card Command/Response ,Share with GPIO_K17
I,GPIO_K18,PU
SDIO2 Card Reset Signal,Share with GPIO_K18
I,GPIO_K19,PU
SDIO2 Card Detect, Share with GPIO_K19
8
VDD_IO_NF
I,GPIO_J20,PU
NAND Chip Enable 0,Share with GPIO_J20
8
VDD_IO_NF
I,GPIO_J21,PU
NAND Chip Enable 1,Share with GPIO_J21
8
VDD_IO_NF
I,GPIO_J22,PU
NAND Chip Enable 2,Share with GPIO_J22
8
VDD_IO_NF
I,GPIO_J23,PU
NAND Chip Enable 3,Share with GPIO_J23
8
VDD_IO_NF
I,GPIO_J16,PD
NAND Command Latch Enable,Share with
8
VDD_IO_NF
I,GPIO_J17,PD
NAND Address Latch Enable,Share with
NAND Write Enable,Share with
12
VDD_IO_NF
Vimicro Copyright© 1999-2011
GPIO_J17
GPIO_J18
I,GPIO_J18,PU
Page 36 of 131
GPIO_J16
www.vimicro.com
Pin Name
NF_REN
NF_DATA0
NF_DATA1
NF_DATA2
NF_DATA3
NF_DATA4
NF_DATA5
NF_DATA6
NF_DATA7
NF_DATA8
NF_DATA9
NF_DATA10
NF_DATA11
NF_DATA12
NF_DATA13
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
B22
PU
D18
B20
B,
PU
A19
B,
PU
B21
B,
PU
D19
B,
PU
E21
B,
PU
D23
B,
PU
E22
B,
PU
A20
B,
PU
D20
B,
PU
B19
B,
PU
A22
B,
PU
C21
B,
PU
C22
B,
PU
NF_DATA14
B,
PU
E23
B,
PU
B23
NF_WPN
B,
PU
D22
NF_DATA15
B,
B,
PD
VC0882 Data Book
Pin Description
12
VDD_IO_NF
I,GPIO_J19,PU
NAND Read Enable,Share with
8
VDD_IO_NF
I,GPIO_J0,PU
NAND Data 0,Share with GPIO_J0
8
VDD_IO_NF
I,GPIO_J1,PU
NAND Data 1,Share with GPIO_J1
8
VDD_IO_NF
I,GPIO_J2,PU
NAND Data 2,Share with GPIO_J2
8
VDD_IO_NF
I,GPIO_J3,PU
NAND Data 3,Share with GPIO_J3
8
VDD_IO_NF
I,GPIO_J4,PU
NAND Data 4,Share with GPIO_J4
8
VDD_IO_NF
I,GPIO_J5,PU
NAND Data 5,Share with GPIO_J5
8
VDD_IO_NF
I,GPIO_J6,PU
NAND Data 6,Share with GPIO_J6
8
VDD_IO_NF
I,GPIO_J7,PU
NAND Data 7,Share with GPIO_J7
8
VDD_IO_NF
I,GPIO_J8,PU
NAND Data 8,Share with GPIO_J8
8
VDD_IO_NF
I,GPIO_J9,PU
NAND Data 9,Share with GPIO_J9
8
VDD_IO_NF
I,GPIO_J10,PU
NAND Data 10,Share with GPIO_J10
8
VDD_IO_NF
I,GPIO_J11,PU
NAND Data 11,Share with GPIO_J11
8
VDD_IO_NF
I,GPIO_J12,PU
NAND Data 12,Share with GPIO_J12
8
VDD_IO_NF
I,GPIO_J13,PU
NAND Data 13,Share with GPIO_J13
8
VDD_IO_NF
I,GPIO_J14,PU
NAND Data 14,Share with GPIO_J14
8
VDD_IO_NF
I,GPIO_J15,PU
NAND Data 15,Share with GPIO_J15
NAND Write Protect,Share with
8
VDD_IO_NF
Vimicro Copyright© 1999-2011
GPIO_J19
GPIO_J24
I,GPIO_J24,PD
Page 37 of 131
www.vimicro.com
Pin Name
NF_RB0
GPIO_J27
GPIO_J28
GPIO_J29
GPIO_J30
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
C23
B,
PU
F22
B,P
U
F23
B,P
U
G22
B,P
U
G23
B,P
U
VC0882 Data Book
Pin Description
4
VDD_IO_NF
I,GPIO_J25,PU
NAND Ready/Busy 0,Share with
8
VDD_IO_NF
I,GPIO_J27,PU
GPIO_J27,Share with NF_CEN4(NAND Chip Enable 4)
8
VDD_IO_NF
I,GPIO_J28,PU
GPIO_J28,Share with NF_CEN5(NAND Chip Enable 5)
8
VDD_IO_NF
I,GPIO_J29,PU
GPIO_J29,Share with NF_CEN6(NAND Chip Enable 6)
8
VDD_IO_NF
I,GPIO_J30,PU
GPIO_J30,Share with NF_CEN7(NAND Chip Enable 7)
DDR_CS0N
L6
O
VDD_IO_DDR
O,DDR_CS0N
DDR SDRAM Chip Select 0
DDR_CS1N
W3
O
VDD_IO_DDR
O,DDR_CS1N
DDR SDRAM Chip Select 1
DDR_A0
L1
O
VDD_IO_DDR
O,DDR_A0
DDR SDRAM Memory Address 0
DDR_A1
N1
O
VDD_IO_DDR
O,DDR_A1
DDR SDRAM Memory Address 1
DDR_A2
L2
O
VDD_IO_DDR
O,DDR_A2
DDR SDRAM Memory Address 2
O
VDD_IO_DDR
O,DDR_A3
DDR SDRAM Memory Address 3
O
VDD_IO_DDR
O,DDR_A4
DDR SDRAM Memory Address 4
DDR_A3
DDR_A4
H1
R1
DDR_A5
H2
O
VDD_IO_DDR
O,DDR_A5
DDR SDRAM Memory Address 5
DDR_A6
T2
O
VDD_IO_DDR
O,DDR_A6
DDR SDRAM Memory Address 6
DDR_A7
J2
O
VDD_IO_DDR
O,DDR_A7
DDR SDRAM Memory Address 7
DDR_A8
T1
O
VDD_IO_DDR
O,DDR_A8
DDR SDRAM Memory Address 8
DDR_A9
K2
O
VDD_IO_DDR
O,DDR_A9
DDR SDRAM Memory Address 9
DDR_A10
P2
O
VDD_IO_DDR
O,DDR_A10
DDR SDRAM Memory Address 10
DDR_A11
P1
O
VDD_IO_DDR
O,DDR_A11
DDR SDRAM Memory Address 11
DDR_A12
N2
O
VDD_IO_DDR
O,DDR_A12
DDR SDRAM Memory Address 12
DDR_A13
K1
O
VDD_IO_DDR
O,DDR_A13
DDR SDRAM Memory Address 13
DDR_A14
W4
O
VDD_IO_DDR
O,DDR_A14
DDR SDRAM Memory Address 14
DDR_A15
W5
O
VDD_IO_DDR
O,DDR_A15
DDR SDRAM Memory Address 15
O
VDD_IO_DDR
DDR_CLK_IN
M2
V
O,DDR_CLK_IN
V
GPIO_J25
DDR SDRAM Clock Inverse
DDR_CLK
M1
O
VDD_IO_DDR
O,DDR_CLK
DDR SDRAM Clock
DDR_CKE0
M6
O
VDD_IO_DDR
O,DDR_CKE0
DDR SDRAM Clock Enable 0
DDR_CKE1
V5
O
VDD_IO_DDR
O,DDR_CKE1
DDR SDRAM Clock Enable 1
DDR_CASN
P6
O
VDD_IO_DDR
O,DDR_CASN
DDR SDRAM Column Address Select
DDR_RASN
N6
O
VDD_IO_DDR
O,DDR_RASN
DDR SDRAM Row Address Select
Vimicro Copyright© 1999-2011
Page 38 of 131
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Pin Name
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
VC0882 Data Book
Pin Description
Range(v)
Release
DDR_WEN
R6
O
VDD_IO_DDR
O,DDR_WEN
DDR SDRAM Write Enable
DDR_DQM0
B1
O
VDD_IO_DDR
O,DDR_DQM0
DDR SDRAM Data Read/Write Mask, Byte 0
DDR_DQM1
A2
O
VDD_IO_DDR
O,DDR_DQM1
DDR SDRAM Data Read/Write Mask, Byte 1
DDR_DQM2
AB2
O
VDD_IO_DDR
O,DDR_DQM2
DDR SDRAM Data Read/Write Mask, Byte 2
DDR_DQM3
AA2
O
VDD_IO_DDR
O,DDR_DQM3
DDR SDRAM Data Read/Write Mask, Byte 3
DDR_BA0
K6
O
VDD_IO_DDR
O,DDR_BA0
DDR SDRAM Bank 0 Access
DDR_BA1
R2
O
VDD_IO_DDR
O,DDR_BA1
DDR SDRAM Bank 1 Access
DDR_BA2
T6
O
VDD_IO_DDR
O,DDR_BA2
DDR SDRAM Bank 2 Access
DDR_DQ0
A6
B
VDD_IO_DDR
B,DDR_DQ0
DDR SDRAM Data 0
DDR_DQ1
G1
B
VDD_IO_DDR
B,DDR_DQ1
DDR SDRAM Data 1
DDR_DQ2
A5
B
VDD_IO_DDR
B,DDR_DQ2
DDR SDRAM Data 2
DDR_DQ3
G2
B
VDD_IO_DDR
B,DDR_DQ3
DDR SDRAM Data 3
DDR_DQ4
F1
B
VDD_IO_DDR
B,DDR_DQ4
DDR SDRAM Data 4
DDR_DQ5
B5
B
VDD_IO_DDR
B,DDR_DQ5
DDR SDRAM Data 5
DDR_DQ6
F2
B
VDD_IO_DDR
B,DDR_DQ6
DDR SDRAM Data 6
DDR_DQ7
B6
B
VDD_IO_DDR
B,DDR_DQ7
DDR SDRAM Data 7
DDR_DQ8
A4
B
VDD_IO_DDR
B,DDR_DQ8
DDR SDRAM Data 8
DDR_DQ9
E2
B
VDD_IO_DDR
B,DDR_DQ9
DDR SDRAM Data 9
DDR_DQ10
A3
B
VDD_IO_DDR
B,DDR_DQ10
DDR SDRAM Data 10
DDR_DQ11
D2
B
VDD_IO_DDR
B,DDR_DQ11
DDR SDRAM Data 11
DDR_DQ12
D1
B
VDD_IO_DDR
B,DDR_DQ12
DDR SDRAM Data 12
DDR_DQ13
B3
B
VDD_IO_DDR
B,DDR_DQ13
DDR SDRAM Data 13
DDR_DQ14
E1
B
VDD_IO_DDR
B,DDR_DQ14
DDR SDRAM Data 14
DDR_DQ15
B4
B
VDD_IO_DDR
B,DDR_DQ15
DDR SDRAM Data 15
DDR_DQ16
V1
B
VDD_IO_DDR
B,DDR_DQ16
DDR SDRAM Data 16
DDR_DQ17
AC6
B
VDD_IO_DDR
B,DDR_DQ17
DDR SDRAM Data 17
DDR_DQ18
V2
B
VDD_IO_DDR
B,DDR_DQ18
DDR SDRAM Data 18
DDR_DQ19
AB5
B
VDD_IO_DDR
B,DDR_DQ19
DDR SDRAM Data 19
DDR_DQ20
AC5
B
VDD_IO_DDR
B,DDR_DQ20
DDR SDRAM Data 20
DDR_DQ21
U2
B
VDD_IO_DDR
B,DDR_DQ21
DDR SDRAM Data 21
DDR_DQ22
AB6
B
VDD_IO_DDR
B,DDR_DQ22
DDR SDRAM Data 22
DDR_DQ23
U1
B
VDD_IO_DDR
B,DDR_DQ23
DDR SDRAM Data 23
DDR_DQ24
AC3
B
VDD_IO_DDR
B,DDR_DQ24
DDR SDRAM Data 24
DDR_DQ25
Y1
B
VDD_IO_DDR
B,DDR_DQ25
DDR SDRAM Data 25
DDR_DQ26
AC4
B
VDD_IO_DDR
B,DDR_DQ26
DDR SDRAM Data 26
B
VDD_IO_DDR
B,DDR_DQ27
DDR_DQ27
W1
Vimicro Copyright© 1999-2011
DDR SDRAM Data 27
Page 39 of 131
www.vimicro.com
Pin Name
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
VC0882 Data Book
Pin Description
Range(v)
Release
DDR_DQ28
AB3
B
VDD_IO_DDR
B,DDR_DQ28
DDR SDRAM Data 28
DDR_DQ29
W2
B
VDD_IO_DDR
B,DDR_DQ29
DDR SDRAM Data 29
DDR_DQ30
AB4
B
VDD_IO_DDR
B,DDR_DQ30
DDR SDRAM Data 30
DDR_DQ31
Y2
B
VDD_IO_DDR
B,DDR_DQ31
DDR SDRAM Data 31
DDR_DQS0
B2
B
VDD_IO_DDR
B,DDR_DQS0
DDR SDRAM Data Strobe,Byte 0
DDR_DQS1
C2
B
VDD_IO_DDR
B,DDR_DQS1
DDR SDRAM Data Strobe,Byte 1
DDR_DQS2
AA1
B
VDD_IO_DDR
B,DDR_DQS2
DDR SDRAM Data Strobe,Byte 2
DDR_DQS3
AC1
B
VDD_IO_DDR
B,DDR_DQS3
DDR SDRAM Data Strobe,Byte 3
B
VDD_IO_DDR
B
VDD_IO_DDR
B
VDD_IO_DDR
B
VDD_IO_DDR
DDR_DQS_IN
A1
V0
DDR_DQS_IN
C1
V1
DDR_DQS_IN
AB1
V2
DDR_DQS_IN
AC2
V3
B,DDR_DQS_IN
V0
B,DDR_DQS_IN
V1
B,DDR_DQS_IN
V2
B,DDR_DQS_IN
V3
DDR SDRAM Data Strobe Inverse,Byte 0
DDR SDRAM Data Strobe Inverse,Byte 1
DDR SDRAM Data Strobe Inverse,Byte 2
DDR SDRAM Data Strobe Inverse,Byte 3
DDR_RSTN
J1
O
VDD_IO_DDR
O,DDR_RSTN
DDR SDRAM Reset Signal, only for DDR3
DDR_ODT0
J6
O
VDD_IO_DDR
O,DDR_ODT0
DDR SDRAM On Die Termination 0
DDR_ODT1
U5
O
VDD_IO_DDR
O,DDR_ODT1
DDR SDRAM On Die Termination 1
DDR_ZQ
H6
I
VDD_IO_DDR
I, DDR_ZQ
DDR SDRAM ZQ
VDAC_RSET
AA14
AIO
VDAC External Resistor Connected to Analog Ground of
VDAC Bias Circuit
VDAC_OUTR
AA13
AO
VDAC Channal R Output
VDAC_OUTG
Y13
AO
VDAC Channal G Output
VDAC_OUTB
Y14
AO
VDAC Channal B Output
VDAC_VREFI
AA12
AI
VDAC
Reference Voltage Input
AO
VDAC
Reference Voltage Output
N
VDAC_VREF
AC12
OUT
VDAC_COMP
USBOTG_RR
AB12
V11
EFEXT
USBOTG_DP
AB10
LUS
USBOTG_DM
INUS
AC10
AIO
VDAC Compensation Pin, Connecting External 0.1uF
Capacitor to VDAC Analog Power
AIO
USB OTG External Resistor For Current Reference
AIO
USB OTG
AIO
USB OTG D- Port
Vimicro Copyright© 1999-2011
D+ Port
Page 40 of 131
www.vimicro.com
Pin Name
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
USBOTG_ID
V12
USBOTG_VB
Y11
US
USBHOST_R
Y12
REFEXT
USBHOST_D
AB11
PLUS
USBHOST_D
AC11
MINUS
AUDC_VCAP
AUDC_LINEL
Y10
AB8
1_P
AUDC_LINEL
AC8
1_N
AUDC_LINER
AA7
1_P
AUDC_LINER
Y7
1_N
AUDC_LINER
Y6
2_P
AUDC_HSOU
AA9
TL
AUDC_HSOU
Y9
TR
AUDC_RCVO
AB7
UT_P
AUDC_RCVO
AC7
UT_N
AUDC_SPKO
V8
UTL_P
AUDC_SPKO
W8
UTL_P
AUDC_SPKO
V9
UTL_N
AUDC_SPKO
UTL_N
VC0882 Data Book
Pin Description
AIO
USB OTG ID
AIO
USB OTG VBUS
AIO
USB HOST
External Resistor For Current Reference
AIO
USB HOST
D+ Port
AIO
USB HOST
D- Port
AO
Internally Generated Common-Mode Voltage Output
AI
Left Differential Line 1 Positive Input
AI
Left Differential Line 1 Negative Input
AI
Right Differential Line 1 Positive Input
AI
Right Differential Line 1 Negative Input
AI
Right Differential Line 2 Positive Input
AO
Left Stereo Single-End Headphone Output
AO
Right Stereo Single-End Headphone Output
AO
Mono Differential Receiver Positive Output
AO
Mono Differential Receiver Negative Output
AO
Left Stereo Differential Speaker Positive Output
AO
Left Stereo Differential Speaker Positive Output
AO
Left Stereo Differential Speaker Negative Output
W9
Left Stereo Differential Speaker Negative Output
AO
Vimicro Copyright© 1999-2011
Page 41 of 131
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Pin Name
AUDC_SPKO
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
AA8
UTR_P
AUDC_SPKO
Y8
UTR_N
AUDC_LINEO
AC9
UT1_P
AUDC_LINEO
AB9
UT1_N
AUDC_MICBI
V10
AS1
VC0882 Data Book
Pin Description
AO
Right Stereo Differential Speaker Positive Output
AO
Right Stereo Differential Speaker Negative Output
AO
Mono Differential Line 1 Positive Output
AO
Mono Differential Line 1 Negative Output
AO
Microphone Bias Voltage Output 1
TP_XINP
AB18
AIO
Touch Panel X Value of Positive
TP_XINN
AC18
AIO
Touch Panel X Value of Negative End
TP_YINP
AB19
AIO
Touch Panel Y Value of Positive
TP_YINN
AC19
AIO
Touch Panel Y Value of Negative End
TP_BAT_VOL
AC20
T
TP_BAT_TEM
Y18
P
TP_BAT_ID
AA18
TP_KEYSCA
W18
N
TP_VREF
VDDA_VDAC
VDD_VDAC
VSSA_VDAC
VSSA_VDAC
VSSA_VDAC
VSSA_VDAC
VDDA_PLL12
_1
U19
AC13
AI
0 ~ 2.4v
Touch Panel Battery Voltage
AI
0 ~ 2.4v
Touch Panel Battery Temperature
AI
0 ~ 2.4v
Touch Panel Battery ID
AI
0 ~ 2.4v
Touch Panel Analog Key Scan In
AO
PW
R
AB13
PW
R
R14
GN
D
R15
GN
D
W14
GN
D
W15
GN
D
E18
PW
R
End
End
Touch Panel Reference Voltage Positive Output
2.25~2.75v or
3.0 ~ 3.6v
2.25~2.75v or
3.0 ~ 3.6v
VDAC Analog Power for Channel R/G/B
VDAC Digital
Power
0V
VDAC Analog Ground for Channel R/G/B/Bias Circuit
0V
VDAC Analog Ground for Channel R/G/B/Bias Circuit
0V
VDAC Analog Ground for Channel R/G/B/Bias Circuit
0V
VDAC Analog Ground for Channel R/G/B/Bias Circuit
PLL Analog Power 1
1.0v ~1.5v
Vimicro Copyright© 1999-2011
Page 42 of 131
www.vimicro.com
Pin Name
VSSA_PLL12
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
E10
_1
GN
D
VDDA_PLL12
F21
_2
PW
R
VSSA_PLL12
E13
_2
GN
D
VDDA_PLL12
E19
_3
PW
R
VSSA_PLL12
E11
_3
GN
D
VDDA_PLL12
E20
_4
PW
R
VSSA_PLL12
E12
_4
GN
D
VDDA_PLL12
F19
_5
PW
R
VSSA_PLL12
E14
_5
GN
D
VDDA_PLL12
F20
_6
PW
R
VSSA_PLL12
E15
_6
GN
D
VDDA_USBO
V13
TG33
VDDA_USBH
AA11
OST33
VSSA_USB
VSSA_USB
VSSA_USB
PW
R
R12
GN
D
R13
GN
D
W12
GN
D
W13
VSSA_USB
GN
D
Y19
VDDA_TP33
PW
R
PW
R
VC0882 Data Book
Pin Description
0V
PLL Analog Ground
1.0v ~1.5v
PLL Analog Power 2
0V
PLL Analog Ground 2
1.0v ~1.5v
PLL Analog Power 3
0V
PLL Analog Ground
1.0v ~1.5v
PLL Analog Power 4
0V
PLL Analog Ground
1.0v ~1.5v
PLL Analog Power 5
0V
PLL Analog Ground 5
1.0v ~1.5v
PLL Analog Power 6
0V
PLL Analog Ground
1
3
4
6
3.0v ~ 3.6v
USB OTG PHY Analog Power 3.3v
3.0v ~ 3.6v
USB PHY Analog Power 3.3v
0V
USB PHY Analog Ground
0V
USB PHY Analog Ground
0V
USB PHY Analog Ground
0V
USB PHY Analog Ground
Touch Panel SAR ADC Analog Power
3.0v ~ 3.6v
Vimicro Copyright© 1999-2011
Page 43 of 131
www.vimicro.com
Pin Name
VSSA_TP33
VSSA_AUD
VSSA_AUD
VDDA_AUD_
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
W19
GN
D
R11
PW
R
W6
GN
D
AA10
HP
PW
R
VSSA_AUD
VSSA_AUD_P
W10
GN
D
R9
A
GN
D
VDDA_AUD_
Y5
OPA
VDDA_AUD_
R
AA5
OPA
VSSA_AUD_P
PW
PW
R
R10
A
GN
D
VSSA_AUD_P
W7
A
GN
D
VDDA_AUD_
Y4
RCV
R
W11
VSSA_AUD
VDDA_AUD_
PW
GN
D
AA4
VIN
PW
R
VDDA_AUD_
AA6
VOUT
VDD_CORE_
F12
ARM
VDD_CORE_
F13
ARM
PW
R
F14
ARM
VDD_CORE_
PW
R
ARM
VDD_CORE_
AO
PW
R
F15
PW
R
0V
0v
0v
2.25v ~ 2.75v
0v
0v
2.7v ~ 3.6v
2.7v ~ 3.6v
VC0882 Data Book
Pin Description
Touch Panel SAR ADC Analog Ground
AUD Ground for Receiver PA, Internal LDO , Headphone &
Linein IO
AUD Ground for Receiver PA, Internal LDO , Headphone &
Linein IO
AUD 2.5 V Power Supply For Headphone
AUD Ground for Receiver PA ,Internal LDO , Headphone &
Linein IO
AUD 3.3 V Ground For Speaker PA & Speaker PA IO
AUD 3.3 V Power Supply For Speaker PA Macro & Speaker
PA IO
AUD 3.3 V Power Supply For Speaker PA Macro & Speaker
PA IO
0v
AUD 3.3 V Ground For Speaker PA & Speaker PA IO
0v
AUD 3.3 V Ground For Speaker PA & Speaker PA IO
2.7v ~ 3.6v
0v
2.7v ~ 3.6v
2.25v ~ 2.75v
AUD 3.3 V Power Supply For Receiver PA
AUD Ground for Receiver PA ,Internal LDO , Headphone &
Linein IO
AUD 3.3 V Power Supply Input
AUD 2.5V
internal LDO Output
1.0v ~1.5v
ARM Core Digital Power
1.0v ~1.5v
ARM Core Digital Power
1.0v ~1.5v
ARM Core Digital Power
ARM Core Digital Power
1.0v ~1.5v
Vimicro Copyright© 1999-2011
Page 44 of 131
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Pin Name
VDD_CORE_
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
F16
ARM
VDD_CORE_
R
J12
ARM
VDD_CORE_
J13
J14
J15
M18
N18
V3
V4
V14
V15
V16
F5
H18
Y3
AA3
PW
R
E16
PW
R
M20
VDD_IO_LCD
PW
R
PMU
VDD_IO_SYS
PW
R
PMU
VDD_CORE_
PW
R
PMU
VDD_CORE_
PW
R
PMU
VDD_CORE_
PW
R
CORE
VDD_CORE_
PW
R
CORE
VDD_CORE_
PW
R
CORE
VDD_CORE_
PW
R
GPU
VDD_CORE_
PW
R
GPU
VDD_CORE_
PW
R
VIDEO
VDD_CORE_
PW
R
VIDEO
VDD_CORE_
PW
R
ARM
VDD_CORE_
PW
R
ARM
VDD_CORE_
PW
R
ARM
VDD_CORE_
PW
PW
R
VC0882 Data Book
Pin Description
1.0v ~1.5v
ARM Core Digital Power
1.0v ~1.5v
ARM Core Digital Power
1.0v ~1.5v
ARM Core Digital Power
1.0v ~1.5v
ARM Core Digital Power
1.0v ~1.5v
ARM Core Digital Power
1.0v ~1.5v
Video Core Power
1.0v ~1.5v
Video Core Power
1.0v ~1.5v
GPU Core Power
1.0v ~1.5v
GPU Core Power
1.0v ~1.5v
1.0v ~1.5v
1.0v ~1.5v
1.0v ~1.5v
1.0v ~1.5v
1.0v ~1.5v
1.0v ~1.5v
2.6v ~ 3.0v
Shutdown Domain Core Digital Power except ARM, Video
Codec & GPU
Shutdown Domain Core Digital Power except ARM, Video
Codec & GPU
Shutdown Domain Core Digital Power except ARM, Video
Codec & GPU
PMU Domain Core Logic Digital Power and ALL DIGITAL I/O
Core Power
PMU Domain Core Logic Digital Power and ALL DIGITAL I/O
Core Power
PMU Domain Core Logic Digital Power and ALL DIGITAL I/O
Core Power
PMU Domain Core Logic Digital Power and ALL DIGITAL I/O
Core Power
SYS
I/O Digital Power
LCD I/O Digital Power
1.7v ~ 3.6v
Vimicro Copyright© 1999-2011
Page 45 of 131
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Pin Name
VDD_IO_LCD
VDD_IO_NF
VDD_IO_SD0
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
M21
PW
R
C20
PW
R
W17
1
PW
R
VDD_IO_SD2
L21
3
PW
R
VDD_IO_CS
AA20
PW
R
E3
VDD_IO_DDR
PW
R
E4
VDD_IO_DDR
PW
R
F3
VDD_IO_DDR
PW
R
F4
VDD_IO_DDR
PW
R
T3
VDD_IO_DDR
PW
R
T4
VDD_IO_DDR
PW
R
U3
VDD_IO_DDR
PW
R
U4
VDD_IO_DDR
PW
R
Pin Description
1.7v ~ 3.6v
LCD I/O Digital Power
1.7v ~ 3.6v
NAND Flash I/O Digital Power
1.7v ~ 3.6v
SDIO 0/1
I/O Digital Power
1.7v ~ 3.6v
SDIO 2/3
I/O Digital Power
1.7v ~ 3.6v
Camera Sensor I/O Digital Power
1.7v ~ 1.95v
1.425 ~
DDR PHY I/O Power
1.575v
1.7v ~ 1.95v
1.425 ~
DDR PHY I/O Power
1.575v
1.7v ~ 1.95v
1.425 ~
DDR PHY I/O Power
1.575v
1.7v ~ 1.95v
1.425 ~
DDR PHY I/O Power
1.575v
1.7v ~ 1.95v
1.425 ~
DDR PHY I/O Power
1.575v
1.7v ~ 1.95v
1.425 ~
DDR PHY I/O Power
1.575v
1.7v ~ 1.95v
1.425 ~
DDR PHY I/O Power
1.575v
1.7v ~ 1.95v
1.425 ~
DDR PHY I/O Power
1.575v
G5
DDR_VREF
VC0882 Data Book
DDR PHY SSTL Reference Power
PW
R
0.5 *
VDD_IO_DDR
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Pin Name
VDD_EFUSE
VDD_TP33
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
W16
R
AA19
V19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GN
D
E8
GN
D
E9
GN
D
G3
GN
D
G4
GN
D
H3
GN
D
H4
GN
D
H5
GN
D
J3
GN
D
J4
GN
D
J5
GN
D
J9
GN
D
J10
GN
D
J11
GN
D
J18
VSS
GN
D
J19
VSS
PW
R
VSS_TP33
VSS
PW
GN
D
2.25 ~ 2.75v
VC0882 Data Book
Pin Description
On-chip Efuse Cell Power
3.0v ~ 3.6v
Touch Panel SAR ADC 3.3v Digital Power
0v
Touch Panel SAR ADC 3.3v Digital Ground
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
0v
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Ground
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Pin Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
K3
D
K4
GN
D
K5
GN
D
K9
GN
D
K10
GN
D
K11
GN
D
K12
GN
D
K13
GN
D
K14
GN
D
K15
GN
D
K18
GN
D
K19
GN
D
L3
GN
D
L4
GN
D
L5
GN
D
L9
GN
D
L10
VSS
GN
D
L11
VSS
GN
GN
D
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
VC0882 Data Book
Pin Description
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
0v
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Ground
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Pin Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
L12
D
L13
GN
D
L14
GN
D
L15
GN
D
L18
GN
D
L19
GN
D
M3
GN
D
M4
GN
D
M5
GN
D
M9
GN
D
M10
GN
D
M11
GN
D
M12
GN
D
M13
GN
D
M14
GN
D
M15
GN
D
M19
VSS
GN
D
N3
VSS
GN
GN
D
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
VC0882 Data Book
Pin Description
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
0v
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Ground
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Pin Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
N4
D
N5
GN
D
N9
GN
D
N10
GN
D
N11
GN
D
N12
GN
D
N13
GN
D
N14
GN
D
N15
GN
D
N19
GN
D
P3
GN
D
P4
GN
D
P5
GN
D
P9
GN
D
P10
GN
D
P11
GN
D
P12
VSS
GN
D
P13
VSS
GN
GN
D
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
0v
VC0882 Data Book
Pin Description
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
0v
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Ground
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Pin Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
Pin
Drive
I/O
State
No.
Typ
Strength
Power
After
e
(mA)
Or
Reset
Range(v)
Release
P14
GN
D
P15
GN
D
P19
GN
D
R3
GN
D
R4
GN
D
R5
GN
D
R19
GN
D
T5
GN
D
0v
0v
0v
0v
0v
0v
0v
0v
Vimicro Copyright© 1999-2011
VC0882 Data Book
Pin Description
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
Digital IO & Pre-driver Ground and Digital Core Logic
Ground
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VC0882 Data Book
3.3 Package Information
Figure3-5
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Top View of 445BGA Package
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Figure 3-6
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Bottom View of 445BGA Package
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Figure 3-7
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Side View of 445BGA Package
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Table 3-2
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Parameters of 445BGA Package
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VC0882 Data Book
Chapter 04
CPU
SubSystem
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4 CPU SubSystem
4.1
CORTEX-A8 Features
The Cortex-A8 processor is a high-performance, low-power, cached application processor that
provides full virtual memory capabilities. The features of the processor
include:
Full implementation of the ARM architecture v7-A instruction set
64-bit high-speed Advanced Microprocessor Bus
Architecture (AMBA) with Advanced Extensible Interface (AXI) for main
memory interface supporting multiple outstanding transactions
A pipeline for executing ARM integer instructions
A NEON pipeline for executing Advanced SIMD and VFP instruction sets
Dynamic branch prediction with branch target address cache, global history
buffer, and 8-entry return stack
Memory Management Unit (MMU) and separate instruction and data Translation
Look-aside Buffers (TLBs) of 32 entries each
Level 1 instruction and data caches of 32KB
Level 2 cache of 128KB
Level 2 cache with parity and Error Correction Code (ECC) configuration option
Embedded Trace Macrocell (ETM) support for non-invasive debug
Static and dynamic power management including Intelligent Energy Management
(IEM)
ARMv7 debug with watchpoint and breakpoint registers and a 32-bit Advanced
Peripheral Bus (APB) slave interface to a CoreSight debug system.
CoreSight Sub-system Features
CoreSight systems provide all the infrastructure you require to debug, monitor, and
optimize the performance of a complete System on Chip (SoC) design.
There are historically three main ways of debugging an ARM processor based SoC:
Conventional JTAG debug. This is invasive debug with the core halted using:
breakpoints and watchpoints to halt the core on specific activity
a debug connection to examine and modify registers and memory and
provide single-step execution.
Conventional monitor debug
This is invasive debug with the core running using a debug monitor that resides in memory.
Trace
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VC0882 Data Book
This is non-invasive debug with the core running at full speed using:
collection of information on instruction execution and data transfers
delivery off-chip in real-time
tools to merge data with source code on a development workstation for later
analysis.
The CoreSight addresses the requirement for a multi-core debug and trace
solution with high bandwidth for whole systems beyond the core, including trace and
monitor of the system bus.
The CoreSight provides:
debug and trace visibility of whole systems
cross triggering support between SoC subsystems
higher data compression than previous solutions
multi-source trace in a single stream
standard Programmer’s Models for standard tool support
open interfaces for third party cores
low pin count
low silicon overhead.
This section describes some of the fundamental features of CoreSight Technology that enable
you to address the issues and challenges of debugging complex SoCs. It contains the
following sections:
Debug access
You gain debug access in CoreSight systems through the Debug Access Port (DAP) that
provides:
real-time access to physical memory without halting the core and without any target
resident code
debug control and access to all status registers
The same mechanism provides fast access for downloading code at the start of the
debug session. This is faster than the traditional JTAG mechanism that uses the ARM
core to write data to memory.
Cross Triggering
The Embedded Cross Trigger (ECT), comprising of the Cross Trigger Interface (CTI)
and Cross Trigger Matrix (CTM), provides a standard interconnect mechanism to pass
debug or profiling events around the SoC.
The ECT provides you with a standard mechanism to connect different signal types. A set of
standard triggers for cores and Embedded Trace Macrocells (ETMs) are predefined and you
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can add triggers for third party cores。
Trace
The CoreSight provides components that support a standard infrastructure for the capture and
transmission of trace data, combination of multiple data streams by
funneling together, and then output of data to a trace port or storing in an on-chip buffer.
The CoreSight enables:
simultaneous trace of asynchronous cores, busses
debug and trace of an AMBA 2 AHB bus
output of trace data to:
a trace port that can run at an independent frequency
an embedded trace buffer for on-chip storage of trace RAM
support for third party cores to enable debug control and standardized Programmer’s Model
and infrastructure..
System APB is connected to debug APB bus via APB MUX to enable software running on
CORTEX-A8 accessing ETM, CTI and DBG inside CORTEX-A8 and CoreSight Components
in CSSYS. Note that Coprocessor read and write instruction can only access part of ETM, CTI
and DBG registers in CORTEX-A8.
4.2 Clock and Reset
VC0882 CLKRST Module provides the following features:
Supports 1 oscillator (or crystal): 12/13/24/26 MHz XCLK
Embeds 6 high performance, low power TCI PLLs
Divided reference frequency range
146KHz - 1.3GHz
/1 output frequency range
240MHz - 1.3GHz
Reference divider values
1-64
Feedback divider values
1-4096
Output divider values
1, 2-8 (even only)
/1 output multiples of div. reference
1-4096
Output duty cycle (nom, tol)
50%,+/-5% (/1 output), +/-2% (others)
Period jitter (P-P) (max)
+/-2.5% output cycle
Input-to-output jitter (P-P) (max)
n/a
(jitter numbers are worst-case estimates with supply and substrate noise levels below
-- actual results will be better)
Power dissipation (nom)
3mA @ 600MHz (/1 output)
Reset pulse width (min)
5µs
Reset /1 output frequency range
20MHz - 200MHz
Lock time (min allowed)
500 div. reference cycles
(actual lock time will be much smaller)
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Freq. overshoot (full-~/half-~) (max)
Area (including isolation) (max)
VC0882 Data Book
40%/50%
~0.11mm2
Number of PLL supply pkg. pins
1 VDDA, 1 VSSA (preferred)
Low freq. supply noise est. (P-P) (max) 10% VDDA
Low freq. sub. noise est. (P-P) (max)
10% VDDA
Reference input jitter (long-term, P-P) (max) 2% div. reference cycle
Reference H/L pulse width (min)
420ps
Process technology
TSMC CLN65LP 0.065µm
Supply voltage (VDD, VDDA) (nom, tol) 1.2V, +/-10%
Junction temperature (nom, min, max)
70C, -40C, 125C
Includes configurable clock dividers to produce desired clock frequencies
Implements clock gating technology to save power
Inserts clock multiplexers to enhance flexibility
Supports system clock switching between XCLK and all 6 PLLs
Integrates pmu hardware reset, watchdog reset, global software reset and each module’s
individual software reset
4.3 Interrupt controller
VC0882 adopts two-level interrupt architecture. The second-level interrupt controllers (SLIC
Sub-module) are embedded in each module. It collects the module’s local interrupts, filters with
its mask settings, and then if no mask settings generates a high-level interrupt report to the
first-level interrupt controller (FLIC Module).
SLIC Sub-module provides the following features:
Embedded in each module
Collects this module’s local interrupts, which are sent to SLIC Module in high level pulses
of one module clock cycle.
Holds 1’b1 at some bits in XXX_SRCPND Register, which indicates these kinds of local
interrupts have happened, until software writes 1’b1 to clear these bits
Filters XXX_SRCPND Register with XXX_INTMASK Register, which allows software to
mask unconcerned local interrupts
Provides XXX_SETMASK and XXX_UNMASK Registers, so as to support atom
manipulation for XXX_INTMASK Register
If any 1’b1 in XXX_SRCPND Register has not been masked, generates and holds a
high-level interrupt report to FLIC Module
FLIC Module provides the following features:
Supports up to 64 interrupt sources
Supports both IRQ and FIQ to ARM
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Specifies the mode of each interrupt source by INTC_INTMODE Register, where none or
only one interrupt source may be specified to FIQ Mode
Separates the interrupt source of FIQ Mode from the others of IRQ Mode, which doesn’t
affect INTC_INTPND and INTC_INTOFFSET Registers
Interrupt sources of both IRQ and FIQ Mode can be masked by INTC_INTMASK Register
Provides INTC_SETMASK and INTC_UNMASK Registers, so as to support atom
manipulation for INTC_INTMASK Register
Performs priority arbitration for interrupt sources of IRQ Mode as follows:
First come first serve
If arrive simultaneously, grant the interrupt source having the highest priority, which is
from 0(H) to 15(L) and configured in INTC_PRIORITY Registers
Furthermore, if multiple interrupt sources all have the same highest priority, grant the
one having the minimum port number.
Saves the result of priority arbitration in INTC_INTPND and INTC_INTOFFSET Registers,
and the value of INTC_INTOFFSET register accords with INTC_INTPND register.
Support software interrupt.
If any 1’b1 in INTC_INTPND Register has not been masked, generates and holds a
low-level interrupt report to ARM.
Generally speaking, ARM has 7 processor modes. Three of them are User Mode, IRQ Mode
and FIQ Mode. ARM executes most tasks in User Mode. If the pin IRQn of ARM has been
pulled down to low level, ARM enters IRQ Mode and usually this mode is used to process
some common interrupts. If the pin FIQn of ARM has been pulled down to low level, ARM
enters FIQ Mode. Since this mode has been optimized to have fast response speed, it is
usually used to process some urgent interrupts.
4.4 Timer
VC0882 timer module supports 8 timers: 3 general-purpose timers, 4 dual timers and 1
watchdog timer. The timers operate from a unique 24MHz timer clock but with separate control
signals for each timer, which give flexible controls.
. The VC0882 timer module has the following features:
3 general-purpose timers, 4 dual timers and 1 watchdog timer
Programmable timer period and timer operation mode
Individual interrupt for each timer
Unique 24MHz clock for all timers
3 operation modes for general-purpose timers:
One-time operation (timer runs for one period then resets and stops)
Periodical operation (timer interrupts and automatically resets every time it reaches
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VC0882 Data Book
maximum value)
Continuous operation (timer interrupts every time it reaches a specific value, then it
continues to count)
3 operation modes for dual timers:
One-time operation (timer runs for one period then resets and stops)
Periodic operation (timer interrupts and automatically resets every time it reaches
maximum value)
Continuous operation (timer interrupts every time it reaches a specific value, then it
continues to count)
watchdog timer is able to used as a general-purpose timer
Capability of each timer is shown below:
Table 4-1 Timer Capability list
Capability
Timer0
32-bit general-purpose timer
X
Dual 32-bit timer (chained)
64-bit general-purpose timer
Timer1
Timer2
Timer3
Timer4
Timer5
Timer6
X
Timer7
X
X
X
X
X
X
Watchdog timer
X
Basically, timer module consists of a register sub-module, 3 general-purpose timers, 4 dual
timers and a watchdog sub-module. The timer register sub-module, Timer_reg, is in charge of
getting timer options through APB interface and sending the setup to the timers. The
general-purpose timer sub-modules will work according to the setup from the register
sub-module and generate interrupts to system interrupt controller. Watchdog sub-module is
able to act as a watchdog timer for the system as well as a general-purpose timer. It is able to
generate a warm reset after an interrupt without CPU clearance.
4.5 EFUSE
The EFUSE module is used to manage electrical fuse IP: program the electrical fuse IP, read
programmed values after programming, read all values before programming (named “unload”
process) and control this IP in power down or standby mode when it’s inactive.
There are two kinds of ways for above processes( PROGRAM, READ, UNLOAD,
POWER_DOWN and STANDBY)：
by APB bus in normal mode
by PAD on ATE(automatic test equipment) in test mode
The EFUSE IP is organized as 128-bit by 8 one-time programmable electrical fuses with
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random access interface. The EFUSE Module can manage this IP by APB bus in normal work
or by PAD inputs in test mode. The electrical fuse is a type of non-volatile memory fabricated in
standard COMS logic progress. The electrical fuse macro is widely used in chip ID, memory
redundancy, security code, configuration setting, and feature selection, etc.
There are two kinds of ways to manage the electrical fuse IP. This is selected by TEST pin:
by APB bus in normal mode
by PAD on ATE in test mode
Software can control the electrical IP into power down or standby mode if the IP is inactive
(No PROGRAM, READ and UNLOAD).
Software can program 1bit at a time according to configured address.
Software can read 1~8bytes at a time according to configured address and configured
read byte length.
The following describes features of EFUSE IP:
Embedded power-switch
Provide power-down and standby mode
Fully compatible with standard CMOS logic process
Asynchronous signal interface
Macro requiring both standard-Vt and high-Vt GO1 (Core device) transistors
Macro also requiring GO2 (I/O device) transistors
Programming condition:
VQPS: 2.5+/-10%, VDD: 1.2V+/-10%
Temp: 1250C~-400C
Program time: 4us~6us and typical program time is 5us
Read condition:
VQPS:2.5V+/-10% or 0V
VDD=1.2V+/-10%
Temp: 1250C~-400C
Provided macro for ESD protection, MUST be used in-pair with this electrical fuse IP
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Chapter 05
Memory
SubSystem
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5 Memory Subsytem
5.1 Interconnection
INTERCONNECT is based on ARM AMBA3 (Advanced Microcontroller Bus Architecture) AXI
(Advanced eXtensible Interface) Bus Protocol and connects all the AXI Master Modules and
AXI Slave Modules of this chip together. Its main tasks are (1) decoding memory addresses
according to the predefined memory mapping table, (2) routing Read Address, Write Address
and Write Data from AXI Masters to AXI Slaves, as well as routing Read Data and Write
Response from AXI Slaves to AXI Masters, so as to realize the chip-level information
interchange, (3) arbitrating if competition exists when routing information from multiple sources
to a unique destination.
Be in compliance with ARM AMBA3 AXI Bus Protocol.
Construct the INTERCONNECT with Synopsys DesignWare Fabric Components, such as
DW_axi, DW_axi_x2x, and DW_axi_hmx.
DW_axi is instantiated as MARB (Main ARBiter) and SARB (Sub ARBiter). MARB is used
to do the top-level integration, while SARB is used to do the module-level or
subsystem-level integration. MARB and SARB make up the backbone of this
INTERCONNECT.
Read Data Interleaving is supported.
Write Data Interleaving is fixed to a depth of 1.
Exclusive Access and Locked Access are not used, so that ARLOCK[1:0] and
AWLOCK[1:0] are fixed to 2’b00.
Cache Options are not used, so that ARCACHE[3:0] and AWCACHE[3:0] are fixed to
4’b0000.
Protection Options are not used, so that ARPROT[2:0] and AWPROT[2:0] are fixed to
3’b000.
Low-Power Interface is not used.
Read Address Channel and Write Address Channel implement a user-defined arbitration
strategy, called Class Based Round Robin + Pulse Width Modulation Arbitration Strategy
(CBRR+PWM for short).
Read Data Channel and Write Response Channel implement the general Round Robin
Arbitration Strategy.
Write Data Channel involves no arbitration because Write Data Interleaving has been fixed
to a depth of 1.
Extend Read Address Channel and Write Address Channel with 2-bit sideband signals
respectively, i.e. ARSIDEBAND[1:0] and AWSIDEBAND[1:0], which are then used by the
CBRR+PWM Arbitration Strategy.
Place performance monitors for AXIBUS, ARBITER and DDRC.
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5.2 DDR Controller
DDRC is mainly responsible for the following functions:
As an AXI slave, receiving AXI transaction from AXI master (memory arbiter).
The received AXI command may be split into two commands according to command split
rule. Each AXI command need to be partitioned into one or multiple DDR bursts before it is
queued.
According to reorder rule, rescheduling the DDR commands for improving DDR efficiency.
According to DDR protocol, write/read data to/from external DDR device.
The DDRC module supports the following features:
Compatible with JEDEC standard LPDDR1, DDR2, DDR3
Data rates up to 800 Mb/s (400 MHz) in 65LP
Compatible with the AMBA 3 AXI protocol
Compatible with the AMBA 3 APB protocol
Supported AXI burst types: incremental and wrap
AXI interface clock asynchronous to the DDRC core clock
Support the following bus configurations:
AXI Data Bus width : Valid DDR Data Bus width = 2 : 1 (normal mode)
AXI Data Bus width : Valid DDR Data Bus width = 4 : 1 (half data path valid mode: for
example, that AXI Data Bus width is 64 bits, DDR Data Bus width is 32, but only 16 bits
of DDR Data Bus are valid ,other 16 bits are not used)
Configurable AXI data bus widths of 64 bits
Corresponds to DDR data bus widths of 32 bits ,respectively
Corresponds to AXI burst size of 4,8,16 bytes, respectively
Register programmable timing parameters support DDR2/DDR3/LPDDR1 comp- onents
from various DRAM vendors
Register programmable DDR burst length of 2,4 or 8
Support LPDDR1/DDR2 read/write command interrupt access
Advanced features such ODT, ZQ Calibration and additive latency
Support for two CSs (chip select) with shared clock pins, command pins, address pins and
data pins
Support for DDR device density ranging from 64Mbit to 8Gbit
Support 16 bit LPDDR1/DDR2/DDR3 device and 32bit LPDDR1 device
Support 8 bit DDR2/DDR3 device
Advanced command re-ordering and scheduling to maximize bus utilization
Register programmable anti-starvation mechanisms according to SideBand Info- rmation
Support single Refresh and Speculative Refresh
Register programmable priority with up to four priorities according to SideBand Information
Register programmable address mapping, including mapping based on row or mapping
based on bank
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Supports autonomous DDR power down entry and exit based on programmable idle
periods
Support for self refresh entry on software command and automatic exit on DRAM access
command arrival
Automated Read DQS recognition with DDR PHY and Automated Dynamic DQS Drift
Compensation
Built-in DQS Gate Training with DDR PHY
Support DDR3 DLL-off Mode
Support LPDDR1 Deep Power Down Mode
5.3 Sram Controller
SRAMC module is the interface between AXI bus and SRAM. It works as an AXI slave as well
as a SRAM controller. It receives AXI transactions from AXI bus and transforms them into
SRAM control signals. When data come back from SRAM, SRAMC put them into AXI data
channel according to AXI protocol.
The core logic of SRAMC can work at a MAX clock frequency of 200MHz;
“Rresp” and “Bresp” always be “OKEY”, it means that AXI interconnect must check the
correctness of the address;
AXI interface and core logic are asynchronous;
AXI data bus width is fixed as 64 bits;
SRAM data bus width is fixed as 16 bits;
SRAM adderss width is fixed as 14 bits;
AMBA AXI protocol related features:
Supports “incrementing” and “wrapping” burst type;
Supports burst length 1 to 16;
Supports narrow transfer;
Supports unaligned data transfers;
Supports multiple transaction ID;
Transactions complete in the order they were received even if they have different
transaction ID;
“fixed” burst type is not supported;
Locked transfer is not supported;
Exclusive access is not supported;
Write data interleaving is not supported;
Low power interface is not supported;
SRAM side
Supports byte write enable;
Supports delayed read data using “rdata_valid” input signal;
Can hold write command using “wen” signal;
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Can hold read command using “ren” signal;
5.4 Rom Controller
ROMC module is the interface between AXI bus and ROM. It works as an AXI slave as well as
a ROM controller. It receives AXI transactions from AXI bus and transforms them into ROM
control signals. When data come back from ROM, ROMC put them into AXI data channel
according to AXI protocol.
The core logic of ROMC can work at a MAX clock frequency of 200MHz;
“Rresp” always be “OKEY”;
AXI interface and core logic are asynchronous;
Data bus width is 64 bits;
Rom address width is 13 bits;
Data bus width of AXI and memory must be the same;
AMBA AXI protocol related feature;
Accepts only read transactions;
Supports “incremental” and “wrap” transaction type;
Supports burst length 1 to 16;
Supports narrow transfer;
Supports unaligned data transfers;
Supports multiple transaction ID;
Transactions complete in the order they were received even if they have different
transaction ID;
“fixed” burst type is not supported;
Locked transfer is not supported;
Exclusive access is not supported;
Write data interleaving is not supported;
Low power interface is not supported;
Supports only one ROM;
5.5 DMAC (Direct Memory Access Controller)
The VC0882 DMAC is a high-performance DMA controller. The DMAC is used to setup a direct
transfer path between memories. The main advantage of DMA is that it can transfer the data
without CPU intervention.
The DMAC supports one channel and only supports software request. You may begin to
transfer memory data when the channel is idle. Software mode means ARM initiates the
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transmission. DMAC will only give out the interrupt to ARM. Channel registers should be well
configured before each transmission.
The VC0882 DMAC has the following features:
Compliance to the AMBA 3.0 Specification---AXI protocol for integration into SoC
implementation.
One DMA channel which can support unidirectional transfer for software request.
Memory-to-memory transfer. Supported memories are DDR SDRAM, internal SRAM,
external dual port SRAM and external SRAM-like Devices such as Nor Flash or Ethernet
Controller.
Only support linear transfer.
APB slave DMA programming interface. Software program the DMAC by writing to the
DMA control registers over the APB slave interface.
One AXI bus master for transferring data. Use these interfaces to transfer data when a
DMA request goes active.
Increment addressing for source and destination.
Internal 32×64bits FIFO (one instance of a sync FIFO).
Support programming max burst length.
The source address and destination address for DMA request are byte aligned.
Transfer length is byte-aligned.
Transfer length is 8~16M bytes.
Only little-endian support.
Support LLI Mode. LLI address is 8byte-aligned (double word aligned) and may be stored
in DDR SDRAM, internal SRAM, external dual port SRAM and external SRAM-like
Devices such as Nor Flash.
Indicate a transmission has completed by interrupt.
Software can terminate transfer by configuring register, a terminate interrupt is used to
indicate the termination completed.
Indicate an error has occurred by an error interrupt. If error occurs, the transmission will
not be stopped until all outstanding AXI transfer finished.
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Chapter 06
Video
SubSystem
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6 Video SubSystem
6.1 Video Encoder
Supported standards and tools
The encoder supported standards, profiles and levels are presented in Table 6-1.
Table 6-1 encoder supported standards, profiles and levels
Standard
Profiles
Levels
Notes
H.264
Baseline Profile
Levels 1-3.1
Image size up to 1280x1024.
B frame not supported.
MPEG-4
Simple Profile
Levels 0-5
Main Profile
Level 4
Only simple profile tools are supported.
Image size up to 1280x1024.
H.263
Profile 0
Levels 10-70
JPEG
Baseline
Image size up to 1280x1024.
Time code extensions not supported.
Image size up to 4672x3504.
The encoder supported H.264 video tools are shown in Table 6-2.
Table 6-2 encoder supported H.264 tools
Standard
Tools
Encoder support
H.264
Slices
I-Slice and P-Slice.
Entropy encoding
CAVLC
Basic
Constrained intra prediction.
Maximum MV range +-16 pixels.
MV accuracy 1/4 pixels.
All block sizes from 4x4 to 16x16 supported.
All intra modes supported.
Number of reference frames
1
Maximum number of slice groups
1
The encoder supported MPEG-4 video tools are shown in Table 6-3.
Table 6-3 encoder supported MPEG-4 tools
Standard
Tools
Encoder support
MPEG-4
Basic
I-VOP and P-VOP.
Maximum MV range +-16 pixels.
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MV accuracy 1/2 pixels.
1 or 4 MV per macro block.
DC prediction.
Error resilience
Video packets.
Data partitioning.
Reversible VLC.
Number of reference frames
1
Quantization
Method 2
Number of visual objects
1
Short video header
Yes
The encoder supported H.263 video tools are shown in Table 6-4.
Table 6-4 encoder supported H.263 tools
Standard
Tools
Encoder support
H.263
Basic
I-VOP and P-VOP.
Maximum MV range +-16 pixels.
MV accuracy 1/2 pixels.
1 MV per macro block.
Error resilience
GOB
Number of reference frames
1
Encoding Features
The features of the encoder for each supported standard are different. There are shown as
followed.
Table 6-5 H.264 features
Standard
Feature
Encoder support
H.264
Input data format
YCbCr 4:2:0 planar or semi-planar.
YCbCr and CbYCrY 4:2:2 interleaved.
Output data format
H.264 byte or NAL unit stream.
Supported image size
96x96 to 1280x1024.
Step size 4 pixels.
Maximum frame rate
25 fps at 720x576 for PAL.
30 fps at 720x480 for NSTC.
30 fps at 1280x720.
Note.
The encoder can support 1280x1024 just at 15 fps.
Maximum bit rate
10 Mbps.
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Notes
1) Internally encoder handles images only in 4:2:0 formats.
2) Actual maximum frame rate will depend on the logic clock frequency and the system bus
performance. The given figure 30 fps at 1280x720 requires logic clock frequency of 271
MHz. 15 fps at 1280x1024 requires logic clock frequency of 193 MHz.
Table 6-6 MPEG-4/H.263 features
Standard
Feature
Encoder support
MPEG-4
H.263
Input data format
YCbCr 4:2:0 planar or semi-planar.
YCbCr and CbYCrY 4:2:2 interleaved.
Output data format
MPEG-4/H.263 elementary video stream.
Supported image size
96x96 to 1280x1024.
Step size 4 pixels.
Maximum frame rate
25 fps at 720x576 for PAL.
30 fps at 720x480 for NSTC.
30 fps at 1280x720.
Note.
The encoder can support 1280x1024 just at 15 fps.
Maximum bit rate
10 Mbps.
Notes
1) Internally encoder handles images only in 4:2:0 formats.
2) Actual maximum frame rate will depend on the logic clock frequency and the system bus
performance. The given figure 30 fps at 1280x720 requires logic clock frequency of 215
MHz. 15 fps at 1280x1024 requires logic clock frequency of 193 MHz.
Table 6-7 JPEG features
Standard
Feature
Encoder support
JPEG
Input data format
YCbCr 4:2:0 planar or semi-planar.
YCbCr and CbYCrY 4:2:2 interleaved.
Output data format
JFIF file format 1.02.
Non-progressive JPEG.
Supported image size
80x16 to 4672x3504.
Step size 4 pixels.
Maximum bit rate
Up to 28 million pixels per second.
Thumbnail encoding
JPEG compressed thumbnails supported.
Pre-processing features
Pre-processing is pipelined with encoder and it can be used only with encoder.
Pre-processing features are presented in Table below.
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Table 6-8 pre-processing features
Feature
Encoder support
Color space conversion
YCbYCr or CbYCrY 4:2:2 Interleaved or semi-planar 4:2:0 to YCbCr
4:2:0.
Cropping
JPEG-from 4672x4672 to any supported encoding size.
Video-from 1920x1920 to any supported encoding size.
Rotation
90 or 270 degrees.
Video stabilization features
Digital video stabilization detects and compensates undesired jitter effect on the video (For
example, images from camera). Stabilization operates with the two input picture buffers
simultaneously.
Video stabilization can be used pipelined with video encoding or in standalone mode when
video encoding is disabled.
Video stabilization features are explained as followed.
Table 6-9 video stabilization features
Feature
Encoder support
Maximum stabilization move in pixels
for two sequential input video pictures.
+-16 pixels.
Adaptive motion compensation filter.
From 6 to 40 sequential video pictures noticed in
unwanted and wanted movement separation.
Offset around stabilized picture.
Minimum 8 pixels in standalone mode.
Minimum 16 pixels when pipelined with video encoder.
Recommended 64 pixels.
Maximum not limited.
Connectivity features
The encoder supports AXI and APB bus interfaces, and different bus width from master
interface and slave interface. And restrict maximum burst length on bus interface, and also the
endian modes can be separately set for input and output data.
The encoder supports connectivity features presented below.
Table 6-10 connectivity features
Feature
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APB slave interface
Yes. 32-bit bus width.
AXI master interface
Yes. 64-bit bus width.
Restricting maximum issued AXI burst length
Yes, to any value between from 1 to 16.
Interrupt method
Polling or level based interrupting.
32-bit little endian
Yes, byte order 3-2-1-0.
32-bit big endian
Yes, byte order 0-1-2-3.
64-bit little endian
Yes, byte order 7-6-5-4-3-2-1-0.
64-bit big endian
Yes, byte order 0-1-2-3-4-5-6-7.
Maxed 32-bit little endian in a 64-bit bus
Yes, byte order 3-2-1-0-7-6-5-4.
Maxed 32-bit big endian in a 64-bit bus
Yes, btye order 4-5-6-7-0-1-2-3.
6.2 Video Decoder
Video standard and profiles
Main standards and profiles description of decoder supported.
Table 6-11 profile and level
Standard
Decoder support
H.264 profile and level
Baseline Profile, levels 1 - 4.1
Main Profile, levels 1 - 4.1
High Profile, levels 1 - 4.1
Support I，P，B frame
SVC profile and level
Scalable Baseline Profile, base layer only
Scalable High Profile, base layer only
Support I, P, B frame.
MPEG-4 visual profile and level
Simple Profile, levels 0 – 6
Advanced Simple Profile, level 0-5
Support I, P, B frame
MPEG-2 profile and level
Main Profile, low, medium and high levels
Support I, P, B frame
MPEG-1 profile and level
Main Profile, low, medium and high levels
Support I, P, B frame
H.263 profile and level
Profile 0, levels 10-70. Image size up to
720x576.
Support I，P frame.
Sorenson Spark profile and level
Bitstream version 0 and 1
VC-1 profile and level
Simple Profile, low, medium and high levels
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Main Profile, low, medium and high levels
Advance Profile, levels 0-3
Support I, P, B frame
JPEG profile and level
Baseline interleaved
RV profile and level
RV8
RV9
RV10
Support I, P, B frame
VP6 profile and level
VP6.0 (Simple Profile)
VP6.1
VP6.2 (Advanced Profile)
DivX profile and level
DivX Home Theater Profile Quanlified
DivX3
DivX4
DivX5
DivX6
Some special function description:
Table 6-12 special function
Standard
Tool
Decoder support
H.263
Time code extensions
Not supported
H.264
Slice groups (FMO)
If more than one slice group used, SW performs
entropy decoding
H.264
Arbitrary slice order
Supported, SW performs entropy decoding
H.264
Redundant slices
Supported, but not utilized; redundant slices are
skipped by SW
H.264
Image cropping
Not performed by the decoder, cropping
parameters are returned to the application
SVC
Enhancement layers
Not supported
MPEG-4
Data partitioning
Supported, SW performs entropy decoding
MPEG-4
Global motion
compensation
Not supported
VC-1
Multi-resolution
Supported, upscaling will be performed by the
post- processor
VC-1
Range mapping
Supported, range mapping will be performed by
the post-processor
JPEG
Non-interleaved data order
Not supported
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Decoder features
The features of the decoder for each supported standard are shown in following tables.
Table 6-13 H.264/SVC base layer features
Feature
Decoder support
Input data format
H.264 byte or NAL unit stream / SVC stream
Decoding scheme
Frame by frame (or field by field)
Slice by slice
Output data format
YCbCr 4:2:0 semi-planar
Supported image size
48 x 48 to 1920 x 1088
Step size 16 pixels
Maximum frame rate
30 fps at 1920 x 1088
Maximum bit rate
As specified by H.264 HP level 4.1
Error detection and concealment
Supported
Table 6-14 MPEG-4/H.263/Sorenson Spark features
Feature
Decoder support
Input data format
MPEG-4 / H.263 / Sorenson Spark elementary
video stream
Decoding scheme
Frame by frame (or field by field)
Video packet by video packet
Output data format
YCbCr 4:2:0 semi-planar
Supported image size
48 x 48 to 1920 x 1088 (MPEG-4, Sorenson
Spark)
48 x 48 to 720 x 576 (H.263)
Step size 16 pixels
Maximum frame rate
30 fps at 1920 x 1088
Maximum bit rate
As specified by MPEG-4 ASP level 5
Error detection and concealment
Supported
Table 6-15 MPEG-2/MPEG-1 features
Feature
Decoder support
Input data format
MPEG-2 / MPEG-1 elementary video stream
Decoding scheme
Frame by frame (or field by field)
Video packet by video packet
Output data format
YCbCr 4:2:0 semi-planar
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Supported image size
48 x 48 to 1920 x 1088
Step size 16 pixels
Maximum frame rate
30 fps at 1920 x 1088
Maximum bit rate
As specified by MPEG-2 MP high level
Error detection and concealment
Supported
Table 6-16 JPEG features
Feature
Decoder support
Input data format
JFIF file format 1.02
YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4
sampling formats
Decoding scheme
Input: buffer by buffer, from 5kB to 8MB at a
time
Output: from 1 MB row to 16 Mpixels at a time
Output data format
YCbCr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4
semi-planar
Supported image size
48 x 48 to 8176 x 8176 (66.8 Mpixels)
Step size 8 pixels
Maximum data rate
Up to 76 million pixels per second
Thumbnail decoding
JPEG compressed thumbnails supported
Error detection
Supported
Table 6-17 VC-1 features
Feature
Decoder support
Input data format
VC-1 stream
Decoding scheme
Frame by frame (or field by field)
Slice by slice
Output data format
YCbCr 4:2:0 semi-planar
Supported image size
48 x 48 to 1920 x 1088
Step size 16 pixels
Maximum frame rate
30 fps at 1920 x 1088
Maximum bit rate
As specified by VC-1 AP level 3
Error detection and concealment
Supported
Table 6-18 RV features
Feature
Decoder support
Input data format
RV8, RV9 or RV10 stream
Decoding scheme
Frame by frame
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Slice by slice
Output data format
YCbCr 4:2:0 semi-planar
Supported image size
48 x 48 to 1920 x 1088
Step size 16 pixels
Maximum frame rate
30 fps at 1920 x 1088
Maximum bit rate
As specified by RV specification
Error detection and concealment
Supported
Table 6-19 VP6 features
Feature
Decoder support
Input data format
VP6.0 / VP6.1 / VP6.2 stream
Decoding scheme
Frame by frame
Output data format
YCbCr 4:2:0 semi-planar
Supported image size
48 x 48 to 1920 x 1088
Step size 16 pixels
Maximum frame rate
30 fps at 1920 x 1088
Maximum bit rate
As specified by VP6 specification
Error detection and concealment
Supported
Table 6-20 DivX feature
Feature
Decoder support
Input data format
Divx3, 4, 5 or 6 stream
Decoding scheme
Frame by frame
Video packet by video packet
Output data format
YCbCr 4:2:0 semi-planar
Supported image size
48 x 48 to 1920 x 1088
Step size 16 pixels
Maximum frame rate
30 fps at 1920 x 1088
Maximum bit rate
As specified by the DivX specification
Error detection and concealment
Supported
Post-processing features
The post-processor (PP) features are described in following table. It is possible to run the
post-processor combined with the decoder, or as a stand-alone IP block, when it can process
image data from any external source.
Using combined mode reduces bus bandwidth, as PP can read its input data directly from the
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decoder output without accessing external memory.
The post-processor output image can be alpha blended with two rectangular areas. If alpha
blending is used in combined mode, the currently decoded image will be set as the
background image.
Alpha blending can be used for creating transparent menus, subtitles and logos on top of the
video playback. These overlay regions must be in the same color space, YCbCr or RGB, as
the target format of the post-processor output image. If the two areas for alpha blending
overlap, the second area overrides the first (the first area content is discarded). Alpha blending
increases the bus load.
Table 6-21 post-processor features
Feature
Post-processor support
Input data format
Any format generated by the decoder in
combined mode
YCbCr 4:2:0 semi-planar
YCbCr 4:2:0 planar
YCbYCr 4:2:2
YCrYCb 4:2:2
CbYCrY 4:2:2
CrYCbY 4:2:2
Post-processing scheme
Frame by frame. Post-processor handles the
image macroblock by macroblock, also in
standalone mode.
Input image source
Internal source (combined mode)
External source (standalone mode)
Output data format
YCbCr 4:2:0 semi-planar
YCbYCr 4:2:2
YCrYCb 4:2:2
CbYCrY 4:2:2
CrYCbY 4:2:2
Fully configurable ARGB channel lengths and
locations inside 32 bits, e.g. ARGB 32-bit
(8-8-8-8), RGB 16-bit (2-6-5), ARGB 16-bit
(4-4-4-4)
Input image size (combined mode)
48 x 48 to 8176 x 8176 (66.8 Mpixels)
Step size 16 pixels
Input image size (stand-alone mode)
Width from 48 to 8176
Height from 48 to 8176
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Maximum size limited to 16.7 Mpixels
Step size 16 pixels
Output image size
16 x 16 to 1920 x 1088
Horizontal step size 8
Vertical step size 2
Image up-scaling
Bicubic polynomial interpolation with a four-tap
horizontal kernel and a two-tap vertical kernel
Arbitrary, non-integer scaling ratio separately
for both dimensions
Maximum output width is 3x the input width
(within the maximum output image size limit)
Maximum output height is 3x the input height –
2 pixels (within the maximum output image size
limit)
Image down-scaling
Proprietary averaging filter
Arbitrary, non-integer scaling ratio separately
for both dimensions
Unlimited down-scaling ratio (e.g. from
16Mpixel to QVGA)
YCbCr to RGB color conversion
BT.601-5 compliant
BT.709 compliant
User definable conversion coefficient
Dithering
2x2 ordered spatial dithering for 4, 5 and 6 bit
RGB channel precision
Programmable alpha channel
Constant eight bit value can be set to the alpha
channel of the 24-bit RGB output data to control
the transparency of the output picture. The
resulting 32-bit ARGB data can be used as
input data for later alpha blending.
Alpha blending
Output image can be alpha blended with two
rectangular areas. YCbCr semi-planar 4:2:0 PP
output format is not supported when performing
alpha blending.
The supported overlay input formats are
following:
1.8 bit alpha value + YCbCr 4:4:4, big endian
channel order being A-Y-Cb-Cr, 8 bits each
2. 8 bit alpha value + 24 bit RGB, big endian
channel order being A-R-G-B, 8 bits each
Deinterlacing
Conditional
spatial
deinterlace
filtering.
Supports only YCbCr 4:2:0 input format.
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RGB image contrast adjustment
Segmented linear
RGB image brightness adjustment
Linear
RGB image color saturation adjustment
Linear
De-blocking filter for MPEG-4 simple profile
/H263
Using a modified H.264 in-loop filter as a
post-processing filter. Filtering has to be
performed in combined mode.
Image cropping / digital zoom
User definable start position, height and width.
Can be used with scaling to perform digital
zoom. Usable only for JPEG or stand-alone
mode.
Picture in picture
Output image can be written to any location
inside video memory. Up to 1920 x 1088 sized
displays supported.
Output image masking
Output image writing can be prevented on two
rectangular areas in the image. The masking
feature is exclusive with alpha blending;
however it is possible to have one masking area
and one blending area.
Image rotation
Rotation 90, 180 or 270 degrees
Horizontal
Vertical
Connectivity features
The decoder and post-processor support the connectivity features presented in following table.
The usage of these features is described in more detail. Note that the endian modes can be
separately set for input and output data, but they have no effect on RGB output data, as RGB
channel order and their lengths are controlled separately.
Table 6-22 interface features
Feature
Decoder support
AXI master access
Yes,64-bit AXI 1.0
APB slave access
Yes, 32-bit AMBA 3 APB 1.0
Memory addressing
64-bit/32-bit
addressing
Restricting the maximum issued AXI burst
length
Yes, to any value between 1-16
Interrupt method
Polling or level based interrupting
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32-bit little endian
Yes, byte order 3-2-1-0
32-bit big endian
Yes, byte order 0-1-2-3
64-bit little endian
Yes, byte order 7-6-5-4-3-2-1-0
64-bit big endian
Yes, byte order 0-1-2-3-4-5-6-7
Mixed 32-bit little endian in a 64-bit bus
Yes, byte order 3-2-1-0-7-6-5-4
Mixed 32-bit big endian in a 64-bit bus
Yes, byte order 4-5-6-7-0-1-2-3
6.3 Camera Interface
The camera interface (CIF) captures the dynamic video data stream or static image from
camera sensor, and store the input into the memory after post-processing.
Only support master type sensor module
Only support 8-bit parallel data output from sensor
Supported two camera sensors(only one works at the same time)
Supported max sensor resolution: 4096x4096
Supported max Pixel clock:100Mhz
Supported max output image size (to memory): 4096x4096
Support parallel interface for SYNC mode or ITU-R BT656 mode
Support differential serial interface for MIPI CSI standard (support two data lanes)
Max bandwidth of MIPI CSI interface: 2Gbps
Support YCbCr422-format data/RAW image data/JPEG compressed data/RGB data
(Bypass post-processing for RAW data/JPEG data/RGB data)
Support test pattern for debugging
Support cropping window of input image
Support two post-processing paths for capture and display
Support up-scaling for capture path/preview path
Max width of input image in capture path for up-scaling: 4096
Max width of input image in preview path for up-scaling: 2048
Max width of output image for up-scaling: 4096
Max x2 for X direction
Max x2 for y direction
Input format: YCbCr422
Output format: YCbCr422
Support down-scaling for capture path/preview path
Max width of input image for down-scaling: 4096
Max width of output image for down-scaling: 4096
Max 1/128 for X direction
Max 1/128 for y direction
Input format: YCbCr422
Output format: YCbCr422
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For capture path
If scaling ratio for Y direction is in [1/128, 1/4], output width must not be more than
2048
For preview path
If scaling ratio for Y direction is in (1/4, 1/2], output width must not be more than
2048
If scaling ratio for Y direction is in [1/128, 1/4], output width must not be more than
1024
Support the following special effect
Sepia
Special color
Negative
Mono color
Four block
Grid color
Embossing
Silhouette
Pencil Draw
Binary Effect
Support 3-color OSD operation with size 480x24
Support frame drop operation
Support storage memory organization as YUV422 interleaved/YUV420 semi-planar format
for input from sensor with YCbCr422/ ITU-R BT656 format
Support slice mode and frame mode
Only support little-endian storage organization
Support direct storage for input from sensor with RAW data/JPEG data/RGB data
Only support frame mode
Only support little-endian storage organization
Capture path support slice mode and frame mode
Preview path only support frame mode
Support auto-focus
Support max width of image for Auto-focus is 4096
Support max 8 rectangle windows for Auto-focus
When using Auto-focus, capture path is disabled for the sake of shared memory
Support memory to memory path
6.4 Face Detection
The hardware design of face detection includes the calculation of integral and LAB (Locally
Assembled Binary), which is composed of follows:
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1) Support maximum sizer image width is 320 pixels, height is 240 pixels, minimum sizer
image width is 24 pixels, and height is 24 pixels and no limitation for original image
size.
2) Only support sizer image luminance format is row by row progressively.
3) Support 64bits AXI master interface.
4) Support 32bits APB slave interface.
5) Calculation of integral (x, y), and store the results to external memory through AXI bus
interface.
6) Using Integral (x, y) results stored in external memory, calculate sum Y for both 3*3 and
2*2 blocks, compare the sum results of nine 3*3 or 2*2 blocks, get an 8-bit LAB, and
then write it back to external memory.
7) Only support LABs image format is row by row progressively.
Actually the face detection include hardware module and software program, some function
implement by software, which is composed as follows:
1) Support designate search window by software.
2) The maximum faces are not limitation in theory. At present in our system the maximum
is 8.
3) Only support the smallest face haves 12x12 pixels resolution between two eyes.
4) About process 5~10 QVGA frames in a second.
5) Support detection of smile faces, but not wink faces.
6) Only report the eyes position.
7) Support the face in profile angle is -20 ~ 20 degrees, pitching angle is -30 ~ 30
degrees.
8) Support detection of black skin faces, actually need enough red pixels could be
detected.
9) Support detection of color eyes and white hair.
10) The average value of luminance in image must surpass 16.
11) Support detection of face with glasses. The mask will decrease accuracy of detection.
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6.5
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LCD interface
LCD（Liquid Crystal Display） interface module is the interface between VC0882 and LCD
panel. LCD interface module provides control signals and pixel data for LCD panels according
to the timing requirements. It can support both DBI（Data Bus Interface） output mode and DPI
（Display Pixel Interface） output mode.
Supports Display Bus Interface (DBI) output mode, compliant to the MIPI(Mobile Industry
Processor Interface) Alliance Display Bus Interface protocol v2.0.
Supports DBI Type A (Clocked E Mode) interface implementation;
Supports DBI Type B interface implementation;
Supports accessing (including writing and reading) in through mode;
Supports dual LCD panels work at different time(DBI & DBI, DBI&DPI)
Supports up to 24 bits per pixel (BPP) ;
Supports up to 24 bits interface with external device;
Supports flexible address mapping;
Supports flexible data mapping;
Supports flexible timing adjustment of control and data signals ;
Display size programmable up to 1080p(1920*1080) with configured interlaced or
progressed mode;
Supports Display Pixel Interface (DPI) output mode, compliant to the MIPI Alliance Display
Pixel Interface protocol V2.0.
Display size programmable up to 1080p(1920 x1080) with configured interlaced or
progressed mode;
Support for 12 & 16&18BPP&24BPP modes for RGB parallel output format (RGB444 ,
RGB565, RGB666,RGB888);
Support programmable pixel clock and asynchronous reset signal ;
Support flexible 3-wire and 4-wire serial interface(including write operation and read
operation of panel registers)
Support parallel dpi interface with up to 24 bits interface;
Support CCIR656 interface (PAL mode and NTSC mode, 8 bit interface only);
Support CCIR601 interface.
Support UPS051&UPS052 interface (8 bit interface only).
Support 24BPP modes for UPS051&UPS052 interface.
Support 16BPP modes for CCIR656 and 24BPP modes for CCIR601.
Programmable 24-bit/18-bit/16-bit/12-bit/8-bit digital output interface
Supports various RGB format (RGB888, RGB565, RGB666, RGB555), YUV format
(YUV444, YUV422) with 1X, 2X, 3X, 4X multiplexed output.
Support Max pixel rate up to 150MHz in DPI mode.
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Note:
1) 1x for 1pixel/1 clock period, 2x for 1pixel/2 clock periods, 3x for 1pixel/3 clock periods,
4x for 1pixel/4 clock periods.
2) Dual panel work at the same time is not support. We can support dual panel in TDM
mode. The dual panel is better to be dual DBI panel. Which panel will be used is selected
by chip select signal separately. The other control and data pins are shared by these two
panels. One DBI panel & one DPI panel can also be implemented, during which case, the
DBI panel make use of the VSYNC blank time of DPI panel to refresh in through mode. It
is hard for software to control the data flow.
3) The interlaced or progressive mode is configured in display engine mode
4) UPS051 represents RGB888 format with 1pixel/3 clock periods.
5) UPS052 represents RGB888 format with 1pixel/4 clock periods, the fourth clock data is
invalid.
6) The Max pixel rate is up to 150MHz in DPI mode. It is also the max pixel clock. For 2X,
the max pixel rate is 75MHz，For 3X, The max pixel rate is 50MHz.
7) When working in interlaced mode, only the odd lines will be refreshed in odd fields and
only even lines will be refreshed in even fields. When working in progressive mode, all the
valid lines in one frame will be refreshed including odd lines and even lines.
6.6 TV Encoder
Support NTSC-M/J/4.43 and PAL- /B/D/G/H/M/N/I/Nc SDTV Composite signal output.
( SECAM system and PAL-60 are not supported in CVBS Encoder)
Table 6-23 Supported NTSC/PAL Video Standards
No
Standards
Field
Number
Active
Scan
Color
Blanking
Line
Rate(Hz)
of Lines
Lines
Type
Sub
pedestal
Frequency
per
per
Carrier
(IRE)
(KHz)
frame
frame
(MHz)
1
NTSC-M
60/1.001
525
480
Interlaced
3.58
7.5
15.734
2
NTSC-J
60/1.001
525
480
Interlaced
3.58
0
15.734
3
NTSC-443
60/1.001
525
480
Interlaced
4.43
7.5
15.734
4
PAL-B/D/G/H/I
50
625
576
Interlaced
4.43
0
15.625
5
PAL-M
60/1.001
525
480
Interlaced
3.58
7.5
15.734
6
PAL-N
50
625
576
Interlaced
4.43
7.5
15.625
7
PAL-Nc
50
625
576
Interlaced
3.58
0
15.625
8
PAL-60
60/1.001
525
480
Interlaced
4.43
7.5
15.734
(Not Supported)
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9
SECAM-D/K/K1/L
50
625
576
Interlaced
(Not Supported)
10
SECAM-B/G
4.25(Db)
VC0882 Data Book
0
15.625
0
15.625
4.40(Dr)
50
625
(Not Supported)
576
Interlaced
4.25(Db)
4.40(Dr)
(Note: the letter, such as M,N,B,D,G,H,I,K, is related with the TV audio sub carrier)
1. Support YPbPr analog signals output on 480i/480p/576i/576p/720p/1080i/1080p systems
Support programmable timing controller for various YPbPr resolutions. The Timing
controller should be coincident with DE(Display Engine) timing controller
Support internal test pattern for CVBS and YPbPr.
Support Sync information from display engine as a timing slave mode.
Support 10-bits video DAC for analog TV signal.
6.7 Display Engine
Display engine can read image pixel data stored in system memory (Frame Buffer, FBUF for
abbreviation in later chapters) and transmit the processed image pixel data to LCD_IF or TV
ENC module for displaying on the LCD panel or TV. The main function of display engine
includes:
Read image pixel data from at most 4 FBUF (at most 4 display layers + HW Cursor +
Background)
Convert the different format of SRC Image pixel data stored in FBUF to uniform format
YUV444
Implement overlay & alpha-blending operation to merge image pixel from different display
layers
Implement post-processing such as up-scaling, brightness/ contrast/ hue/ saturation/
adjustment, gamma, dithering, and etc.
Convert the format of processed pixel data to proper format configured by SW
Output pixel data and sync signals to TV Encoder or LCD_IF.
Implement “capture with frame” function
Features
Support MIPI DPI/MIPI DBI interface standard
Support two DBI panels connection or one DPI panel plus one DBI panel connection (But
the two panels can’t work at the same time.)
Max panel resolution: 1600x1200 for TV/1920x1080 for LCD panel1)
Max pixel rate up to 162MHz
Support BT601 and BT609 color domain
Programmable bits-per-pixel when output to LCD IF: 16/18/24-bpp such as YUV422,
RGB565, RGB666, RGB888, and etc.
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Support programmable multi-cycle output mode: 1/2/3/4 cycles per pixel
Support RGB-format pixel data output and YUV-format pixel data output with synchronous
signals, and ITU-R BT656 format output
Support interlace/non-interlace output
Support 4 display layers plus background and HW cursor
Only support rectangle shape for all the layers
Max resolution of each display layer (from FBUF) is 1920x1080
Flexible cropping window from FBUF
Support mono-color background (YUV444 format), the resolution of background is
always as same as display panel
Support HW cursor with max resolution 64x64
Supported image format and memory organization stored in FBUF
Layer 1 & Layer 2:
Semi-planar/Planar/Interleaved format for YUV422
Semi-planar/Planar format for YUV420
Layer 3 & Layer4:
8-bpp
RGB565
Packed/Unpacked format for RGB888
RGBA8888
ARGB8888
Only support little-endian organization
Using Pipeline architecture to implement overlay & alpha-blending operation
Each pipeline phase merges two display layers, and the merged result enters the next
pipeline phase
Each pipeline phase supports both overlay & alpha-blending operation
Support key color for overlay operation
Support INV/OR/AND/Transparent operation for overlay
Support pixel alpha value for ARGB8888/RGBA8888
Support global alpha value by configuring register
input format: YUV444
output format: YUV444
Support up-scaling for overlay pixel data , which is output from overlay & alpha-blending
unit
Max input size for up-scaling:
1920x1080
Max output size for up-scaling: 1920x1080
Max x6 for X direction
Max x6 for y direction
Input format: YUV444
Output format: YUV444
Support brightness/contrast/hue/saturation adjustment
Input format: YUV444
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Output format: YUV444
Support programmable gamma correction
Support R, G, B color components corrected separately (3 correction curve)
Input format: RGB888
Output format: RGB888
Support dithering for less than 24-bit color display:
RGB888-> RGB565
RGB888-> RGB666
Provide capture path to implement the function as “capture with frame”. For example, in
some applications, it’s needed that capturing the image from sensor, then adding “some
effect” on the captured image such as photo frame. This “effect” can be implemented by
DE which merges the captured image from sensor and “effect” picture. After merging, DE
need store the merged image to memory (Capture Buffer, CBUF for abbreviation in later
chapters), so the “capture path” is used. Also, “the capture path” could be used for
debugging.
Supported image format and memory organization when writing to CBUF5)
Interleaved format for YUV422
Semi-planar format for YUV420
Unpacked format for RGB888
Only support little-endian organization
Table 6-24 Supported Max Size for Layers (from FBUF)
Layer Number
Layer1
Layer2
Layer3
Layer4
Image Pixel Format
Max Size
YUV422
1080P
YUV420
1080P
YUV422
1080P
YUV420
1080P
YUV422
1080P
YUV420
1080P
8-bpp
1080P
RGB565
1080P
RGB888
1080P
ARGB8888
1080P
RGBA8888
1080P
YUV422
1080P
YUV420
1080P
8-bpp
1080P
RGB565
1080P
RGB888
1080P
ARGB8888
1080P
RGBA8888
1080P
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6.8 GPU
The GPU (Graphics Processing Unit) graphics IP core is designed to meet the market
requirements for high performance 2D and 3D graphics and video decode and encode in
mobile devices or consumer devices.
The GPU IP software stack fully supports for Android, Linux, and windows embedded
platforms. It also supports the OpenGL ES 1.1 and the OpenGL ES 2.0 programmable API and
OpenVG 1.1.
General Features
64 bit AXI interface for independent read and write data buses to memory
Multiple burst length (support 8 bytes, 16 bytes, 32 bytes and 64 bytes) for AXI
4Kbytes addressable register space (could expand to 256Kbytes for future purpose)
32-bit data bus no burst
Low power CMOS technology compatible
Automatic clock gating for flip-flops and rams
software controlled clock skipping
Support up to 500Mhz
Support virtual memory
Support interrupt
Full-featured 3D Graphics Pipeline
OpenGL ES 2.0 compliant, including extensions; OpenGL ES1.1; OpenVG 1.1
IEEE 32-bit floating-point pipeline supports long shader instructions (maximum 256
instruction)
Up to 256 threads per shader
Up to 16 programmable Scalable Ultra-threaded, unified vertex and pixel shaders
FSAA mechanisms: MSAA 4x, high quality FSAA 16x
Vertex processing supported format: BYTE, UBYTE, SHORT, USHORT, INT, UINT, DEC,
UDEC, FLOAT,FLOAT16,D3DCOLOR, FIXED16DOT16
Primitive processing support triangle strip, fan, list, line strip and list, point list, quad
Texture Processing: integer input texture formats: ARGB4444, XRGB4444, ARGB1555,
XRGB1555, RGB565, ARGB8888, XRGB8888, RGBA4444, RGBA8888, YV12, NV12,
YUY2, UYVY
Texture processing: integer output texture formats: RGBA4444, RGBA5551, RGB565,
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RGBA8888
Texture mipmap support: 13 mipmap levels, programmable LOD biasing & replacement
Texture filters: point sample, bi-linear, tri-linear, anisotropic (AF), percentage-closest
filtering for depth textures
Texture types: 2D, cubic environment map, projective, depth, HDR, bump map,
displacement map, cube map
Up to 8 programmable elements per vertex
Dependent texture operation with high-performance
Alpha blending
Depth and stencil compare
Support for 4 vertex shader and 8 pixel shader simultaneous textures
Point sampling, bi-linear sampling, tri-linear filtering and cubic textures
Resolve and fast clear
8K x 8K rendering target and texture size
Low bandwidth at both high and low data rates
Low CPU loading
Full-featured 2D Graphic Pipeline
Bit blit, stretch blit, pattern blit and fast clear
Line drawing
Rectangle fill and clear
Mono expansion for text rendering
Anti-aliased font support
ROP2, ROP3, ROP4
Alpha blending
90/180/270 degree rotation
Vertical and Horizontal mirror
Transparency by monochrome mask, chroma key or pattern mask
High quality 9-tap filter for scaling
32K x 32K coordinate system
Color space conversion between YUV and RGB for both BT709 and BT601
Clipping window
Color Index Input conversion Support
Filter Blit
Input Formats: (Only Filter Blit support YUV input)
A1R5G5B5
A4R4G4B4
A8R8G8B8
X1R5G5B5
X4R4G4B4
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X8R8G8B8
RGB565
NV12 (semi-planer YUV420)
NV16 (semi-planer YUV422)
YUY2(package YUV422)
UYVY(package YUV422)
YV12(planer YUV420)
8-bit color index
1-bit monochrome
The output data Formats:
A1R5G5B5
A4R4G4B4
A8R8G8B8
X1R5G5B5
X4R4G4B4
X8R8G8B8
RGB565
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Chapter 07
Storage
SubSystem
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7 Storage SubSystem
7.1 USB OTG
The UOTG module is the high-speed universal serial bus dual-role subsystem module. It is
composed of the USB 2.0 high-speed dual-role controller (UOTGC) and the high-speed
single-port OTG PHY (single_port_otg_phy)
The function requirement of UOTG interface in VC0882 is list as following.
Support USB Mass Storage in device mode
Provides production firmware download function
Provides access to SD/MMC card or NandFlash
Provides access to baseband resource (Nor-flash/SRAM)
Support USB web camera in device mode
Support USB PictBridge in device mode
Support USB virtual serial port in device mode
Support USB Virtual Ethernet Adapter in device mode
Support USB Mass Storage in host mode
Provides access to USB-HDD/USB-DVDRW
Support USB virtual serial port in host mode
Support USB mouse in host mode.
USB device speed could down to 1.1 by configuration
Support USB charger detecting.
Support standard USB charger (DP and DM are shorted together in charger) detecting
Support non-standard USB charger (DP and DM are both floated in charger) detecting.
The UOTG includes the following features:
Operates either as the host/peripheral in point-to-point communications with another USB
function or as a function controller for a USB peripheral
Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the
On-The-Go supplement to the USB 2.0 specification
Supports point-to-point communications with one high-, full- or low-speed device
Support control, interrupt, bulk, isochronous transfers
Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
Supports Suspend and Resume signaling
Support remote wakeup in host mode
Support 7 additional transmit endpoints and 7 additional receive endpoints
The transfer type of each endpoint is configurable
Configurable FIFOs, support dynamic FIFO sizing
All endpoint FIFOs share a synchronous 4K bytes RAM
Support for CPU access to FIFOs
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Support endpoints interrupt for transmitting or receiving packets
Support for DMA access to FIFOs
Support 8 DMA channels
Support soft connect/disconnect
Performs all transaction scheduling in hardware
Supports off-chip charge pump regulator to generate 5 V for VBUS
Support USB charger detecting.
Support standard USB charger (DP and DM are shorted together in charger) detecting
Support non-standard USB charger (DP and DM are both floated in charger) detecting
7.2 USB HOST
The UHOST module is the high-speed universal serial bus host subsystem module. It is
composed of the high-speed single-port USB host controller (UHOSTEOC) and the
high-speed single-port OTG PHY (single_port_otg_phy)
The main part of UHOSTEOC is an UHOSTIP which is a high-speed single-port USB2.0 host
controller. It contains two independent, single-port host controllers that operate in parallel:
The EHCI controller, based on the Enhanced Host Controller Interface (EHCI) specification
for USB Release 1.0, is in charge of high-speed traffic (480M bit/s), over the UTMI
interface.
The OHCI controller, based on the Open Host Controller Interface (OHCI) specification for
USB Release 1.0a is in charge of full-speed/low-speed traffic (12/1.5M bit/s, respectively),
over a serial interface.
The single-port OTG PHY is owned by exactly one of the controllers at any time.
The UHOST includes the following features:
High-speed single-port USB host controller. Support one USB downstream port.
Fully compliant with the USB 2.0 specification, Enhanced Host Controller Interface (EHCI)
Specification, Revision 1.0, and the Open Host Controller Interface (OHCI) Specification
Release 1.0a.
Supports high-speed, 480-Mbps transfers using an EHCI Host Controller, as well as full
and low speeds through one integrated OHCI Host Controllers.
The supported peripherals are determined by OS software.
For VC0882, the following peripherals need to be supported: USB-HDD, USB-DVDRW,
USB Mouse, USB Keyboard, USB Modem.
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7.3 SDIO Controller
The MMC/SD/SDIO controller (SDIO) provides the host interface for supporting the standard
MMC/SD/SDIO cards, which acts as a bridge between the host system bus and the
MMC/SD/SDIO bus (referred to as “protocol bus”). The SDIO handles MMC/SD/SDIO
protocols at the transmission level, it passes host bus transactions to the MMC/SD/SDIO cards
by sending commands and performing data accesses to/from the cards.
VC0882 SDIO module has the following features:
Compatible with SD Memory Card Spec 2.0 and supports SDHC up to 32GB card
Compatible with SDIO Card Spec 2.0
a)
Support SDIO Read Wait and Suspend/Resume operations
b)
Support SDIO cards to interrupt the host, also support interrupt period
Compatible with JESD84-A43 standard (MMC 4.3), up to 8-bit data bus
Support MMC boot operation
Support MMC bus testing procedure
Support for SD Memory, SDIO, SD Combo, miniSD, MMC, MMC plus, MMC RS and
Trans-Flash cards
Support dual voltage cards typically operating at 1.8V and 3V
Up to 200 Mbps of data transfer for SD/SDIO cards using 4-bit data bus
Up to 416 Mbps of data transfer for MMC cards using 8-bit data bus
Support programmable protocol bus clock for different cards, up to 52MHz
Support Single Block, Multi Block read and write, block size from 1 to 4096 bytes
Support stop during the data transfer at block gap
Support auto command transfer after completing the last data/non-data command transfer
Support internal 2-channel DMA for both transmit and receive, up to 4 linked list item
(referred to as “LLI”) register available for linked memory access
Support two 32x32 bit FIFO for both transmit and receive
Interrupt-based application interface to control software interaction
7.4 NAND Flash Controller
NAND Flash Controller (NFC) is designed for NAND flash interface. The NFC provides an
interface between standard NAND Flash devices and the IC and hides the complexities of
accessing a NAND Flash memory device. It provides an interface to 8-bit or 16-bit NAND flash
devices (including SLC, MLC and TLC1)) with different page size from 512B to 16KB. The
NAND interface supports a few functions, such as Page Reading, Page Writing, Block erasing,
Reset operation and so on. The NFC module can support BCH (Bose, Chaudhuri &
Hocquenghem Type of code) encode and decode operation. When sector size is 512B, the
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4/8/16 bit ECC is supported, when sector size is 1024B, the 24/32/40/48 bit ECC is supported.
Logically, NFC is mainly composed of three parts: MARB DMA interface, ECC codec and
NAND flash control interface.
Note1): SLC: Single Level Cell; MLC: Multiple Level Cell; TLC: Triple Level Cell.
Compliant to open NAND Flash Interface (ONFI) 1.0 Specification.
Support mainly operation by hardware:
Support page program and page read operation
Support page cache program and page cache read operation
Support page random program and page random read operation
Support status read operation after page program operation
Support mainly operation by software:
Support block erase operation
Support reset operation
Support plane program and plane read operation
Support status read operation1)
Hardware BCH encoder and decoder are included.
Error detection/correction capability of 4/8/16 bits per 512 bytes
Error detection/correction capability of 24/32/40/48 bits per 1024 bytes
8-bit parallel architecture and calculation based on 1-bit length
The ECC calculation region is configurable (User data only or both user data and FTL2)
data or bypass the ECC calculation for both user data and FTL data)
Support SLC, MLC and TLC NAND flash.
Support single command transfer by hardware and triggered by software
Support single address transfer by hardware and triggered by software
Support single data transfer(including reading and programming) by hardware and
triggered by software
Support auto checking whether page is erased or not by hardware during page reading
operation
Support address & command transfer of random operation by hardware when in FTL
transfer
Support interlaced storage of ECC and user data.
Support Asynchronous Interface Bus Operation
Module frequency is 50Mhz for 8-bit interface, and interface clock is 50Mhz
Module frequency is 100Mhz for 16-bit interface, and interface clock is 50Mhz
Support max 16 DMA operation consecutively during a page operation
8KB for 512B/sector
16KB for 1024B/sector
Support FTL data length up to 32 byte3) when FTL ECC is enabled.
Support max 4 consecutive page read/ page cache read by hardware
Support max 4 consecutive page program/page cache program by hardware
Support read NAND flash status by hardware after page program operation
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Support AXI BUS Interface.
Support 8/16 bit data bus.
Support 16 CS (chip select) signal interface.
Support 2 RB(ready/busy) signal interface
Support NAND DMA data transfer by hardware and command & address transfer by
software.
Support both NAND DMA data transfer and command & address transfer by hardware
Support delay configuration (8bit registers from 0 to 0xFF nfc_mclk) between command
and data.
Support delay configuration (8bit registers from 0 to 0xFF nfc_mclk) between address and
data.
Support error correction by hardware itself before writing data to DRAM during NAND read
operation4).
Support configurable page address cycle number (four cycles or five cycles).
Support 16bit nand flash composed by double chip 8bit nand flash.
Note1): The read status operation can be supported by software. During page program
operation, the status operation is done by hardware itself after a page program is done.
Note2): FTL is file transfer layer. The address & command transfer of random operation by
hardware is also used when only FTL data needs to be read or written, it can also be used for
other type of data transfer for compatibility . But only one DMA random transfer supported for
one page in one trigger operation, multiple random transfers are not supported during one
trigger operation.
Note3): There is no FTL length restriction when there FTL does not participate in ECC
calculating.
Note4): The operation is reading data from NAND and writing them to DRAM.
7.5 SPI (Serial Peripheral Interface)
The SPI controller module has the following features:
Support two SPI controllers;
Provide master/slave modes selectable by control registers;
Full duplex synchronous serial data transfer;
The frequency, polarity, and phase of SCLK are programmable;
The polarity of SSN is programmable;
MSB or LSB first data transfer mode is programmable for both 8-bit and 16-bit;
Support SPI data transfer by APB mode and DMA mode;
The max transfer length of DMA transfer is 2M bytes for master mode;
8X32 FIFO for both transmitting and receiving data;
The max frequency of module clock (spi_clk) is 216MHz;
The max transfer speed in master mode is 54MHz;
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The max transfer speed in slave mode is 27MHz;
When work in master mode, one SPI master can connect up to 2 SPI slaves with two SSN
and MISO.
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Chapter 08
Peripheral
SubSystem
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8 Peripheral SubSystem
8.1 Audio Module
VC0882 Audio Subsystem (AUD) is responsible for the chip’s audio playback and record. It
mainly consists of 2 parts: Audio Interface and Audio Codec:
Audio Interface (referred to as AUDIF): it acts as a bridge which handles data transfer
between System Memory and Audio Codec, also supporting data format conversion and
digital mixer
Audio Codec (referred to as ACOD): it’s a mixed analog/digital virtual component
containing a stereo audio codec (ADC + DAC) and additional analog function offering an
ideal mixed signal front end for low power and high quality audio applications
The AUD also provides 2 I2S/PCM Interfaces of master mode through VC0882 PADs to
support optional outer devices connection, such as Bluetooth and the 3rd-party Audio Codec.
With VC0882 Audio Subsystem, various applications can be implemented, such as music
playback, microphone record, call in/out with background sound, call in/out with 2-way record,
karaoke with record, FM radio with record, as well as WIFI phone call in/out.
The AUDIF module provides the following features:
Provides 2 I2S/PCM Interfaces of master mode through VC0882 PADs, so as to connect
external devices of slave mode
Transfers with MSB first and left alignment
Supports 8 I2S Formats and 4 PCM Formats
Includes two 32-bit stereo digital mixer (produce Y = A + B result)
Supports processing left and right channel data separately
Supports overflow and underflow clip control
Includes 1 Transmit DMA channel and 1 Transmit FIFO (32x32 bit), also supports software
ping-pong buffer operation
Includes 2 Receive DMA channels and 2 Receive FIFOs (32x32 bit), also supports
software ping-pong buffer operation
Supports 6 memory formats of audio raw data: Stereo-32bit, Stereo-16bit, Stereo-8bit,
Mono-32bit, Mono-16bit, and Mono-8bit
Supports only signed audio data processing
Switches data path by multiplexers to implement various applications flexibly
The ACOD module provides the following features:
Built-in PLL solution to better jitter issue
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12MHz or 13MHz master clock supply
Contains a high-quality 24-bit stereo ADC and a high-quality 24-bit stereo DAC
Provides 6 mono differential line inputs with boost gain stage (0/4/8/12/16/20 dB), they can
be used either for line in or microphone in application
Includes 2 multiplexers in front of the input PGA to select the signal between the line inputs
Provides 1 stereo single-end 16/32 Ohm headphone output
Provides 2 mono differential line output that but they can’t be driven simultaneously
Provides 1 mono differential BTL 16/32 Ohm receiver output
Provides stereo differential speaker output and one of them can also be configured to the
mono differential BTL 8 ohm output
Supports audio sampling rates (Fs) from 8KHz to 96KHz (88.2KHz not supported)
Supports the Automatic Gain Control (AGC) function for better sound recording
performances
Built-in reduction of audible glitches systems
Patented pop-up noise reduction system
Provide soft mute mode to reduce audible parasites
Include zero-cross detection to minimize zipper noise
Supports output short circuit protection
Provides 2 microphone bias output
Embedded low dropout linear regulator
Internal voltage reference to generate all required internal voltages
UART
The UART (Universal Asynchronous Receiver/Transmitter) core provides serial
communication capabilities, which allow communication with external devices, like another
computer using a serial cable and RS232 protocol. The UART module performs all of the
normal operations associated with start-stop asynchronous communication. Serial data is
transmitted and received at standard bit rates using the internal baud rate generator. This core
is designed to be maximally compatible with the industry standard National Semiconductors’
16550A device.
The UART controller module has the following features:
Functional compatible with the 16550A.
Full-duplex operation.
Robust receive data sampling with noise filtering.
64-byte FIFO for receiver and 64-byte FIFO for transmitter.
- Programmable interrupt trigger levels for FIFO.
- "Old data" timer on receiver FIFO.
Fully programmable serial interface.
- Data bit: 7-bit or 8-bit.
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- Parity bit: None, Even, Odd, or Stick check.
- Stop bit: 1-bit or 2-bit.
Break condition detection and generation.
Embody baud rate generator.
- Programmable integer and fractional divisor for baud rate generation.
- Programmable Baud rate computation method support up to 12Mbps baud rate.
- Slow speed mode: Baud rate = (functional clock/16)/divisor.
- Middle speed mode: Baud rate = (functional clock/8)/divisor.
- High speed mode: Baud rate = (functional clock/4)/divisor.
Complete status-reporting capability.
Internal diagnostic capability.
- Loop-back mode for self test.
- Break condition, parity error and framing error simulation.
Slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA)
specification.
Separate APB read/write operation for transmit and receive data.
Separate DMA Operation for transmit and receive data services.
Modem control functions with DSR, DCD, RI and DTR signals.
Auto-flow control capability.
- RTS controlled by UART receive FIFO.
- CTS from external controls UART transmitter.
Software-flow control capability.
- Programmable XOFF character used to stop the UART transmitter.
- Programmable XON character used to start the UART transmitter.
IIC Module
I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of data
exchange between devices. It is most suitable for applications requiring occasional
communication over a short distance between many devices.
There are two separate I2C master controllers in VC0882, each of which provides an interface
between the internal ARM processor and any external I2C-bus-compatible device that
connects through the I2C serial bus. They use the same I2C master controller module. This
document describes the I2C master controller module in VC0882.
The I2C master controller module has the following features:
Master mode only
Compliance with Philips I2C bus specification version 2.1
Support for standard mode (up to 100K bits/s) and fast mode (up to 400K bits/s)
Support multi master mode
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7-bit and 10-bit device addressing modes
Support start/restart/stop
Transaction based software interface
Built-in 16-byte FIFO for buffered read or write
The maximum transfer length of each transaction is 65535 for read or write operation. The
zero transfer length means there is no data to be written out or no data to be read in for
current transaction.
Module enable/disable capability
Programmable SCL clock generation
8-bit-wide data access
Arbitration lost detection
Bus busy detection
Clock Stretching and Wait state generation
Support PMU hardware directly communicates with external power management chip with
five request channels and priority control. Support hardware round-robin arbitration and
software arbitration. During software arbitration mode the software can has exclusive I2C
bus control until it release the I2C bus.
Not support CBUS address
Not support high-speed mode
8.4 PWM
The PWM module is used to generate square waves with variable pulse width and frequency.
The frequency of output signal ranges from 6K to 12MHz with 24MHz reference clock, and the
output pulse ratio ranges from 0/256 to 255/256. The average DC voltage of PWM wave can
be utilized to drive various devices, such as LED and motor. In VC0882, there are three PWM
outputs. Each PWM output can be controlled by software independently.
The following lists the main features of PWM module:
AMBA 3 APB (Advanced Peripheral Bus) register bus interface
Supports up to 3 external channels
The pulse ratio of the output waveform ranges from 0/256 to 255/256.
The frequency of the output waveform ranges from 6KHz to 12MHz.
8.5 KeyPad
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The KPD module supports the keypad that connects the column and row when their
intersecting key is pressed. The KPD is a 16-bit interface peripheral and provides interface for
R x C off-chip keypad matrix.
An off-chip keypad matrix is defined as an X-Y matrix where one key is pressed at a time
or more keys are pressed simultaneously, the keypad definition is used for portable
applications such as mobile phones, personal digital assistants, smart handheld devices,
personal media players or other handheld applications.
The 16-bit keypad ports can be configured as output ports for C (column) or input ports for
R (row) by writing to keypad control registers according to system application. R (row) is input
of KPD module, while C (column) is output of KPD module.
The KPD is designed to simplify the software task of scanning a keypad matrix. With
appropriate software support, the KPD is capable of detecting depress/release and decoding
one or multiple keys pressed simultaneously on the keypad.
Logic in the KPD is capable of scanning the keypad matrix periodically, and storing up to
three key-values pressed in the interrupt status register simultaneously. The KPD may
generate a CPU interrupt any time when a key press or release is detected, if the interrupt is
unmasked.
The following lists the main feature of KPD IP core:
32-bit AMBA-APB slave bus interface.
Supports R x C external keypad matrix (R + C = 8 Tm, Tm = 7.8ns
(2) tod < 7.5+4Tm. In slave mode, SPI_SCLK is generated by external SPI device, so SPI need to do
synchronization and glitch suppression before use. Time for synchronization and glitch suppression
is 4 SPI module internal working clock period Tm. In the above table, Tm = 7.8ns
(3) toh > 4Tm. In slave mode, SPI_SCLK is generated by external SPI device, so SPI module need to
do synchronization and glitch suppression before use. Time for synchronization and glitch
suppression is 4 SPI module internal working clock period Tm. In the above table, Tm = 7.8ns
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Figure 9-2
SPI Interface--Transmit and Receive in Slave Mode
SPI in Master Mode
Table 9-19 SPI Interface Electrical Characteristics (Master Mode)
Parameter
tp Cycle time, SPI_SCLK period
tss SPI_SSN active to SPI_SCLK first edge
tsh SPI_SCLK last edge to SPI_SSN inactive
tod Delay time, SPI_SCLK active edge to SPI_MOSI
shifted
toh Hold time, SPI_MOSI valid after SPI_SCLK active
edge
tds Setup time, SPI_MISO valid before SPI_SCLK active
edge
tdh Hold time, SPI_MISO valid after SPI_SCLK active
edge
MIN MAX Unit
15.6
ns
62.4
ns
62.4
ns
3.2
ns
-1
ns
9.5
ns
-3
ns
Notes
(1)
(2)
(2)
(1) SPI_SCLK period should be at least 2 times as that of SPI module internal working clock in master
mode: T >= 2 Tm
(2) Programmable by configuring SPI register, 4 SPI_SCLK period is default value and also for
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recommendation. In the above table, SPI_SCLK period = 15.6ns
Figure 9-3
SPI Interface--Transmit and Receive in Master Mode
9.6 I2C Interface Timing
Table 9-20 I2C Interface Timing Conditions
Timing Condition Parameter
Input Conditions
tR
Input signal rise time
tF
Input signal fall time
Output Condition
Cload
Output load capacitance
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MIN
MAX
Unit
0.5
0.5
5
5
ns
ns
20
pf
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Table 9-21 I2C Interface Electrical Characteristics (Standard Mode)
Parameter
tCSCL
Cycle time, SCL period
tWHSCL SCL high pulse width
tWLSCL SCL low pulse width
tS2SCL Setup time, SDA low to high when SCL high for stop bit
tH2SCL Hold time, SDA high to low when SCL high for start bit
tWBF
I2C bus free time
tS2SDA SDA setup time
tH2SDA SDA hold time
MIN MAX Unit
10
us
4.0
us
4.7
us
4.0
us
4.0
us
4.7
us
250
ns
0
ns
Table 9-22 I2C Interface Electrical Characteristics (Fast Mode)
Parameter
tCSCL
Cycle time, SCL period
tWHSCL SCL high pulse width
tWLSCL SCL low pulse width
tS2SCL Setup time, SDA low to high when SCL high for stop bit
tH2SCL Hold time, SDA high to low when SCL high for start bit
tWBF
I2C bus free time
tS2SDA SDA setup time
tH2SDA SDA hold time
MIN MAX Unit
2.5
us
0.6
us
1.3
us
0.6
us
0.6
us
1.3
us
100
ns
0
ns
Figure 9-4 I2C Interface Timing
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9.7 SDIO Interface Timing
Table 9-23 SDIO Interface Timing Conditions
Timing Condition Parameter
Input Conditions
tR
Input signal rise time
tF
Input signal fall time
Output Condition
Cload
Output load capacitance
MIN
MAX
Unit
0.5
0.5
5
5
ns
ns
40
pf
Table 9-24 SDIO Interface Electrical Characteristics
Parameter
tp
Cycle time, SD_CLK period
tw
Duration time, SD_CLK high
tsu
Setup time, input data valid before SD_CLK active
edge
tIH
Hold time, input data valid after SD_CLK active
edge
tOD
Delay time, SD_CLK active edge to data output
transition
tOH
Hold Time, data output valid after SD_CLK active
edge
tCMDD Delay time, SD_CLK active edge to command
output transition
tCMDH Hold Time, command output valid after SD_CLK
active edge
MIN
20
8
4.6
MAX Unit Notes
ns
ns
(1)
ns
0
ns
12
2
12
2
ns
(2)
ns
(2)
ns
(2)
ns
(2)
(1) Duty cycle of SDIO_CLK is 40% of the clock cycle.
(2) The same value in both normal and high speed mode
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tp
tw
SD_CLK
tSU
tIH
Data
SD_DATA (In)
SD_DATA (Out)
Data
tOD
tOH
Command
SD_CMD
tCMDD
Figure 9-5
tCMDH
SDIO Interface Normal Timing
tp
tw
SD_CLK
tSU
tIH
Data
SD_DATA (In)
Data
SD_DATA (Out)
tOD
tOH
Command
SD_CMD
tCMDD
Figure 9-6
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tCMDH
SDIO Interface High Speed Timing
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9.8 NFC Interface Timing
Table 9-25 NFC Interface Timing Conditions
Timing Condition Parameter
Input Conditions
tR
Input signal rise time
tF
Input signal fall time
Output Condition
Cload
Output load capacitance
MIN
MAX
Unit
0.5
0.5
5
5
ns
ns
40
pf
Table 9-26 NFC Interface Electrical Characteristics
Parameter
tWC
WEN cycle time
tWP
WEN pulse width
tRP
REN pulse width
tRC
REN cycle time
tCLS
CLE setup time
tCLH
CLE hold time
tCS
CEN setup time
tCH
CEN hold time
tALS
ALE setup time
tALH
ALE hold time
tDOS
Data output setup time
tDOA
Data output delay time for access
tDOH
Data output hold time
tDIS
Data input setup time
tDIH
Data input hold time
MIN
20
9
20
9
80
80
80
80
80
80
10
MAX
2
8.6
3.3
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(1) Related to the output maximum frequency supported by the NFC module.
(2) Programmable by configuring NFC register, as least 4 write/read cycles are for recommendation. In
the above table, write/read cycle period = 20ns.
(3) tDOH > -0.365 + min (tWP), relative to the rise edge of WEN, the actual output delay time shall be
combined with 1/2 of write cycle time, i.e., the minimum write pulse, here min (tWP) = 9ns.
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NF_CLE
NF_CE
N
NF_WE
N
NF_ALE
Command
NF_DATA
Figure 9-7
Figure 9-8
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NFC Command Latch Timing
NFC Address Latch Timing
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Figure 9-9
NFC Data Output Timing
Figure 9-10 NFC Standard Data Input Timing
Figure 9-11 NFC EDO Data Input Timing
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9.9 AUD Interface Timing
Table 9-27 Audio Interface Timing Conditions
Timing Condition Parameter
Input Conditions
tR
Input signal rise time
tF
Input signal fall time
Output Condition
Cload
Output load capacitance
MIN
MAX
Unit
0.5
0.5
5
5
ns
ns
20
pf
Table 9-28 Audio Interface Electrical Characteristics
Parameter
tsclk
AUD_SCK period
twsdly Delay time, AUD_SCK active edge to AUD_WS
transition
tsdodly Delay time, AUD_SCK active edge to
AUD_SDO_DAC transition
tsdistp AUD_SDI_ADC setup time
tsdihld AUD_SDI_ADC hold time
MIN
MAX Unit Notes
162.5 1953 ns
(1)
1
6.2
ns
1
8.6
11.2
0
ns
ns
ns
(1) AUD_SCK = 64 x fs , where max(fs) = 96KHz and min(fs) = 8KHz. (fs means frequency of sample)
Figure 9-12 Timing Specification of I2S/PCM Serial Interface to External Devices
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9.10 LCD Interface Timing
Table 9-29 LCD Interface Timing Conditions
Timing Condition Parameter
Input Conditions
tR
Input signal rise time
tF
Input signal fall time
Output Condition
Cload
Output load capacitance
MIN
MAX
Unit
0.5
0.5
5
5
ns
ns
20
pf
LCD Serial Interface
Table 9-30 LCD Interface Electrical Characteristics (Serial Interface)
Parameter
tLSCL
SCL low level pulse width
tHSCL
SCL high level pulse width
tDS
SDA setup time
tDH
SDA hold time
tCSS
CS setup time
tCSH
CS hold time
tAS
DCX setup time
tAH
DCX hold time
MIN
40
40
30.5
30
30.5
36
29
30
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(1)(2)
(1)(3)
(1)(4)
(1)(5)
(1)(6)
(1)(7)
(1)(8)
(1)(9)
(1) The setup and hold time can be configured by the internal register of VC0882, the value listed in the table are
the parameter range which VC0882 can support at most, the hold/setup need of the panel should not exceed
the max hold/setup value. The value in the table above is calculated when TPCLK is 40ns. PCLK is the refresh
clock of panel.
(2) The width of tLSCL is n*TPCLK, in which n can be configured between 1 and 128 by the internal register
SCK_WIDTH.
(3) The width of tHSCL is n* TPCLK, in which n can be configured by the internal register SCK_WIDTH.
(4) The SDA setup time tDS = n* TPCLK -9.5, in which n can be configured from 1 to 128 by the internal register
SCK_WIDTH. For example, if the panel need of SDA setup time is 120ns and TPCLK is 40ns, so we can
configure the n to 4 or even larger. For n=5, the tDS =150.5ns, which is larger than 120ns.
(5) The SDA hold time tDH = n* TPCLK -10, in which n can be configured from 1 to 128 by the internal register
SCK_WIDTH. We should configure the n parameter according to the panel need. For example, if the panel
need of SDA hold time is 120ns and TPCLK is 40ns, so we can configure the n to 4 or even larger. For n=4, the
tDH =150ns, which is larger than 120ns.
(6) The CS setup time tCSS = n* TPCLK -9.5, in which n can be configured from 1 to 128 by the internal register
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SCK_WIDTH.
(7) The CS hold time tCSH = n* TPCLK -4, in which n can be configured from 1 to 128 by the internal register
SCK_WIDTH.
(8) The DCX setup time tAS = n* TPCLK -11, in which n can be configured from 1 to 128 by the internal register
SCK_WIDTH.
(9) The DCX hold time tAH = n* TPCLK -10, in which n can be configured from 1 to 128 by the internal register
SCK_WIDTH.
DCX
tAS
tAH
CS
tCSS
tCSH
tHSCL
tLSCL
SCK
tDS
SDA
DATA
DATA
tDH
DATA
DATA
DATA
DATA
Figure 9-13 LCD Serial Interface Timing
Data Output for DPI Panel
Table 9-31 LCD Interface Electrical Characteristics (Data Output for DPI Panel)
Parameter
tp
LCD_PCLK period
tduty LCD_PCLK output clock duty cycle
todr Delay time, LCD_PCLK rise edge to data transition
tohf Hold time, data valid after LCD_PCLK fall edge
todf Delay time, LCD_PCLK fall edge to data transition
tohr Hold time, data valid after LCD_PCLK rise edge
MIN
6.17
40%
MAX
60%
2.7
1.74
2.9
1.88
Unit
ns
ns
ns
ns
ns
Notes
(1)
(2)
(1) tohf > -0.72 + 1/2tp, relative to the next edge of LCD_PCLK, the actual output delay time shall be combined
with 1/2 of pixel cycle time, the duty cycle 40% shall also be considered.
(2) tohr > -0.58 + 1/2tp, relative to the next edge of LCD_PCLK, the actual output delay time shall be combined
with 1/2 of pixel cycle time, the duty cycle 40% shall also be considered.
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Figure 9-14 Data Output Timing for DPI Panel (falling edge capture)
Figure 9-15 Data Output Timing for DPI Panel (rising edge capture)
Interface Timing with DBI Panel
DBI Write Operation
Table 9-32 LCD Interface Electrical Characteristics (DBI Panel for Write Operation)
Parameter
tWLW
Write low level pulse width
tWHW
Write high level pulse width
tAS
Address setup time
tAH
Address hold time
tDSW
Write data setup time
tDHW
Write data hold time
tCS
Chip select setup time
tCH
Chip select hold time
MIN
40
40
35.5
37
35.5
30.5
35
37
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(1)(2)
(1)(3)
(1)(4)
(1)(5)
(1)(6)
(1)(7)
(1)(8)
(1)(9)
(1) The setup and hold time can be configured by the internal register of VC0882, the value listed in the table are
the parameter range which VC0882 can support at most, the hold/setup need of the panel should not exceed
the max hold/setup value. The value in the table above is calculated when TPCLK is 40ns. PCLK is the internal
working clock of LCDIF module.
(2) The width of tWLW is n*TPCLK, in which n can be configured from 1 to 31 by the internal register WRC.
(3) The width of tWHW is n*TPCLK, in which n can be configured from 1 to 62 by the internal register WSC and DHC
(4) The Address setup time tAS = n*TPCLK -4.5, in which n can be configured from 1 to 31 by the internal register
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WSC. If the panel setup need is 100ns, n can be configured to 3, then the tAS = (3*40 -4.5) = 115.5n, which is
larger then 100n.
(5) The Address hold time tAH = n*TPCLK -3, in which n can be configured from 1 to 31 by the internal register DHC.
If the panel setup need is 60ns, n can be configured to 2, then the tAH = (2*40 -3) = 87n, which is larger then
60n.
(6) The Write data setup time tDSW = n*TPCLK - 4.5, in which n can be configured from 1 to 62 by the internal
register WSC and WRC.
(7) The Write data hold time tDHW = n*TPCLK - 9.5, in which n can be configured from 1 to 31 by the internal register
DHC.
(8) The Chip select setup time during write tCS = n*TPCLK - 5, in which n can be configured from 1 to 62 by the
internal register WSC and WRC.
(9) The Chip select hold time tCH = n*TPCLK - 3, in which n can be configured from 1 to 31 by the internal register
DHC.
RS
tAS
tAH
tCS
tCH
CSN
tWLW
tWHW
WRN
tDSW
tDHW
Valid data
Write Data DB[17:0]
Figure 9-16 LCD Interface Timing for DBI Panel (Write Operation)
DBI Read Operation
Table 9-33 LCD Interface Electrical Characteristics (DBI Panel for Read Operation)
Parameter
tRLW
Read low level pulse width
tRHW
Read high level pulse width
tAS
Address setup time
tAH
Address hold time
tRACC
Read data access time
tDH
Read data hold time
tCS
Chip select setup time
tCH
Chip select hold time
MIN
40
40
35.5
38.5
10
-15
35
38
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(1)(2)
(1)(3)
(1)(4)
(1)(5)
(1)(6)
(1)(7)
(1)(8)
(1)(9)
(1) The setup and hold time can be configured by the internal register of VC0882, the value listed in the table are
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VC0882 Data Book
the parameter range which VC0882 can support at most, the hold/setup need of the panel should not exceed
the max hold/setup value. The value in the table above is calculated when TPCLK is 40ns. PCLK is the internal
working clock of LCDIF module.
(2) The width of tRLW is n*TPCLK, in which n can be configured from 1 to 31 by the internal register RAC.
(3) The width of tRHW is n*TPCLK, in which n can be configured from 1 to 62 by the internal register RAC and ROC.
(4) The Address setup time during Read tAS = n*TPCLK -4.5, in which n can be configured from 1 to 31 by the
internal register RSC. If the panel setup need is 100ns, n can be configured to 3, then the tAS = (3*40 -4.5) =
115.5n, which is larger then 100n.
(5) The Address hold time during Read tAH = n*TPCLK -1.5, in which n can be configured from 1 to 31 by the
internal register DHC. If the panel setup need is 60ns, n can be configured to 2, then the tAH = (2*40 -1.5) =
78.5n, which is larger then 60n.
(6) The Read data access time we can tolerate is tRACC = n*TPCLK -30, in which n can be configured from 1 to 31
by the internal register RAC. The panel access time should not exceed tRACC. For example, if the panel access
time is 100n, the n can be configured to 4 or larger. When n=4, tRACC =130ns, which is larger than 100ns.
(7) The Read data hold time tDH = -15, which means the read data output from panel can be ahead of the
posedge of RD 15ns.
(8) The Chip select setup time during Read tCS = n*TPCLK -5, in which n can be configured from 1 to 62 by the
internal register RAC and RSC.
(9) The Chip select hold time during Read t tCH = n*TPCLK -2, in which n can be configured from 1 to 31 by the
internal register ROC.
RS
tAS
tAH
tCH
tCS
CSN
tRLW
tRHW
RDN
tRACC
Read Data
DB[17:0]
tDH
Valid data
Figure 9-17 LCD Interface Timing for DBI Panel (Read Operation)
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