Document #
Originator:
13-52-12
Title:
QMA7981 Datasheet
Rev:D
MEMS / Peili Yan
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
1 / 30
矽睿
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
Abstract
Single-Chip 3-Axis Accelerometer
QMA7981
Advanced Information
The QMA7981 is a single chip three-axis accelerometer. This surface-mount, small sized
chip has integrated acceleration transducer with signal conditioning ASIC, sensing tilt, motion,
shock and vibration, targeted for applications such as screen rotation, step counting, sleep quality,
gaming and personal navigation in mobile and wearable smart devices.
The QMA7981 is based on our state-of-the-art, high resolution single crystal silicon MEMS
technology. Along with custom-designed 14-bit ADC ASIC, it offers the advantages of low noise,
high accuracy, low power consumption, and offset trimming. The device supports digital interface
IIC and SPI.
The QMA7981 is in a 2x2x0.95mm3 surface mount 12-pin land grid array (LGA) package.
FEATURES
BENEFIT
3-Axis Accelerometer in a 2x2x0.95 mm3 Land
Small size for highly integrated products.
Grid Array Package (LGA), guaranteed to
operate over a temperature range of -40 °C to
+85 °C.
Signals have been digitized and factory
trimmed.
14-Bit ADC with low noise accelerometer
High resolution allows for motion and tilt
I2C Interface with Standard and Fast modes.
High-Speed
sensor
Support SPI digital interface
Built-In Self-Test
sensing
Interfaces
communications.
for
fast
data
Enables low-cost functionality test after
assembly in production
Wide range operation voltage (1.71V To
Automatically maintains sensor’s sensitivity
3.6V) and low power consumption (2-50uA
low power conversion current)
under wide operation voltage range and
compatible
with
battery
powered
applications
RoHS compliant , halogen-free
Environmental
protection
and
wide
applications
Built–in motion algorithm
Low power and easy applications including
step counting, sleep quality, gaming and
personal navigation
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
2 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
CONTENTS
CONTENTS....................................................................................................................................................................................... 3
1
INTERNAL SCHEMATIC DIAGRAM ................................................................................................................................... 4
1.1
Internal Schematic Diagram ..................................................................................................................................... 4
2
SPECIFICATIONS AND I/O CHARACTERISTICS .............................................................................................................. 5
2.1
Product Specifications .............................................................................................................................................. 5
2.2
Absolute Maximum Ratings ..................................................................................................................................... 6
2.3
I/O Characteristics .................................................................................................................................................... 6
3
PACKAGE PIN CONFIGURATIONS ..................................................................................................................................... 7
3.1
Package 3-D View .................................................................................................................................................... 7
3.2
Package Outlines ...................................................................................................................................................... 8
4
EXTERNAL CONNECTION ................................................................................................................................................. 10
4.1
I2C Dual Supply Connection .................................................................................................................................. 10
4.2
I2C Single Supply connection ................................................................................................................................ 10
4.3
SPI Dual Supply Connection .................................................................................................................................. 11
4.4
SPI Single Supply connection ................................................................................................................................ 11
5
BASIC DEVICE OPERATION .............................................................................................................................................. 12
5.1
Acceleration sensor................................................................................................................................................. 12
5.2
Power Management ................................................................................................................................................ 12
5.3
Power On/Off Time ................................................................................................................................................ 12
5.4
Communication Bus Interface I2C and Its Addresses ............................................................................................. 13
6
MODES OF OPERATION ..................................................................................................................................................... 14
6.1
Modes Transition .................................................................................................................................................... 14
6.2
Description of Modes ............................................................................................................................................. 14
7
Functions and interrupts .......................................................................................................................................................... 15
7.1
STEP_ INT ............................................................................................................................................................. 15
7.2
DRDY_INT ............................................................................................................................................................ 16
7.3
ANY_MOT_INT .................................................................................................................................................... 16
7.4
SIG_MOT_INT ...................................................................................................................................................... 17
7.5
NO_MOT_INT ....................................................................................................................................................... 17
7.6
RAISE_INT ............................................................................................................................................................ 17
7.7
Interrupt configuration ............................................................................................................................................ 17
8
I2C COMMUNICATION PROTOCOL .................................................................................................................................. 19
8.1
I2C Timings ............................................................................................................................................................ 19
8.2
I2C R/W Operation ................................................................................................................................................. 19
9
REGISTERS ........................................................................................................................................................................... 21
9.1
Register Map .......................................................................................................................................................... 21
9.2
Register Definition ................................................................................................................................................. 22
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reproduced, or disclosed in whole or in part without prior written permission of QST.
3 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
1 INTERNAL SCHEMATIC DIAGRAM
1.1 Internal Schematic Diagram
Sinc
Offset
FS
CVA
SDM
G-SENSOR
MUX
INT1
Interrupt
Gain
INT2
AD0
IF
SDA
OSC
BG
VPMXYZ
Trim
Reg File
SCL
OTP
RESV1
GND
POWER(A+D)
POR
Mode
FSM
SelfTest
Table 1.
Block Function
Block
Transducer
CVA
Interrupt
FSM
I2C/SPI
OSC
Power
RESV2
VDD
Block Diagram
GND
VDDIO
Figure 1.
SENB
Function
3-axis acceleration sensor
Charge-to-Voltage amplifier for sensor signals
Digital interrupt engine, to generate interrupt signal on data conversion, and
motion function
Finite state machine, to control device in different mode
Interface logic data I/O
Internal oscillator for internal operation
Power block, including LDO
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reproduced, or disclosed in whole or in part without prior written permission of QST.
4 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
2 SPECIFICATIONS AND I/O CHARACTERISTICS
2.1
Product Specifications
Table 2.
Specifications (* Tested and specified at 25°C and 3.0V VDD except stated otherwise.)
Parameter
Supply voltage VDD
I/O voltage VDDIO
Standby current
Low power current
Low noise current
BW
Data output rate
(ODR)
Conditions
VDD, for internal blocks
VDDIO, for IO only
VDD and VDDIO on
ODR=268 Hz
ODR=134 Hz
ODR=67 Hz
ODR=33.6 Hz
ODR=13.4 Hz
ODR=6.7 Hz
ODR=32.5 Hz
ODR=21.6 Hz
ODR=13 Hz
ODR=6.5 Hz
Programmable bandwidth
Min
1.71
1.71
2*BW
Typ
3.3
3.3
1
50
25.3
12.9
6.7
2.9
1.7
100
83.3
50
25
0.16~168
Max
3.6
VDD
Unit
V
V
μA
μA
μA
Hz
Samples
/sec
0.32~336
Startup time
From the time when VDD reaches to
90% of final value to the time when
device is ready for conversion
2
ms
Wakeup time
From the time device enters into
active mode to the time device is
ready for conversion
1
ms
Operating
temperature
Acceleration Full
Range
Sensitivity
Sensitivity
Temperature Drift
Sensitivity tolerance
Zero-g offset
Zero-g offset
Temperature Drift
Noise density
Nonlinearity
Cross Axis Sensitivity
-40
FS=±2g
FS=±4g
FS=±8g
FS=±16g
FS=±32g
℃
85
±2/±4/±8/
±16/±32
4096
2048
1024
512
256
g
LSB/g
FS=±2g, Normal VDD Supplies
±0.02
%/℃
Gain accuracy
FS=±2g, Normal VDD Supplies
±4
±80
%
mg
FS=±2g, Normal VDD Supplies
±2
mg/℃
FS=±2g, run state
FS=±2g, Best fit straight line,
200
±0.5
1
μg/√Hz
%FS
%
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reproduced, or disclosed in whole or in part without prior written permission of QST.
5 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
2.2
Absolute Maximum Ratings
Table 3.
Absolute Maximum Ratings (Tested at 25°C except stated otherwise.)
Parameters
VDD
VDDIO
ESD
Shock Immunity
Storage temperature
Condition
Min
-0.3
-0.3
HBM
Duration < 200μS
-50
Max
5.4
5.4
2
10000
150
Units
V
V
kV
g
℃
2.3 I/O Characteristics
Table 4.
I/O Characteristics
Parameter
Voltage Input
High Level 1
Voltage Input
Low Level 1
Voltage Output
High Level
Voltage Output
Low Level
Symbol
VIH1
Pin
SDA, SCL
VIL1
SDA, SCL
VOH
INT1, INT2
VOL
INT1, INT2,
SDA
Condition
Output Current
≥-100μA
Output Current
≤100μA(INT)
Output Current
≤1mA (SDA)
Min.
0.7*VDDI
O
-0.3
TYP.
Max.
VDDIO+0
.3
0.3*VDDI
O
0.8*VDDI
O
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
Unit
V
V
V
0.2*VDDI
O
V
6 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
3 PACKAGE PIN CONFIGURATIONS
3.1 Package 3-D View
Arrow indicates direction of g field that generates a positive output reading in normal measurement configuration.
AD0
2
SDX
3
VDD
IO
4
RES
V1
11
SCX
RES
V2
x
Top View
y
QMA7981
1
12
INT
1
INT
2
5
6
Figure 2.
Package View
Table 5.
Pin Configurations
PIN
No.
1
PIN
NAME
AD0
I/O
2
3
4
5
6
7
8
9
10
11
12
SEN
B
10
Z
GND
9
GND
IO
8
VDD
7
X
QMA7981
Y
TYPE
Function
I
Power
Supply
VDDIO
CMOS
SDX
IO
VDDIO
CMOS
VDDIO
RESV1
INT1
INT2
VDD
GNDIO
GND
SENB
RESV2
SCL
P
I
O
O
P
G
G
IO
IO
I
VDDIO
VDDIO
VDDIO
VDDIO
VDD
GND
GND
VDDIO
VDDIO
VDDIO
Power
CMOS
CMOS
CMOS
Power
Power
Power
CMOS
CMOS
CMOS
LSB of I2C address, or SDO of 4W
SPI
Serial data for I2C, or SDI of 4W
SPI, or SDIO of 3W SPI
Power supply to digital interface
Reserved. Float or connect to GND
Interrupt 1
Interrupt 2
Power supply to internal block
Ground to digital interface
Ground to internal block
Protocol selection
Reserved. Float, or connect to GND
Serial clock for I2C, or Serial clock
for SPI
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reproduced, or disclosed in whole or in part without prior written permission of QST.
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Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
3.2 Package Outlines
3.2.1
Package Type
LGA (Land Grid Array)
3.2.2
Package Outline Drawing:
2.0mm (Length)*2.0mm (Width)*0.95mm (Height)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETER.
Figure 3.
Package Outline Drawing
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reproduced, or disclosed in whole or in part without prior written permission of QST.
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Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
3.2.3
Marking:
Figure 4.
Marking Format
Marking Text
Description
Comments
Line 1
Y: year code
CCC: lot code
Line 2
S: Sub-con ID
P: Part number
7: Fixed number
year code: 1 character
Lot code: 3 alphanumeric digits, variable to generate mass
production trace-code
S: 1 alphanumeric digit, variable identify sub-con
P: 1 alphanumeric digit, variable to identify part number
7: “7” stand for product name QMA7981
Pin 1 identifier
--
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reproduced, or disclosed in whole or in part without prior written permission of QST.
9 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
4
4.1
EXTERNAL CONNECTION
I2C Dual Supply Connection
Digital Power
1.71~VDD
Power
2.2Kohm
SCL
SDA
SDX
VDD
IO
RES
V1
INT
1
RES
V2
QMA7981
SCX
Top View
2.2Kohm
AD0
INT
2
C3, 10nF
SEN
B
GND
GND
IO
Analog Power
1.71~3.6V
VDD
C1, 0.1uF
C2, 2.2uF
Interrupt
Figure 5.
4.2
I2C Dual Supply Connection
I2C Single Supply connection
Power
1.71~3.6V
Power
2.2Kohm
SCL
SDA
SDX
VDD
IO
RES
V1
INT
1
RES
V2
QMA7981
SCX
Top View
2.2Kohm
AD0
INT
2
C3, 10nF
SEN
B
GND
GND
IO
VDD
C1, 0.1uF
C2, 2.2uF
Interrupt
Figure 6.
I2C Single Supply Connection
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reproduced, or disclosed in whole or in part without prior written permission of QST.
10 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
4.3
SPI Dual Supply Connection
Digital Power
1.71~VDD
Power
CSB
SCK
SDI
SCX
SDX
VDD
IO
Top View
RES
V1
INT
1
SDO
RES
V2
QMA7981
AD0
INT
2
C3, 10nF
SEN
B
GND
GND
IO
Analog Power
1.71~3.6V
VDD
C1, 0.1uF
C2, 2.2uF
Interrupt
Figure 7.
4.4
SPI Dual Supply Connection
SPI Single Supply connection
Power
1.71~3.6V
Power
CSB
SCK
SDI
SCX
SDX
VDD
IO
Top View
RES
V1
INT
1
SDO
RES
V2
QMA7981
AD0
INT
2
C3, 10nF
SEN
B
GND
GND
IO
VDD
C1, 0.1uF
C2, 2.2uF
Interrupt
Figure 8.
SPI Single Supply Connection
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reproduced, or disclosed in whole or in part without prior written permission of QST.
11 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
5 BASIC DEVICE OPERATION
5.1
Acceleration sensor
The QMA7981 acceleration sensor circuit consists of tri-axial sensors and application specific support circuits to measure
the acceleration of device. When a DC power supply is applied to the sensor, the sensor converts any accelerating incident
in the sensitive axis directions to charge output.
5.2
Power Management
Device has two power supply pins. VDD is the main power supply for all of the internal blocks, including analog and digital.
VDDIO is a separate power supply, for digital interface only.
The device contains a power-on-reset generator. It generates reset pulse as power on, which can load the register’s default
value, for the device to function properly.
To make sure the POR block functions well, we should have such constrains on the timing of VDD and VDDIO.
The device should turn-on both power pins in order to operate properly. When the device is powered on, all registers are
reset by POR, then the device transits to the standby mode and waits for further commends.
Table 6 provides references for four power states.
Table 6． Power States
5.3
Power State
1
2
VDD
0V
0V
VDDIO
0V
1.71v~3.6v
3
4
1.71v~3.6v
1.71v~3.6v
0V
1.71v~VDD
Power State description
Device Off, No Power Consumption
Not allowed. User need to make sure that VDDIO is less
than VDD. Otherwise, there will be leakage from VDDIO
to VDD through internal ESD devices
Device Off, Same Current as Standby Mode
Device On, Normal Operation Mode, Enters Standby
Mode after POR
Power On/Off Time
Device has two power supply pins and two ground pins. VDD is the main power supply for all of the internal blocks,
including analog and digital. VDDIO is a separate power supply, for digital interface only. GND is 0V supply for all of internal
blocks, and GNDIO for digital interface.
There is no limitation on the voltage levels of VDD and VDDIO relative to each other, as long as they are within operating
range.
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reproduced, or disclosed in whole or in part without prior written permission of QST.
12 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
The device contains a power-on-reset generator. It generates reset pulse as power on, which can load the register’s default
value, for the device to function properly.
To make sure the POR block functions well, we should have such constrains on the timing of VDD.
The power on/off time related to the device is in Table 7
Table 7. Time Required for Power On/Off
Parameter
POR Completion
Time
Symbol
PORT
Power off Voltage
SDV
Power on Interval
PINT
Power on Time
PSUP
Figure 9.
5.4
Condition
Time Period After VDD and
VDDIO at Operating Voltage to
Ready for I2C Commend and
Analogy Measurement.
Voltage that Device Considers to
be Power Down.
Time Period Required for Voltage
Lower Than SDV to Enable Next
POR
Time Period Required for Voltage
from SDV to 90% of final value
Min.
Typ.
Max.
250
Unit
μs
0.2
V
100
μs
50
ms
Power On/Off Timing
Communication Bus Interface I2C and Its Addresses
This device will be connected to a serial interface bus as a slave device under the control of a master device, such as the
processor. Control of this device is carried out via I²C.
This device is compliant with I²C -Bus Specification, document number: 9398 393 40011. As an I²C compatible device,
this device has a 7-bit serial address and supports I²C protocols. This device supports standard and fast speed modes, 100
kHz and 400 kHz, respectively. External pull-up resistors are required to support all these modes.
There are two I2C addresses selected by connecting pin 1 (AD0) to GND or VDDIO.
configured to “001001” and the LSB can be configured by AD0.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
The first six MSB are hardware
13 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
Table 8.
I2C Address Options
I2C Slave Address(HEX)
12
13
AD0 (pin 1)
Connect to GND
Connect to VDDIO
I2C Slave Address(BIN)
0010010
0010011
6 MODES OF OPERATION
6.1
Modes Transition
QMA7981 has two different operational modes, controlled by register (0x11), MODE_BIT. The main purpose of these modes
is for power management. The modes can be transited from one to another, as shown below, through I 2C commands. The
default mode after power-on is standby mode.
Power Off
Reset
(POR or Soft Reset)
Reset
(POR or Soft Reset)
NVM Load
NVM Load
0x36=0xB6
0x36=0xB6
Standby
Standby
0x11=1
0x11=1
0x33=1
Active
0x33=1
0x11=0
Active
0x11=0
0x36=0xB6
0x36=0xB6
Figure 10.
Basic operation flow after power-on
Figure 11.
The work mode transferring
The default mode after power on is standby mode. Through I2C instruction, device can switch between standby mode and
active mode. With SOFTRESET by writing 0xB6 into register 0x36, all of the registers will get default values. SOFTRESET can
be done both in active mode and in standby mode. Also, by writing 1 in NVM_LOAD (0x33) when device is in active
mode, the NVM related image registers will get default value from NVM, however, other registers will keep the values of
their own.
6.2 Description of Modes
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reproduced, or disclosed in whole or in part without prior written permission of QST.
14 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
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6.2.1
Active Mode
In active mode, the ADC digitizes the charge signals from transducer, and digital signal processor conditions these signals in
digital domain, processes the interrupts, and send data to Data registers (0x01~0x06).
6.2.2
Standby Mode
In standby mode, most of the blocks are off, while device is ready for access through I2C. Standby mode is the default mode
after power on or soft reset. Device can enter into this mode by set the soft reset register (0x36) to 0xB6 or set the
MODE_BIT (0x11) to logic 0.
Besides the above two modes, the device also contains NVM loading state. This state is used to reset the value of the NVM
related image registers. There are two bits related to this state. When NVM_LOAD (0x33) is set to 1, NVM loading starts.
When the device is in NVM loading state, NVM_RDY (0x33) is set to logic 0 by device. After NVM loading is finished,
NVM_RDY (0x33) is set back to logic 1 by device, and NVM_LOAD is reset to 0 by device automatically. NVM loading can
only happen when NVM_LOAD is set to 1 in active mode. If the user sets this NVM_LOAD bit to 1 in standby mode, the
device will not take the action until it enters into active state by setting MODE_BIT (0x11) to logic 1.
After loading NVM, the device will enter into standby mode directly.
The loading time for NVM is about 100uS.
7 Functions and interrupts
ASIC support interrupts, such as STEP_INT, DRDY_INT, ANY_MOT_INT, SIG_MOT_INT, NO_MOT_INT, RAISE_INT, etc.
7.1 STEP_ INT
The STEP/STEP_QUIT detect that the user is entering/exiting step mode. When the user enter into step mode, at least one
axis sensor data will vary periodically, by numbering the variation periods the step counter can be calculated.
Figure 10.
STEP/STEP_QUIT
Median data (max+min) /2 is called dynamic threshold, the max and min data can be updated by certainly samples, the
sample number can be set by register STEP_SAMPLE_CNT (0x12). When the sensor data decreasing (or increasing)
through the dynamic threshold, a user run step is detected.
Register STEP_PRECISION (0x13) is used as threshold when updating the new collected sensor data. Sensor data below
the threshold will be discarded, this helps removing unstable variations causing failed detection.
The run step event happened at certain interval timing. All of the events outside the timing window will not be regarded as
a run step and the step counter will not counted. The timing window can be set by register STEP_TIME_UP(0x15) and
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reproduced, or disclosed in whole or in part without prior written permission of QST.
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Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
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STEP_TIME_LOW(0x14), the conversion ODR numbers ranged from
STEP_TIME_LOW *ODR to 8*
STEP_TIME_UP*ODR .
STEP_COUNT_PEAK is used to set a fixed peak value for step detection, 0.05G~0.4G can be set. STEP_COUNT_P2P
is used to set a peak to peak threshold for step detection, 0.3G~1G can be set.
To remove unstable variation which will cause false STEP event detection, the step counter considers steps as valid step
events only after some continuous steps detected; the start threshold can be set by 0x1F. Also, the step counter
register STEP_CNT ({0x0E,0x08,0x07}) will be updated immediately by the setting number, and interrupt STEP is also
generated.
The related interrupt status bit is STEP_INT (0x0A) and SIG_STEP (0x0A). When the interrupt is generated, the value
of STEP_INT will be set to logic 1, which will be cleared after the interrupt status register is read by user.
STEP_IEN/SIG_STEP_IEN (0x16/0x16) is the enable bit for the STEP_INT/SIG_STEP_INT. Also, to get this interrupt on
PIN_INT1 and/or PIN_INT2, we need to set INT1_STEP (0x19)/INT1_SIG_STEP (0x19)
or INT2_STEP (0x1B)
/INT2_SIG_STEP (0x1B) to logic 1, to map the internal interrupt to the interrupt PINs.
7.2 DRDY_INT
The width of the acceleration data is 14 bits, in two’s complement representation. The data of each axis is split into 2 parts,
the MSB part (one byte contains bit 13 to bit 6) and the LSB part (one byte contains bit 5 to bit 0). Reading data should start
with LSB part. When user is reading the LSB byte of data, to ensure the integrity of the acceleration data, the content of
MSB can be locked, by setting SHADOW_DIS (0x21) to logic 0. This lock function can be disabled by setting SHADOW_DIS
to logic 1. Without lock, the MSB and LSB content will be updated by new value immediately. The bit NEW_DATA in the LSB
byte is the flag of the new data. If new data is updated, this NEW_DATA flag will be 1, and will be cleared when
corresponding MSB or LSB is read by user.
Also, the user should note that even with SHADOW_DIS=0, the data of 3 axes are not guaranteed from the same time point.
The device supports four different acceleration measurement ranges. The range is setting through RANGE (0x0F), and
the details as following:
Acceleration
RANGE
Resolution
range
0001
2g
244ug/LSB
0010
4g
488ug/LSB
0100
8g
977ug/LSB
1000
16g
1.95mg/LSB
1111
32g
3.91mg/LSB
Others
2g
244ug/LSB
The interrupt for the new data serves for the synchronous data reading for the host. It is generated after storing a new
value of z-axis acceleration data into data register. This interrupt will be cleared automatically when the next data
conversion cycle starts, and the interrupt will be effective about 64*MCLK, and automatically cleared.
The interrupt mode for the new data is fixed to be non-latched.
7.3 ANY_MOT_INT
Any motion Any motion detection uses slope between two successive data to detect the changes in motion. It generates
interrupt when a preset threshold ANY_MOT_TH (0x2E) is exceeded.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
16 / 30
Document #:
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Rev: D
矽睿
The time difference between two successive data depends on the output data rate (ODR).
Slope(t1) = (𝑎𝑐𝑐(𝑡1) − 𝑎𝑐𝑐(𝑡0)) ∗ 𝑂𝐷𝑅
The any motion detection criteria are fulfilled and interrupt is generated if any of enabled channels exceeds ANY_MOT_TH
for ANY_MOT_DUR (0x2C) consecutive times.
As long as all the enabled channels data fall or stay below ANY_MOT_TH for ANY_MOT_DUR consecutive times, the
interrupt will be reset unless the interrupt signal is latched.
The any motion detection engine will send out the signals of axis which triggered the interrupt (ANY_MOT_FIRST_X
(0x09), ANY_MOT_FIRST_Y (0x09), ANY_MOT_FIRST_Z (0x09)) and the sign of the motion (ANY_MOT_SIGN
(0x09))
7.4 SIG_MOT_INT
A significant motion is a motion due to a change in user location.
The algorithm is as following:
1) Look for movement, same setting as any motion detection
2) If movement detected, sleep for T_Skip (0x2F)
3) Look for movement
a) If no movement detected within T_Proof (0x2F), go back to 1
b) If movement detected, report a significant movement, and generate the interrupt
The significant motion detection and any motion detection are exclusive, user can select either one through SIG_MOT_SEL
(0x2F).
If significant motion is detected, the engine will set SIG_MOT_INT (0x0A).
7.5 NO_MOT_INT
No-motion interrupt is generated if the slope (absolute value of acceleration difference) on all selected axes is smaller than
the programmable threshold for a programmable time. Figure shows the timing for the no-motion interrupt. Register (0x2C)
NO_MOT_DUR defines the delay times before the no-motion interrupt is generated. Table lists the delay times adjustable
with register (0x2C) NO_MOT_DUR.
The no-motion interrupt is enabled per axis by writing logic 1 to bits (0x18) NO_MOTION_EN_X, (0x18) NO_MOTION_EN_Y,
and (0x18) NO_MOTION_EN_Z, respectively. The no-motion threshold is set through the (0x2D) NO_MOT_TH register. The
meaning of an LSB of (0x2D) NO_MOT_TH depends on the selected g-range: it corresponds to 3.91mg in 2g-range (7.81mg
in 4g-range, 15.6mg in 8g-range, 31.25mg in 16g-range, 62.5mg in 32g-range). Therefore the maximum value is 996mg in
2g-range (2g in 4g-range, 4g in 8g-range, 8g in 16g-range, and 16g in 32g-range). The time difference between the
successive acceleration samples depends on the selected ODR and equates to 1/ODR.
7.6 RAISE_INT
Raise wake algorithm is used to detect the action of raise hand (or hand down). The interrupt is enabled by writing logic 1 to
bits (0X16[1]) RAISE_EN, (0X16[2]) HD_EN. User can adjust the sensitivity through the registers. The register
RAISE_WAKE_SUM_TH(0X2A[5:0]) defines the strength of hand action (raise and down). The register
RAISE_DIFF_TH(0X2A[7:6],0X2B[1:0]) defines the differential values of twice actions, when the hand behavior almost done
the differential value will be smaller and we can use this register to set the threshold. RAISE_WAKE_PERIOD and
RAISE_WAKE_TIMEOUT_TH define the duration of the total hand action.
7.7 Interrupt configuration
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
17 / 30
Document #:
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Rev: D
矽睿
The device has the above 3 interrupt engines. Each of the interrupts can be enabled and configured independently. If the
trigger condition of the enabled interrupt fulfilled, the corresponding interrupt status bit will be set to logic 1, and the
mapped interrupt pin will be activated. The device has two interrupt PINs, INT1 and INT2. Each of the interrupts can be
mapped to either PIN or both PINs.
The interrupt status registers INT_ST(0x09~0x0d) will update when a new data word is written into the data registers. If an
interrupt is disabled, the related active interrupt status bit is disabled immediately.
When interrupt condition is fulfilled, related bit of interrupt will be set, until the associated interrupt condition is no more
valid. Read operation to related register will also clear the register.
Device supports 2 interrupt modes, non-latched, and latched mode. The interrupt modes are set through LATCH_INT
(0x21).
In non-latched mode, the mapped interrupt pin will be set and/or cleared same as associated interrupt register bit. Also, the
mapped interrupt pin can be cleared with read operation to any of the INT_ST(0x09~0x0d).
Exception to this is the new data interrupt and step interrupt, which are automatically reset after a fixed time (T_Pulse =
64/MCLK), no matter LATCH_INT (0x21) is set to 0 or 1.
In latched mode, the clearings of mapped pins are determined by INT_RD_CLR (0x21).
If the condition for trigging the interrupt still holds, the interrupt status will be set again with the next change of the data
registers.
Mapping the interrupt pins can be set by INT_MAP (0x19~0x1B).
The electrical interrupt pins can be set INT_PIN_CONF (0x20). The active logic level can be set to 1 or 0, and the
interrupt pin can be set to open-drain or push-pull.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
18 / 30
Document #:
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Rev: D
矽睿
8 I2C COMMUNICATION PROTOCOL
8.1
I2C Timings
Table 9 and Figure 11 describe the I2C communication protocol times
Table 9.
I2C Timings
Parameter
SCL Clock
SCL Low Period
SCL High Period
SDA Setup Time
SDA Hold Time
Start Hold Time
Start Setup Time
Stop Setup Time
New Transmission
Time
Rise Time
Fall Time
Figure 11.
t sudat
t hddat
t hdsta
t susta
t susto
t buf
Condition
Min.
0
1
1
0.1
0
0.6
0.6
0.6
1.3
Typ.
Max.
400
Unit
kHz
μs
μs
0.9
tr
tf
μs
μs
μs
μs
μs
μs
μs
μs
I2C Timing Diagram
8.2
I2C R/W Operation
8.2.1
Abbreviation
Table 10.
Symbol
fscl
t low
t high
Abbreviation
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
19 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
SACK
MACK
NACK
RW
8.2.2
Acknowledged by slave
Acknowledged by master
Not acknowledged by master
Read/Write
Start/Stop/Ack
START: Data transmission begins with a high to transition on SDA while SCL is held high. Once I 2C transmission starts, the
bus is considered busy.
STOP: STOP condition is a low to high transition on SDA line while SCL is held high.
ACK: Each byte of data transferred must be acknowledged. The transmitter must release the SDA line during the
acknowledge pulse while the receiver mush then pull the SDA line low so that it remains stable low during the high period
of the acknowledge clock cycle.
NACK: If the receiver doesn’t pull down the SDA line during the high period of the acknowledge clock cycle, it’s recognized
as NACK by the transmitter.
8.2.3
I2C Write
I C write sequence begins with start condition generated by master followed by 7 bits slave address and a write bit (R/W=0).
The slave sends an acknowledge bit (ACK=0) and releases the bus. The master sends the one byte register address. The
slave again acknowledges the transmission and waits for 8 bits data which shall be written to the specified register address.
After the slave acknowledges the data byte, the master generates a stop signal and terminates the writing protocol.
2
Table 11.
I2C Write
Slave Address
STOP
Data
(0x80)
1 0 0 0 0 0 0 0
SACK
Register Address
(0x11)
0 0 0 1 0 0 0 1
SACK
8.2.4
SACK
START
R
W
0 0 1 0 0 1 0 0
I2C Read
I C write sequence consists of a one-byte I2C write phase followed by the I2C read phase. A start condition must be
generated between two phase. The I 2C write phase addresses the slave and sends the register address to be read. After
slave acknowledges the transmission, the master generates again a start condition and sends the slave address together
with a read bit (R/W=1). Then master releases the bus and waits for the data bytes to be read out from slave. After each
data byte the master has to generate an acknowledge bit (ACK = 0) to enable further data transfer. A NACK from the master
stops the data being transferred from the slave. The slave releases the bus so that the master can generate a STOP
condition and terminate the transmission.
The register address is automatically incremented and more than one byte can be sequentially read out. Once a new data
read transmission starts, the start address will be set to the register address specified in the current I 2C write command.
2
Table 12.
I2C Read
SACK
MACK
Data
(0x00)
0 0 0 0 0 0 1 0
Slave Address
START
R
W
0 0 1 0 0 1 0 1
Register Address
(0x00)
0 0 0 0 0 0 0 0
SACK
START
R
W
0 0 1 0 0 1 0 0
SACK
Slave Address
Data
(0x01)
0 0 0 0 0 0 0 0
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
20 / 30
Document #:
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Rev: D
矽睿
……………………………….
STOP
Data
(0x07)
0 0 0 0 0 0 0 0
NACK
……………………………….
MACK
MACK
MACK
Data
(0x02)
0 0 0 0 0 0 1 0
9 REGISTERS
9.1
Register Map
The table below provides a list of the 8-bit registers embedded in the device and their respective function and addresses
Table 13. Register Map
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
21 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
9.2
Register Definition
Register 0x00 (CHIP ID)
Bit7
Bit6
Bit5
CHIP_ID
This register is used to identify the device
Register 0x01 ~ 0x02 (DXL, DXM)
Bit7
Bit6
Bit5
DX
DX
DX:
NEWDATA_X:
Bit2
Bit1
Bit0
R/W
RW
Default
0xEX
Bit4
Bit3
Bit2
Bit1
Bit0
NEWDATA
_X
R/W
R
Default
0x00
R
0x00
R/W
R
Default
0x00
R
0x00
R/W
R
Default
0x00
R
0x00
R/W
R
R
Default
0x00
0x00
Bit4
Bit3
Bit2
Bit1
Bit0
NEWDATA
_Y
14bits acceleration data of y-channel. This data is in two’s complement.
1, acceleration data of y-channel has been updated since last reading
0, acceleration data of y-channel has not been updated since last reading
Register 0x05 ~ 0x06 (DZL, DZM)
Bit7
Bit6
Bit5
DZ
DZ
DZ:
NEWDATA_Z:
Bit3
14bits acceleration data of x-channel. This data is in two’s complement.
1, acceleration data of x-channel has been updated since last reading
0, acceleration data of x-channel has not been updated since last reading
Register 0x03 ~ 0x04 (DYL, DYM)
Bit7
Bit6
Bit5
DY
DY
DY:
NEWDATA_Y:
Bit4
Bit4
Bit3
Bit2
Bit1
Bit0
NEWDATA
_Z
14bits acceleration data of z-channel. This data is in two’s complement.
1, acceleration data of z-channel has been updated since last reading
0, acceleration data of z-channel has not been updated since last reading
Register 0x07 ~ 0x08 (STEP_CNT)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
STEP_CNT
STEP_CNT
STEP_CNT:
16 bits of step counter, out of total 24bits data. The MSB data are in 0x0e
Register 0x09 (INT_ST0)
Bit7
Bit6
NO_MOT
SIG_STEP
Bit5
Bit4
Bit3
ANY_MOT
_SIGN
Bit2
ANY_MOT
_FIRST_Z
Bit1
ANY_MOT
_FIRST_Y
Bit0
ANY_MOT
_FIRST_X
R/W
R
Default
0x00
Bit1
Bit0
R/W
Default
NO_MOT:
1, no_motion interrupt active
0, no_motion interrupt inactive
ANY_MOT_SIGN:
1, sign of any_motion triggering signal is negative
0, sign of any_motion triggering signal is positive
ANY_MOT_FIRST_Z:
1, any_motion interrupt is triggered by Z axis
0, any_motion interrupt is not triggered by Z axis
ANY_MOT_FIRST_Y:
1, any_motion interrupt is triggered by Y axis
0, any_motion interrupt is not triggered by Y axis
ANY_MOT_FIRST_X:
1, any_motion interrupt is triggered by X axis
0, any_motion interrupt is not triggered by X axis
Register 0x0a (INT_ST1)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
22 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
SIG_STEP
SIG_STEP:
HD_INT
RAISE_INT
SIG_MOT_I
NT
R
0x00
Bit2
Bit1
Bit0
R/W
R
Default
0x00
Bit2
Bit1
Bit0
R/W
R
8bit MSB data of step counter, out of total 24bits data. The LSB data are in 0x07 and 0x08
Default
0x00
Bit5
Bit4
Bit3
Bit2
Bit1
1
RANGE
set the full scale of the accelerometer. Setting as following
Bit0
R/W
RW
Default
0xF0
1, significant step is active
0, significant step is inactive
1, step valid interrupt is active
0, step quit interrupt is inactive
1, hand down interrupt is active
0, hand down interrupt is inactive
1, raise hand interrupt is active
0, raise hand interrupt is inactive
1, significant interrupt is active
0, significant interrupt is inactive
STEP_INT:
HD_INT:
RAISE_INT:
SIG_MOT_INT:
Register 0x0b (INT_ST2)
Bit7
Bit6
DATA_INT:
Register 0x0e (STEP_CNT)
Bit7
Bit6
STEP_CNT
STEP_CNT:
Register 0x0f (FSR)
Bit7
Bit6
1
1
RANGE:
RANGE
0001
0010
0100
1000
1111
Others
STEP_INT
Bit5
Bit4
Bit3
DATA_INT
1, data ready interrupt active
0, data ready interrupt inactive
Bit5
Acceleration range
2g
4g
8g
16g
32g
2g
Register 0x10 (BW)
Bit7
Bit6
1
1
BW:
BW
xx000
xx001
xx010
xx011
xx100
xx101
xx110
xx111
Others
Register 0x11 (PM)
Bit7
Bit6
MODE_BIT
1
MODE_BIT:
Bit4
Bit3
Resolution
244ug/LSB
488g/LSB
977ug/LSB
1.95mg/LSB
3.91mg/LSB
244ug/LSB
Bit5
Bit4
Bit3
1
BW
bandwidth setting, as following
Bit2
Bit1
Bit0
R/W
RW
Default
0xE0
Bit5
Bit4
Bit3
Bit2
T_RSTB_SINC_SEL
MCLK_SEL
1, set device into active mode
0, set device into standby mode
Bit1
Bit0
R/W
RW
Default
0x40
ODR
MCLK/7695
MCLK/3855
MCLK/1935
MCLK/975
MCLK/15375
MCLK/30735
MCLK/61455
MCLK/7695
T_RSTB_SINC_SEL: Reset clock setting. The preset time is reserved for CIC filter in digital
11, T_RSTB_SINC=8*MCLK
10, T_RSTB_SINC=6*MCLK
01, T_RSTB_SINC=4*MCLK
00, T_RSTB_SINC=3*MCLK
MCLK_SEL:
set the master clock to digital
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
23 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
MCLK_SEL
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
Freq of MCLK
500KHz
333KHz
200KHz
100KHz
50KHz
25KHz
12.5KHz
5KHz
Reserved
Register 0x12 (STEP_CONF0)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Default
STEP_EN
STEP_SAMPLE_CNT
RW
0x14
STEP_EN:
enable step counter, this bit should be set when using step counter
STEP_SAMPLE_CNT:
sample count setting for dynamic threshold calculation. The actual value is STEP_SAMPLE_CNT*8, default is 0xC, 96 sample
count
Register 0x13 (STEP_CONF1)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Default
STEP_CLR
STEP_PRECISION
RW
0x7F
STEP_CLR:
clear step count in register 0x07 ,0x08 and 0x0E
STEP_PRECISION:
threshold for acceleration change of two successive sample which is used to update sample_new register in step counter, the actual g
value is STEP_PRECISION*LSB*16 when STEP_PRECISION!=0000000 & !=1111111
When STEP_PRECISION=0000000, always use P2P/8
When STEP_PRECISION=1111111, always use P2P/16
When STEP_PRECISION=?, always use P2P/4
Register 0x14 (STEP_CONF2)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
STEP_TIME_LOW
RW
STEP_TIME_LOW:
the short time window for a valid step, the actual time is STEP_TIME_LOW*(1/ODR)
Default
0x19
Register 0x15 (STEP_CONF3)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
STEP_TIME_UP
RW
STEP_TIME_UP:
time window for quitting step counter, the actual time is STEP_TIME_UP*8*(1/ODR)
Default
0x00
Register 0x16 (INT_EN0)
Bit7
Bit6
1
SIG_STEP_I
EN
SIG_STEP_IEN:
STEP_IEN:
HD_EN:
RAISE_EN:
Register 0x17 (INT_EN1)
Bit7
Bit6
1
1
INT_DATA_EN:
Bit5
1
Bit4
1
Bit3
STEP_IEN
Bit2
HD_EN
Bit1
RAISE_EN
Bit0
1
R/W
RW
Default
0xB1
Bit2
Bit1
Bit0
R/W
RW
Default
0xE0
1, enable significant step interrupt
0, disable significant step interrupt
1, enable step valid interrupt
0, disable step valid interrupt
1, enable hand-down interrupt
0, disable hand-down interrupt
1, enable raise-hand interrupt
0, disable raise-hand interrupt
Bit5
1
Bit4
Bit3
INT_DATA
_EN
1, enable data ready interrupt
0, disable data ready interrupt
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
24 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
Register 0x18 (INT_EN2)
Bit7
Bit6
NO_MOT_
NO_MOT_
EN_Z
EN_Y
NO_MOT_EN_Z:
NO_MOT_EN_Y:
NO_MOT_EN_X:
ANY_MOT_EN_Z:
ANY_MOT_EN_Y:
ANY_MOT_EN_X:
Register 0x19 (INT_MAP0)
Bit7
Bit6
1
INT1_SIG_
STEP
INT1_SIG_STEP:
Bit5
Bit4
Bit3
Bit2
NO_MOT_
1
1
ANY_MOT
EN_X
_EN_Z
1, enable no_motion interrupt on Z axis
0, disable no_motion interrupt on Z axis
1, enable no_motion interrupt on Y axis
0, disable no_motion interrupt on Y axis
1, enable no_motion interrupt on X axis
0, disable no_motion interrupt on X axis
1, enable any_motion interrupt on Z axis
0, disable any_motion interrupt on Z axis
1, enable any_motion interrupt on Y axis
0, disable any_motion interrupt on Y axis
1, enable any_motion interrupt on X axis
0, disable any_motion interrupt on X axis
Bit1
ANY_MOT
_EN_Y
Bit0
ANY_MOT
_EN_X
R/W
RW
Default
0x18
Bit5
1
Bit1
INT1_RAIS
E
Bit0
INT1_SIG_
MOT
R/W
RW
Default
0xB0
Bit1
1
Bit0
INT1_ANY_
MOT
R/W
RW
Default
0x62
Bit4
1
Bit3
INT1_STEP
Bit2
INT1_HD
1, map significant step interrupt to INT1 pin
0, not map significant step interrupt to INT1 pin
INT1_STEP:
1, map step valid interrupt to INT1 pin
0, not map step valid interrupt to INT1 pin
INT1_HD:
1, map hand down interrupt to INT1 pin
0, not map hand down interrupt to INT1 pin
INT1_RAISE:
1, map raise hand interrupt to INT1 pin
0, not map raise hand interrupt to INT1 pin
INT1_SIG_MOT:
1, map significant interrupt to INT1 pin
0, not map significant interrupt to INT1 pin
Register 0x1a (INT_MAP1)
Bit7
Bit6
INT1_NO_
1
MOT
INT1_NO_MOT:
INT1_DATA:
INT1_ANY_MOT:
Register 0x1b (INT_MAP2)
Bit7
Bit6
1
INT2_SIG_S
TEP
INT2_SIG_STEP:
INT2_STEP:
INT2_HD:
INT2_RAISE:
INT2_SIG_MOT:
Bit5
1
Bit4
Bit3
Bit2
INT1_DAT
A
1, map no_motion interrupt to INT1 pin
0, not map no_motion interrupt to INT1 pin
1, map data ready interrupt to INT1 pin
0, not map data ready interrupt to INT1 pin
1, map any motion interrupt to INT1 pin
0, not map any motion interrupt to INT1 pin
Bit5
1
Bit4
1
Bit3
INT2_STEP
Bit2
INT2_HD
Bit1
INT2_RAISE
Bit0
INT2_SI
G_MOT
R/W
RW
Default
0xB0
1, map significant step interrupt to INT2 pin
0, not map significant step interrupt to INT2 pin
1, map step valid interrupt to INT2 pin
0, not map step valid interrupt to INT2 pin
1, map hand down interrupt to INT2 pin
0, not map hand down interrupt to INT2 pin
1, map raise hand interrupt to INT2 pin
0, not map raise hand interrupt to INT2 pin
1, map significant interrupt to INT2 pin
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
25 / 30
Document #:
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Rev: D
矽睿
0, not map significant interrupt to INT2 pin
Register 0x1c (INT_MAP3)
Bit7
Bit6
INT2_NO_
1
MOT
INT2_NO_MOT:
INT2_DATA:
INT2_ANY_MOT:
Register 0x1d (SIG_STEP_TH)
Bit7
Bit6
STEP_INTERVAL
STEP_INTERVAL :
Bit5
1
Bit4
Bit3
Bit2
INT2_DAT
A
1, map no_motion interrupt to INT2 pin
0, not map no_motion interrupt to INT2 pin
1, map register data ready interrupt to INT2 pin
0, not map register data ready interrupt to INT2 pin
1, map any motion interrupt to INT2 pin
0, not map any motion interrupt to INT2 pin
Bit5
Bit4
Bit3
Register 0x1f
Bit7
Bit6
STEP_START_CNT
STEP_START_CNT:
STEP_COUNT_PEAK:
STEP_COUNT_P2P:
DIS_IE_AD0:
EN_SPI3W:
STEP_COUNT_PEAK:
INT2_OD:
INT2_LVL:
INT1_OD:
INT1_LVL:
Register 0x21 (INT_CFG)
Bit7
Bit6
INT_RD_CL SHADOW_
R
DIS
INT_RD_CLR:
SHADOW_DIS:
Bit2
Bit1
Bit1
Bit5
Bit4
Bit3
Bit2
Bit1
STEP_COUNT_PEAK
STEP_COUNT_P2P
th_step_pattern = 0/4/8/12/16/24/32/40
FIXED_PEAK = 0.05g + 0.05g * STEP_COUNT_PEAK.
This FIXED_PEAK is used in algorithm of STEP COUNTER.
STEP_COUNT_PEAK is in register 0x20 and
STEP_COUNT_PEAK[2:0]= {0x20[4], 0x1F[4:3]}
FIXED_P2P = 0.3g + 0.1g * STEP_COUNT_P2P.
STEP_COUNT_P2P[3:0]= {0x1F[2:0]}
Register 0x20 (INTPIN_CONF)
Bit7
Bit6
Bit5
DIS_PU_SE
DIS_IE_AD
EN_SPI3W
NB
0
DIS_PU_SENB:
Bit0
INT2_ANY_
MOT
R/W
RW
Default
0x62
R/W
Default
RW
0x00
threshold of significant step. When MOD(STEP_CNT, STEP_INTERVAL)=0, SIG_STEP_INT will be generated.
Register 0x1e (raise hand: X_TH Z_TH)
Bit7
Bit6
Bit5
Bit4
Bit3
Z_TH
X_TH
X_TH:
0~7.5, LSB 0.5 (unit : m/s2)
Z_TH:
-8~7, LSB 1 (unit : m/s2)
Bit2
Bit1
1
Bit4
Bit3
STEP_COU
INT2_OD
NT_PEAK<
2>
1, disable pull-up resistor of PIN_SENB
0, enable pull-up resistor of PIN_SENB
1, disable input of AD0
0, not disable input of AD0
1, enable 3W SPI
0, 4W SPI
Definition in 0x1F
1, open-drain for INT2 pin
0, push-pull for INT2 pin
1, logic high as active level for INT2 pin
0, logic low as active level for INT2 pin
1, open-drain for INT1 pin
0, push-pull for INT1 pin
1, logic high as active level for INT1 pin
0, logic low as active level for INT1 pin
Bit5
DIS_I2C
Bit4
1
Bit3
1
Bit2
INT2_LVL
Bit1
INT1_OD
Bit0
Bit0
R/W
RW
Default
0x66
Bit0
R/W
RW
Default
0xA9
Bit0
INT1_LVL
R/W
RW
Default
0x05
Bit2
1
Bit1
Bit0
R/W
Default
LATCH_INT LATCH_INT RW
0x1C
_STEP
1, clear all the interrupts in latched-mode, when any read operation to any of registers from 0x09 to 0x0D
0, clear the related interrupts, only when read the register INT_ST (0x09 to 0x0D),
no matter the interrupts in latched-mode, or in non-latched-mode.
Reading 0x09 will clear the register 0x09 only and the others keep the status
1, disable the shadowing function for the acceleration data
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
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Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
DIS_I2C:
LATCH_INT_STEP:
LATCH_INT:
0, enable the shadowing function for the acceleration data.
when shadowing is enabled, the MSB of the acceleration data is locked,
when corresponding LSB of the data is reading.
This can ensure the integrity of the acceleration data during the reading.
The MSB will be unlocked when the MSB is read.
1: disable I2C. Setting this bit to 1 in SPI mode is recommended
0: enable I2C
1, step related interrupt is in latch mode
0, step related interrupt is in non-latch mode
1, interrupt is in latch mode
0, interrupt is in non-latch mode
Register 0x27 (OS_CUST_X)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Default
OS_CUST_X
RW
0x00
OS_CUST_X:
offset calibration of X axis for user, the LSB depends on full-scale of the device which is 3.9mg in 2g range,
7.8mg in 4g range, 15.6mg in 8g range, 31.2mg in 16g, and 62.5mg in 32g
Register 0x28 (OS_CUST_Y)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Default
OS_CUST_Y
RW
0x00
OS_CUST_Y:
offset calibration of Y axis for user, the LSB depends on full-scale of the device which is 3.9mg in 2g range,
7.8mg in 4g range, 15.6mg in 8g range, 31.2mg in 16g, and 62.5mg in 32g
Register 0x29 (OS_CUST_Z)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Default
OS_CUST_Z
RW
0x00
OS_CUST_Z:
offset calibration of Z axis for user, the LSB depends on full-scale of the device which is 3.9mg in 2g range,
7.8mg in 4g range, 15.6mg in 8g range, 31.2mg in 16g, and 62.5mg in 32g
Register 0x2a (RAISE_WAKE_SUM_TH RAISE_WAKE_DIFF_TH)
Bit7
Bit6
Bit5
Bit4
Bit3
RAISE_WAKE_DIFF_TH
RAISE_WAKE_SUM_TH : 0 ~ 31.5 (LSB 0.5 m/s2)
RAISE_WAKE_DIFF_TH
0
1
2
3
4
5
6
7
8
9
10
default
Bit1
Bit0
Bit2
Bit1
Bit0
RAISE_WAKE_DIFF_TH
R/W
RW
Default
0xD8
R/W
RW
Default
0x7C
UNIT (m/s2)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.2
Register 0x2b (RAISE_WAKE_DIFF_TH HD_X_TH HD_Z_TH)
Bit7
Bit6
Bit5
Bit4
Bit3
HD_Z_TH
HD_X_TH
HD_X_TH :
HD_Z_TH :
Bit2
hand down x threshold, 0~7 (m/s2)
hand down z threshold, 0~7 (m/s2)
Register 0x2c (MOT_CONF0)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Default
NO_MOT_DUR
ANY_MOT_DUR
RW
0x00
NO_MOT_DUR:
no motion interrupt will be triggered when slope < NO_MOT_TH for the times which defined by NO_MOT_DUR
Duration = (NO_MOT_DUR + 1) * 1s, if NO_MOT_DUR =b00
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
27 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
ANY_MOT_DUR:
Duration = (NO_MOT_DUR + 4) * 5s, if NO_MOT_DUR =b01
Duration = (NO_MOT_DUR + 10) * 10s, if NO_MOT_DUR =b1x
any motion interrupt will be triggered when slope > ANY_MOT_TH for (ANY_MOT_DUR + 1) samples
Register 0x2d (MOT_CONF1)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
NO_MOT_TH
NO_MOT_TH:
Threshold of no-motion interrupt. The threshold definition is as following
TH= NO_MOT_TH * 16 * LSB
R/W
RW
Default
0x00
R/W
RW
Default
0x00
Bit0
SIG_MOT_
SEL
R/W
RW
Default
0x00
Bit0
ANY_MOT
_RST_N
R/W
RW
Default
0x1F
Register 0x2e (MOT_CONF2)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ANY_MOT_TH
ANY_MOT_TH:
Threshold of any motion interrupt. The threshold definition is as following
TH= ANY_MOT_TH * 16 * LSB
Register 0x2f (MOT_CONF3)
Bit7
Bit6
Bit5
Bit4
SIG_MOT_TPROOF
SIG_MOT_TPROOF:
SIG_MOT_TSKIP:
SIG_MOT_SEL:
Register 0x30
Bit7
Bit6
MO_BP_C
STEP_BP_C
O
O
MO_BP_CO:
Bit3
Bit2
SIG_MOT_TSKIP
Bit1
00, T_PROOF=0.25s
01, T_PROOF=0.5s
10, T_PROOF=1s
11, T_PROOF=2s
00, T_SKIP=1.5s
01, T_SKIP=3s
10, T_SKIP=6s
11, T_SKIP=12s
1, select significant motion interrupt
0, select any motion interrupt
NO_MOT_RST_N:
Bit2
Bit1
NO_MOT_
SIG_MOT_
RST_N
RST_N
1, motion detector will use data without OS_CUST
0, motion detector will use data with OS_CUST
1, pedometer will use data without OS_CUST
0, pedometer will use data with OS_CUST
0, Reset no motion detector. After reset, user should write 1 back.
SIG_MOT_RST_N:
0, Reset significant motion detector. After reset, user should write 1 back.
ANY_MOT_RST_N:
0, Reset any motion detector. After reset, user should write 1 back.
STEP_BP_CO:
Register 0x32 (ST)
Bit7
Bit6
SELFTEST_
BIT
SELFTEST_BIT:
SELFTEST_SIGN:
BP_AXIS_STEP:
Bit5
Bit5
Bit4
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
SELFTEST_
BP_AXIS_STEP
RW
SIGN
1, self-test enabled. When self-test enabled, a delay of 3ms is necessary for the value settling.
0, normal
1, set self-test excitation positive
0, set self-test excitation negative
11, bypass Z axis, use only X and Y axes data for step counter algorithm
10, bypass Y axis, use only X and Z axes data for step counter algorithm
01, bypass X axis, use only Y and Z axes data for step counter algorithm
00, use all of 3 axes data for step counter algorithm
Register 0x34 (Y_TH YZ_TH_SEL)
Bit7
Bit6
Bit5
Bit4
YZ_TH_SEL
Y_TH
Y_TH: -16 ~ 15 (m/s2)
YZ_TH_SEL
UNIT (m/s2)
Bit3
Bit3
Bit2
Bit1
Bit0
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
R/W
RW
Default
0x00
Default
0x9D
28 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
0
1
2
3
4
5
6
7
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
Register 0x35 (RAISE_WAKE_PERIOD)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RAISE_WAKE_PERIOD
RAISE_WAKE_PERIOD: * ODR period = wake count (EX. ODR = 1ms, 0X35 = 100 ➔ wake count = 0.1 sec)
R/W
RW
Default
0x81
Register 0x36 (SR)
Bit7
Bit6
SOFT_RESET
SOFT_RESET:
R/W
RW
Default
0x00
R/W
RW
Default
0x00
Register 0x3f (RAISE_WAKE_TIMEOUT_TH RAISE_WAKE_PERIOD RAISE_WAKE_EN)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
RAISE_WAKE_PERIOD
RAISE_WAKE_TIMEOUT_TH
RW
RAISE_WAKE_TIMEOUT_TH * ODR period = timeout count (EX. ODR = 1ms, 0X3e = 100 ➔ timeout count = 0.1 sec)
Default
0x02
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0xB6, soft reset all of the registers. After soft-reset, user should write 0x00 back
Register 0x3e (RAISE_WAKE_TIMEOUT_TH)
Bit7
Bit6
Bit5
Bit4
RAISE_WAKE_TIMEOUT_TH
Bit3
Bit2
Bit1
Bit0
ORDERING INFORMATION
Ordering Number
Temperature Range
Package
Packaging
QMA7981-TR
-40℃~85℃
LGA-12
Tape and Reel: 5k pieces/reel
FIND OUT MORE
For more information on QST’s Accelerometer Sensors contact us at 86-21-50497300.
The application circuits herein constitute typical usage and interface of QST product. QST does not provide warranty or assume
liability of customer-designed circuits derived from this description or depiction.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
29 / 30
Document #:
13-52-12 Title: QMA7981 Datasheet
Rev: D
矽睿
QST reserves the right to make changes to improve reliability, function or design. QST does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights
nor the rights of others.
ISO9001 : 2015
China Patents 201510000399.8, 201510000425.7, 201310426346.3, 201310426677.7, 201310426729.0, 201210585811.3 and
201210553014.7 apply to the technology described.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
30 / 30
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