AZC199-04S.R7G

AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port Features Description ESD Protect for 4 high-speed I/O lines and one VDD line
Provide ESD protection for each line to AZC199-04S is a design which includes ESD rated diode arrays to protect high speed data interfaces. The AZC199-04S has been specifically designed to protect sensitive components which are connected to data and transmission lines from over-voltage caused by Electrostatic Discharging (ESD). AZC199-04S is a unique design which includes ESD rated, low capacitance steering diodes and a unique design of clamping cell which is an equivalent TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the power supply line or to ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. Besides, there is a back-drive protection design in AZC199-04S for power-down mode operation. AZC199-04S may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge). One AZC199-04S can be used to replace 4 BAV99 devices in a 5V application or a lower than 5V application.
IEC 61000-4-2,(ESD) ±27kV (air), ±16kV (contact) IEC 61000-4-4 (EFT) Level-3, 55A (5/50ns) IEC 61000-4-5 (Lightning) 6A (8/20µs) For low operating voltage applications: 5V, 4.2V, 3.3V, 2.5V etc.
Low capacitance : 1.0pF typical
Fast turn-on and Low clamping voltage
Array of ESD rated diodes with internal equivalent TVS diode
Solid-state silicon-avalanche and active circuit triggering technology
Back-drive protection for power-down mode
Lead-free version available
Green part
Applications Video Graphics Cards Digital Visual Interface (DVI)
USB2.0 Power and Data lines protection
Notebook and PC Computers
Monitors and Flat Panel Displays

Circuit Diagram Pin Configuration 5 1 3 4 I/O 4 VDD I/O 3 6 5 4 6 2 1 I/O 1 2 3 GND I/O 2 JEDEC SOT23-6L (Top View) Revision 2015/01/06 ©2015 Amazing Micro. 1 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL IPP Peak Pulse Current (tp =8/20µs) (I/O pins) VDC Operating Supply Voltage (VDD-GND) ESD per IEC 61000-4-2 (Air) (I/O pins) VESD_IO ESD per IEC 61000-4-2 (Contact) (I/O pins) ESD per IEC 61000-4-2 (Air) (VDD, GND pins) VESD_PW ESD per IEC 61000-4-2 (Contact) (VDD, GND pins) TSOL Lead Soldering Temperature TOP Operating Temperature TSTO Storage Temperature VIO DC Voltage at any I/O pin RATING 6 6 27 16 30 22 260 (10 sec.) -55 to +85 -55 to +150 (GND – 0.5) to (VDD + 0.5) ELECTRICAL CHARACTERISTICS SYMBOL CONDITIONS PARAMETER Reverse Stand-Off VRWM Voltage Reverse Leakage ILeak Current Channel Leakage ICH-Leak Current Reverse Breakdown VBV Voltage Forward Voltage VF ESD Clamping Vclamp_io Voltage –I/O ESD Clamping Vclamp_VDD Voltage –VDD ESD Dynamic Turn on Rdynamic_io Resistance –I/O ESD Dynamic Turn on Rdynamic_VDD Resistance –VDD Lightning Clamping Vlightning_io Voltage Lightning Clamping Vlightning_VDD Voltage Channel Input CIN-1 Capacitance -1 Channel Input CIN-2 Capacitance - 2 Channel to Channel CCROSS-1 Input Capacitance -1 Channel to Channel CCROSS-2 Input Capacitance -2 Variation of Channel Input Capacitance -1 △CIN-1 Variation of Channel Input Capacitance -2 △CIN-2 Revision 2015/01/06 MIN TYP o UNITS A V kV kV o C C o C o V MAX UNITS Pin 5 to pin 2, T=25 C 5 V VRWM = 5V, T=25 oC, Pin 5 to pin 2 5 µA VPin5 = 5V, VPin2 = 0V, T=25 oC 1 µA 9 V 1 V IBV = 1mA, T=25 oC, Pin 5 to Pin 2 IF = 15mA, T=25 oC, Pin 2 to Pin 5 IEC 61000-4-2 +6kV, T=25 oC, Contact mode, Any Channel pin to Ground IEC 61000-4-2 +6kV, T=25 oC, Contact mode, VDD pin to Ground IEC 61000-4-2 0~+6kV,T=25 oC, Contact mode, any Channel pin to Ground IEC 61000-4-2 0~+6kV, T=25 oC, Contact mode, VDD pin to Ground IPP=5A, tp=8/20µs, T=25 oC Any Channel pin to Ground IPP=5A, tp=8/20µs, T=25 oC VDD pin to Ground Vpin5 =5V, Vpin2 =0V, VIN =2.5V, f =1MHz, T=25 oC, Any Channel pin to Ground Vpin5=floated,Vpin2=0V,VIN=2.5V,f=1MHz, T=25oC,Any Channel pin to Ground Vpin5 =5V, Vpin2 =0V, VIN =2.5V, f =1MHz, T=25 oC , Between Channel pins Vpin5 =floated,Vpin2 =0V,VIN =2.5V,f =1MHz,T=25 oC,Between Channel pins Vpin5 =5V, Vpin2 =0V, VIN =2.5V, f =1MHz, T=25 oC , Channel_x pin to Ground Channel_y pin to Ground Vpin5 =floated, Vpin2 =0V, VIN =2.5V, f =1MHz, T=25 oC , Channel_x pin to Ground - Channel_y pin to Ground ©2015 Amazing Micro. 2 6 0.8 11 V 9 V 0.3 Ω 0.15 Ω 8.5 V 7.7 V 1.0 1.2 pF 1.5 1.7 pF 0.15 0.2 pF 0.18 0.23 pF 0.08 0.1 pF 0.06 0.08 pF www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port Input Capacitance (pF) Typical Characteristics Typical Variation of CIN vs. VIN 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 VDD=floated VDD=5V f = 1MHz, T=25 oC, 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Input Voltage (V) Clamping Voltage vs. Peak Pulse Current Forward Clamping Voltage vs. Peak Pulse Current 5 10 9 8 Forward Clamping Voltage (V) Clamping Voltage (V) 12 11 I/O pin to GND pin VDD pin to GND pin 7 6 5 4 3 2 Waveform Parameters: tr=8µ µs td=20µ µs 1 0 4.5 4 I/O pin to GND pin 3 2 VDD pin to GND pin 0 5.0 5.5 6.0 6.5 7.0 7.5 5 6 Transmission Line Pulsing (TLP) Measurement 18 16 14 V_pulse Pulse from a transmission line TLP_I 10 100ns + TLP_V 8 DUT - 6 4 I/O to GND 2 0 0 2 4 6 8 10 12 Transmission Line Pulsing (TLP) Voltage (V) Revision 2015/01/06 7 8 9 10 11 Peak pulse Current (A) Transmission Line Pulsing (TLP) Current (A) Transmission Line Pulsing (TLP) Current (A) Peak pulse Current (A) 12 Waveform Parameters: tr=8µ µs td=20µ µs 1 ©2015 Amazing Micro. Transmission Line Pulsing (TLP) Measurement 18 16 14 V_pulse 12 Pulse from a transmission line TLP_I 10 100ns + TLP_V 8 DUT - 6 4 VDDto GND 2 0 0 2 4 6 8 10 Transmission Line Pulsing (TLP) Voltage (V) 3 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port Applications Information A. Design Considerations The ESD protection scheme for system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D2 are general used to protect data line from ESD stress pulse. The diode D3 is a back-drive protection design, which blocks the DC back-drive current when the potential of I/O pin is greater than that of VDD pin. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (IESD1) will pass through the ESD current path1. Thus, the ESD clamping voltage VCL of data line can be described as follow: VCL = Fwd voltage drop of D1 + Breakdown voltage drop of D3 + supply voltage of VDD rail + L1 × d(IESD1)/dt + L2 × d(IESD1)/dt Where L1 is the parasitic inductance of data line, and L2 is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from power-rail ESD clamp ing circuit zero to 30A in 1ns. Here d(IESD1)/dt can be approximated by ∆IESD1/∆t, or 30/(1x10-9). So just 10nH of total parasitic inductance (L1 and L2 combined) will lead to over 300V increment in VCL! Besides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. The AZC199-04S has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (IESD2) will be directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path2). The clamping voltage VCL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current. AZC199-04S L2 D3 I ESD2 VDD rail I ESD1 D1 data line L1 + Vp _ VESD + Protected IC V CL D2 _ GND rail ESD current path 1 (I ESD1) ESD current path 2 (I ESD2) Fig. 1 Revision 2015/01/06 Application of positive ESD pulse between data line and GND rail. ©2015 Amazing Micro. 4 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port B. Device Connection AZC199-04S can provide protection for 4 I/O signal lines simultaneously. If the number of I/O signal lines is less than 4, the unused I/O pins can be simply left as NC pins. In some cases, systems are not allowed to be reset or restart after the ESD stress directly applying at the I/O-port connector. Under this situation, in order to enhance the sustainable ESD Level, a 0.1µF chip capacitor can be added between the VDD and GND rails. The place of this chip capacitor should be as close as possible to the AZC199-04S. In some cases, there isn’t power rail presented on the PCB. Under this situation, the power pin (pin 5) of AZC199-04S can be left as floating. The protection will not be affected, only the load capacitance of I/O pins will be slightly increased. Fig. 3 shows the detail connection. The AZC199-04S is designed to protect four data lines and power rails from transient over-voltage (such as ESD stress pulse). The device connection of AZC199-04S is shown in the Fig. 2. In Fig. 2, the four protected data lines are connected to the ESD protection pins (pin1, pin3, pin4, and pin6) of AZC199-04S. The ground pin (pin2) of AZC199-04S is a negative reference pin. This pin should be directly connected to the GND rail of PCB (Printed Circuit Board). To get minimum parasitic inductance, the path length should keep as short as possible. In addition, the power pin (pin 5) of AZC199-04S is a positive reference pin. This pin should directly connect to the VDD rail of PCB., then the VDD rail also can be protected by the power-rail ESD clamped circuit (not shown) of AZC199-04S. data line I/O 1 To I/O-port Connector data line I/O 2 I/O 2 GND rail 2 3 6 AZC199-04S 1 To I/O-port Conne ctor I/O 1 VDD rail 5 *Optional 0.1µ µF Chip Cap. 4 I/O 3 I/O 3 data line I/O 4 To Protected IC To Protected IC I/O 4 data line Fig. 2 Data lines and power rails connection of AZC199-04S. data line I/O 1 To I/O-port Connector data line I/O 2 I/O 2 GND rail 2 3 5 VDD floated 4 I/O 3 I/O 3 data line I/O 4 To Protected IC 6 AZC199-04S 1 To I/O-port Conne ctor I/O 1 data line To Protected IC I/O 4 Fig. 3 Data lines and power rails connection of AZC199-04S. VDD pin is left as floating when no power rail presented on the PCB. Revision 2015/01/06 ©2015 Amazing Micro. 5 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port C. Application plate as shown in Fig. 5. This back drive current may make VGA5V be not at zero potential, which may lead system to an abnormal state. Therefore, it should be eliminated, and the integrated back-drive protection diode can eliminate this current. The VGA Input Port In contrast with the design for a VGA output port, the schematic of ESD protection design for a VGA input port on a display system is shown in Fig. 6. In most of VGA input circuit designs, there are always two power supplies, one is from the connector’s DSUB-5V pin which potential comes from another VGA output port, the other is from the own power supply circuit of the VGA input port, system 5V. The VDD pin of AZC199-04S is directly connected to the connector’s DSUB-5V pin to block the ESD event which comes from the DSUB-5V pin. The PCB layout example for the VGA Port Fig. 7 shows the PCB layout example for a VGA port with two AZC199-04S being used. In order to get good signal quality, in this PCB example, the signal traces for R, G, and B signals are with 0.4mm width and are accompanied with GND traces, respectively. AZC199-04S is designed for protecting high speed I/O ports from very high over-voltage caused by Electrostatic Discharging (ESD). Thus, a lot of kinds of high speed I/O ports can be the applications of AZC199-04S, especially, the VGA and DVI ports with the ESD spec. of contact-15kV, Air-27kV, Class-C above. The VGA Output Port Fig. 4 shows the schematic of ESD protection design for a VGA output port on a host system, (e.g. the source, such as MB, NB, Media player…), where two AZC199-04S are used. The AZC199-04S has been integrated with back-drive protection diode for preventing the back-drive current to occur. Thus, no extra BAV70 for preventing the back-drive current to occur is needed. The back-drive current occurs as shown in Fig, 5. When the source stays at OFF state, at the source connector, the VGA5V pin was wished to be at zero potential. At this moment, if without the integrated back-drive current protection diode, the display device stays at ON state, and the pulled high signals will produce a current back drive to the source’s VGA5V power System_5V VGA5V Vide o Filter ESD Protection Design Red VGA5V Blue 6 5 4 Green Vide o Filter Green 75 Ω Vide o Filter Blue Blue AZC199-04S 75 Ω Detect DDCA_SCL 1 75 Ω 2 Green FB FB FB FB FB Detect VSYNC HSYNC DDC_Data DDC_CLK 3 DDCA_SDA Red VSYNC HSYNC HSYNC VGA5V VSYNC 6 5 4 AZC199-04S Signals From Scaler Detect VGA5V Red DIG_GND Red_GND Green_GND Blue_GND 1 2 3 GND DDCA_SCL DDCA_SDA 15-pin VGA connector Fig. 4 The ESD design for a VGA OUTPUT port which two AZC199-04S are used. Revision 2015/01/06 ©2015 Amazing Micro. 6 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port Source Site (e.g. MB) Monitor Site VGA5V 6 5 4 System 5V VGA5V BAV70 VDD 0.1uF VDD 1 2 3 10KΩ Ω 100Ω Ω DDCA_SDA to scaler DDC_Data DDCA_SDA DDCA_SDA FB Fig. 5 The occurred back drive current when the source is at OFF state and the display device is at ON state. ESD Protection Design Detect DSUB-5V Blue 6 Red Green Blue DIG_GND 100Ω Ω 0.047uF FB 0Ω Ω to scaler Green 75Ω Ω 2 3 Blue 5.6pF 100Ω Ω 0.047uF FB 0Ω Ω to scaler Blue Red 75Ω Ω 6 5 5.6pF 1KΩ Ω VSYNC 4 to scaler VSYNC AZC199-04S HSYNC to scaler Red 5.6pF HSYNC DSUB-5V VSYNC DDCA_SDA VSYNC Gree n Green DDCA_SCL FB 0Ω Ω 75Ω Ω 1 Detect 100Ω Ω 0.047uF Red 4 AZC199-04S DSUB-5V 5 2.2KΩ Ω HSYNC 1 2 220pF 1KΩ Ω FB 120Ω Ω to scaler HSYNC 2.2KΩ Ω 3 33pF Red_GND Green_GND DDCA_SCL DDCA_SDA System 5V Blue_GND GND System 5V DDCA_SDA 100Ω Ω 10KΩ Ω to scaler DDC_Data DSUB_5V System 5V BAV70 or BAT54 15-pin VGA connector 100Ω Ω DDCA_SCL 10KΩ Ω to scaler DDC_CLK EEPROM Fig. 6 The ESD design for a VGA INPUT port which two AZC199-04S are used. Revision 2015/01/06 ©2015 Amazing Micro. 7 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port Pin-1 Pin-1 Fig. 7 The PCB layout example for a VGA port with two AZC199-04S being used. Revision 2015/01/06 ©2015 Amazing Micro. 8 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port Mechanical Details SOT23-6L PACKAGE DIAGRAMS TOP VIEW PACKAGE DIMENSIONS Symbol Millimeters MIN. MIN. 1.45 A MAX. 0.057 A1 0 0.15 0.000 0.006 A2 0.9 1.3 0.035 0.051 b 0.3 0.5 0.012 0.020 c 0.08 0.21 0.003 0.008 D 2.72 3.12 0.107 0.123 E 1.4 1.8 0.055 0.071 E1 2.6 3 0.102 0.118 e 0.95BSC 0.037BSC e1 1.9BSC 0.075BSC L1 SIDE VIEW MAX. Inches 0.3 0.6 0.012 0.024 L 0.7REF 0.028REF L2 0.25BSC 0.010BSC Ɵ 0 0 8 8 Notes:
This dimension complies with JEDEC outline standard MO-178 Variation AB.
Dimensioning and tolerancing per ASME Y14.5M-1994.
All dimensions are in millimeters, and the END VIEW Revision 2015/01/06 ©2015 Amazing Micro. dimensions in inches are for reference only.
1mm = 40 mils = 0.04 inches. 9 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port LAND LAYOUT Dimensions Index Millimeter Inches A 0.60 0.024 B 1.10 0.043 C 0.95 0.037 D 2.50 0.098 E 1.40 0.055 F 3.60 0.141 Notes: This LAND LAYOUT is for reference purposes only. Please consult your manufacturing partners to ensure your company’s PCB design guidelines are met. MARKING CODE C16XY 103X S15X Part Number Marking Code AZC199-04S (Green part) C16XY Note : Green means Pb-free, RoHS, and Halogen free compliant. C16 = Device Code X = Date Code Y = Control Code Ordering Information PN# Material Type Reel size MOQ/internal box MOQ/carton AZC199-04S.R7G Green T/R 7 inch 4 reel= 12,000/box 6 box =72,000/carton Revision 2015/01/06 ©2015 Amazing Micro. 10 www.amazingIC.com AZC199-04S Low Capacitance High ESD Level Protection Array For High Speed I/O Port Revision History Revision Modification Description Revision 2008/04/02 Original Release. Revision 2008/09/29 Add the marking code for Green part. Revision 2008/12/26 Update the PACKAGE DIMENSIONS. Revision 2011/06/13 1. Update the Company Logo. 2. Add the ordering information. Revision 2015/01/06 Revision 2015/01/06 Remove the marking code of Non-Green part. ©2015 Amazing Micro. 11 www.amazingIC.com