XD3526

XL3526 SOP18,XD3526 DIP18 The XD/XL3526 s a high performance pulse width modulator integrated circuit intended for fixed frequency switching regulators and other power control applications. Functions included in this IC are a temperature compensated voltage reference, sawtooth oscillator, error amplifier, pulse width modulator, pulse metering and steering logic, and two high current totem pole outputs ideally suited for driving the capacitance of power FETs at high speeds. Additional protective features include soft start and undervoltage lockout, digital current limiting, double pulse inhibit, adjustable dead time and a data latch for single pulse metering. All digital control ports are TTL and B−series CMOS compatible. Active low logic design allows easy wired−OR connections for maximum flexibility. The versatility of this device enables implementation in single−ended or push−pull switching regulators that are transformerless or transformer coupled. The XD/XL3526 is specified over a junction temperature range of 0 ° to +125°C. • 8.0 V to 35 V Operation • 5.0 V ±1% Trimmed Reference • 1.0 Hz to 400 kHz Oscillator Range • Dual Source/Sink Current Outputs: ±100 mA • Digital Current Limiting • Programmable Dead Time • Undervoltage Lockout • Single Pulse Metering • Programmable Soft−Start • Wide Current Limit Common Mode Range • Guaranteed 6 Unit Synchronization Vref VCC Ground Sync RDeadtime RT CT Reset CSoft−Start 18 17 Reference Regulator 15 12 +C.S. −C.S. Shutdown Under− Voltage Lockout To Internal Circuitry 14 VC 11 9 Oscillator 10 13 Output A 5 4 Compensation +Error −Error PIN CONNECTIONS 1 2 Soft Start Memory F/F S 3 VCC + − Amp 100 mV 7 + 6 − 8 − + SQ R RQ Toggle F/F Q T Q 16 Q Output B Metering F/F Figure 1. Representative Block Diagram 1 +Error 1 18 Vref −Error 2 17 VCC Compensation 3 16 Output B CSoft−Start 4 15 Ground Reset 5 14 VC −CS 6 13 Output A +CS 7 12 Sync Shutdown 8 11 RDeadtime RT 9 10 CT XL3526 SOP18,XD3526 DIP18 MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Supply Voltage VCC +40 Vdc Collector Supply Voltage VC +40 Vdc Logic Inputs −0.3 to +5.5 V Analog Inputs −0.3 to VCC V Output Current, Source or Sink IO ±200 mA Reference Load Current (VCC = 40 V, Note 2) Iref 50 mA 15 mA Logic Sink Current Power Dissipation TA = +25°C (Note 3) TC = +25°C (Note 4) PD mW 1000 3000 Thermal Resistance Junction−to−Air RθJA 100 °C/W Thermal Resistance Junction−to−Case RθJC 42 °C/W Operating Junction Temperature TJ +150 °C Storage Temperature Range Tstg −65 to +150 °C TSolder ±300 °C Lead Temperature (Soldering, 10 Seconds) RECOMMENDED OPERATING CONDITIONS Characteristics 1. 2. 3. 4. Symbol Min Max Unit Supply Voltage VCC 8.0 35 Vdc Collector Supply Voltage VC 4.5 35 Vdc Output Sink/Source Current (Each Output) IO 0 ±100 mA Reference Load Current Iref 0 20 mA Oscillator Frequency Range fosc 0.001 400 kHz Oscillator Timing Resistor RT 2.0 150 kΩ Oscillator Timing Capacitor CT 0.001 20 μF Available Deadtime Range (40 kHz) − 3.0 50 % Operating Junction Temperature Range TJ 0 +125 °C Values beyond which damage may occur. Maximum junction temperature must be observed. Derate at 10 mW/°C for ambient temperatures above +50°C. Derate at 24 mW/°C for case temperatures above +25°C. 2 XL3526 SOP18,XD3526 DIP18 ELECTRICAL CHARACTERISTICS (VCC = +15 Vdc, TJ = Tlow to Thigh [Note 6], unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Reference Output Voltage (TJ = +25°C) Vref 4.90 5.00 5.10 V Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Regline − 10 30 mV Load Regulation (0 mA ≤ IL ≤ 20 mA) Regload − 10 50 mV Temperature Stability ΔVref/ΔT − 10 − mV ΔVref 4.85 5.00 5.15 V ISC 25 80 125 mA Reset Output Voltage (Vref = +3.8 V) − 0.2 0.4 V Reset Output Voltage (Vref = +4.8 V) 2.4 4.8 − V REFERENCE SECTION (Note 7) Total Reference Output Voltage Variation (+8.0 V ≤ VCC ≤ +35 V, 0 mA ≤ IL ≤ 20 mA) Short Circuit Current (Vref = 0 V) (Note 5) UNDERVOLTAGE LOCKOUT OSCILLATOR SECTION (Note 8) − ±3.0 ±8.0 % Frequency Stability over Power Supply Range (+8.0 V ≤ VCC ≤ +35 V) Initial Accuracy (TJ = +25°C) Δfosc Δ V − 0.5 1.0 % Frequency Stability over Temperature (ΔTJ = Tlow to Thigh) Δfosc − 2.0 − % Δ TJ CC Minimum Frequency (RT = 150 kΩ, CT = 20 μF) fmin − 0.5 − Hz Maximum Frequency (RT = 2.0 kΩ, CT = 0.001 μF) fmax 400 − − kHz Sawtooth Peak Voltage (VCC = +35 V) Vosc(P) − 3.0 3.5 V Sawtooth Valley Voltage (VCC = +8.0 V) Vosc(V) 0.45 0.8 − V Input Offset Voltage (RS ≤ 2.0 kΩ) VIO − 2.0 10 mV Input Bias Current IIB − −350 −2000 nA Input Offset Current IIO − 35 200 nA ERROR AMPLIFIER SECTION (Note 9) 5. 6. 7. 8. 9. DC Open Loop Gain (RL ≥ 10 MΩ) AVOL 60 72 − dB High Output Voltage (VPin 1−VPin 2 ≥ +150 mV, Isource = 100 μA) VOH 3.6 4.2 − V Low Output Voltage (VPin 2−VPin 1 ≥ +150 mV, Isink = 100 μA) VOL − 0.2 0.4 V Common Mode Rejection Ratio (RS ≤ 2.0 kΩ) CMRR 70 94 − dB Power Supply Rejection Ratio (+12 V ≤ VCC ≤ +18 V) PSRR 66 80 − dB Maximum junction temperature must be observed. Tlow = 0°C Thigh = +125°C IL = 0 mA unless otherwise noted. fosc = 40 kHz (RT = 4.12 kΩ ± 1%, CT = 0.01 μF ± 1%, RD = 0 Ω) 0 V ≤ VCM ≤ +5.2 V. 3 XL3526 SOP18,XD3526 DIP18 ELECTRICAL CHARACTERISTICS (continued) Characteristics Symbol Min Typ Max Unit Minimum Duty Cycle (VCompensation = +0.4 V) DCmin − − 0 % Maximum Duty Cycle (VCompensation = +3.6 V) DCmax 45 49 − % VOH VOL 2.4 − 4.0 0.2 − 0.4 IIH IIL − − −125 −225 −200 −360 Vsense 80 100 120 mV IIB − −3.0 −10 μA − 0.1 0.4 V 50 100 150 μA 12.5 12 13.5 13 − − − − 0.2 1.2 0.3 2.0 IC(leak) − 50 150 μA Rise Time (CL = 1000 pF) tr − 0.3 0.6 μs Fall Time (CL = 1000 pF) tf − 0.1 0.2 μs ICC − 18 30 mA PWM COMPARATOR SECTION (Note 10) DIGITAL PORTS (SYNC, SHUTDOWN, RESET) Output Voltage (High Logic Level) (Isource = 40 μA) (Low Logic Level) (Isink = 3.6 mA) V Input Current ⎯ High Logic Level (High Logic Level) (VIH = +2.4 V) (Low Logic Level) (VIL = +0.4 V) μA CURRENT LIMIT COMPARATOR SECTION (Note 12) Sense Voltage (RS ≤ 50 Ω) Input Bias Current SOFT−START SECTION Error Clamp Voltage (Reset = +0.4 V) ICS CSoft−Start Charging Current (Reset = +2.4 V) OUTPUT DRIVERS (Each Output, VC = +15 Vdc, unless otherwise noted.) Output High Level Isource = 20 mA Isource = 100 mA VOH Output Low Level Isink = 20 mA Isink = 100 mA VOL Collector Leakage, VC = +40 V Supply Current (Shutdown = +0.4 V, VCC = +35 V, RT = 4.12 kΩ) 10. fosc = 40 kHz (RT = 4.12 kΩ ± 1%, CT = 0.01 μF ± 1%, RD = 0 Ω) 11. 0 V ≤ VCM ≤ +5.2 V 12. 0 V ≤ VCM ≤ +12 V 4 V V V ref , REFERENCE VOLTAGE (V) XL3526 SOP18,XD3526 DIP18 50 mV Spec Limit −75 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 5.0 4.0 3.0 2.0 1.0 150 1.0 2.0 Figure 2. Reference Stability over Temperature 3.0 4.0 5.0 10 20 30 40 VCC, SUPPLY VOLTAGE (V) Figure 3. Reference Voltage as a Function Supply Voltage 8.0 SHUTDOWN VOLTAGE (V) 80 60 40 20 1 + _ 3 2 0 10 100 pF 100 CComp 1.0 k 10 k 100 k 1.0 M 4.0 3.0 2.0 0 10 M 25 50 75 100 125 150 175 200 f, FREQUENCY (Hz) DIFFERENTIAL INPUT VOLTAGE (mV) Figure 4. Error Amplifier Open Loop Frequency Response Figure 5. Current Limit Comparator Threshold 7.0 RESET VOLTAGE (V) 5.0 1.0 8.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 6.0 V sat , OUTPUT DRIVER SATURATION VOLTAGE (V) A Vol , VOLTAGE GAIN (dB) 7.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 2.5 2.0 1.5 1.0 0.5 0 2.0 5.0 10 20 50 100 200 Vref, REFERENCE VOLTAGE (V) OUTPUT DRIVER SINK CURRENT (mA) Figure 6. Undervoltage Lockout Characteristic Figure 7. Output Driver Saturation Voltage as a Function of Sink Current 5 XL3526 SOP18,XD3526 DIP18 200 10 20 50 IC, SINK CURRENT (mA) 100 5.0 2.0 200 0.005 0.01 0.02 5.0 10 0.002 0 2.0 20 Figure 8. VC Saturation Voltage as a Function of Sink Current 100 200 500 1000 0.5 50 5.0 10 20 50 1.0 RD = 0 Ω 1.0 2.0 1.5 100 0.05 0.1 0.2 0.5 2.0 R T, TIMING RESISTOR (k Ω ) V SAT , SATURATION VOLTAGE (V) 2.5 OSCILLATOR PERIOD (ms) Figure 9. Oscillator Period VCC Q6 Vref Q5 Vref 125 μA Q11 Q3 Q4 50μA 50μA 14μA 14μA 100 μA Q7 Q8 To Reset Q12 100μA R1 3 Compensation Q10 100μA 1.2V Bandgap Reference Q9 Q1 Q2 1.0k 500 1.0k + 500 − R2 1 + Error − Error Figure 10. Error Amplifier Figure 11. Undervoltage Lockout Memory F/F Sync S Q PWM The metering Flip−Flop is an asynchronous data latch which suppresses high frequency oscillations by allowing only one PWM pulse per oscillator cycle. S R Q Clock D Q The memory Flip−Flop prevents double pulsing in a push−pull configuration by remembering which output produced the last pulse. PWM Metering F/F Figure 12. Pulse Processing Logic 6 To Driver A To Driver B XL3526 SOP18,XD3526 DIP18 APPLICATIONS INFORMATION Negative Output Voltage R1 R3 Vref 1 + Vref 2 − R2 R3 Positive Output Voltage R1 17 VCC 1 + 2 − C* 27 R2 18 Reference Regulator Vref Gnd Gnd + 15 10μF Vout = Vref R1 + R2 R2 R1 R2 Vout = Vref Gnd R1R2 R1 + R2 R3 = * May be required with some types of transistors Figure 13. Extending Reference Output Current Capability Figure 14. Error Amplifier Connections Output to Load + RS 11 12 XD/XL3526 − 6 Sync 8 RD 9 Vout R1 + 7 10 R2 Gnd RT CT 0.1 V + I(max) = Figure 15. Oscillator Connections − Vout R1 R1 + R2 ISC = RS 0.1 V RS Figure 16. Foldback Current Limiting +12V Vref + Error − Error Reset 1 2 + 14 VC 100 μA Ramp − PWM Error − Amp XD/XL3526 + Gnd Q2 5 A 13 B 16 Q1 Q3 To Undervoltage Lockout CSoft−Start The totem pole output drivers of the XD/XL3526 are ideally suited for driving the input capacitance of power FETs at high speeds. Figure 17. Soft−Start Circuity Figure 18. Driving VMOS Power FETs 7 XL3526 SOP18,XD3526 DIP18 +V Supply R1 14 VC +V Supply 5 8 C1 14 VC 13 4 B CS T2 XD/XL3526 Gnd 15 S Q1 A C2 Q2 16 R4 A R B XD/XL3526 R1 C1 T1 C2 +CS −CS Gnd 15 13 D1 16 D2 Q1 7 R3 6 R2 T1 In the above circuit, current limiting is accomplished by using the current limit comparator output to reset the soft−start capacitor. Figure 19. Half−Bridge Configuration Q1 +V Supply Figure 20. Flyback Converter with Current Limiting To Output Filter R1 +V Supply R1 C1 R2 14 VC A XD/XL3526 B 14 VC 13 A 13 Gnd Gnd B Q1 C2 XD/XL3526 16 R2 16 R3 Q2 15 15 Figure 21. Single−Ended Configuration Figure 22. Push−Pull Configuration 8 T1 XL3526 SOP18,XD3526 DIP18 9 XL3526 SOP18,XD3526 DIP18 10