CBM706AS8

CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION FEATURES GENERAL DESCRIPTION  Guaranteed RESET valid with VCC = 1V The CBM705, CBM706, CBM707, CBM708  190 μA quiescent current microprocessor supervisory circuits  Precision supply voltage monitor suitable monitoring 5V supplies/batteries 4.65 V (CBM705/CBM707) 200 ms reset pulse width  Debounced TTL/CMOS manual reset and power microprocessor activity. 4.40 V (CBM706/CBM708)  for are The CBM705/ power-supply CBM706 monitoring provide circuitry that generate a reset output during power-up, input (MR) power-down, and brownout conditions. The Independent watchdog timer reset output remains operational with VCC as (CBM705/CBM706) low as 1V. Independent watchdog monitoring  1.60 sec timeout (CBM705/CBM706) circuitry is also provided. This is activated if  Active high reset output  the watchdog input has not been toggled within 1.60 sec. (CBM707/CBM708)  In addition, there is a 1.25V threshold Voltage monitor for power fail or low detector to warn of power failures, to detect battery warning  low battery conditions, or to monitor an Superior upgrade for ADM705 to additional power supply. An active low, ADM708 debounced manual reset input ( MR ) is also included. APPLICATIONS  Microprocessor systems  Computers  Controllers  Intelligent instruments  Critical microprocessor supply The CBM705 and CBM706 are identical except for the reset threshold monitor levels, which are 4.65V and 4.40V, respectively. The CBM707 and CBM708 provide a similar functionality to the CBM705 and CBM706 and only differ in that a watchdog timer function is not available. Instead, an monitoring active high reset output (RESET) is available as well as the active low reset output ( RESET ). The CBM707 and CBM708 are identical except for the reset threshold monitor levels, which are 4.65V and 4.40V, respectively. All devices are available in narrow 8-lead SOIC packages. 1 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION FUNCTIONAL BLOCK DIAGRAMS *VOLTAGE REFERENCE = 4.65V (CBM705), 4.40V (CBM706) Figure 1. CBM705/CBM706 * VOLTAGE REFERENCE = 4.65V (CBM707), 4.40V (CBM708) Figure 2. CBM707/CBM708 2 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION SPECIFICATIONS VCC = 4.75 V to 5.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments 5.5 V 190 250 μA 4.5 4.65 4.75 V CBM705/CBM707 4.25 4.40 4.50 V CBM706/CBM708 POWER SUPPLY VCC Operating Voltage Range 1.0 Supply Current LOGIC OUTPUT Reset Threshold Reset Threshold Hysteresis RESET PULSE WIDTH RESET OUTPUT VOLTAGE RESET OUTPUT VOLTAGE WATCHDOG TIMEOUT PERIOD (tWD) WDI Pulse Width (tWP) 40 160 mV 200 280 VCC-1.5 V ISOURCE = 800 µA 0.4 V ISINK = 3.2 mA 0.3 V VCC = 1 V, ISINK = 50 µA 0.3 V VCC = 1.2 V, ISINK = 100 µA V CBM707/CBM708, ISOURCE = 800 µA 0.4 V CBM707/CBM708, ISINK = 1.2 mA 2.25 sec VCC−1.5 1.00 1.60 ms 50 VIL = 0.4 V, VIH = VCC×0.8,WDI = VCC ns WATCHDOG INPUT WDI Input Threshold Logic Low Logic High 0.8 3.5 WDI Input Current WDO OUTPUT VOLTAGE V 50 -150 V 150 -50 VCC-1.5 µA WDI=0V µA WDI=0V V ISOURCE = 800µA 0.4 V ISINK = 1.2mA 600 µA MANUAL RESET INPUT MR Pull-Up Current 100 MR Pulse Width 150 250 MR = 0V ns MR INPUT THRESHOLD Logic Low Logic High 0.8 2.0 V V MR TO RESET OUTPUT DELAY 250 ns POWER FAIL INPUT PFI Input Threshold 1.2 1.25 1.3 V PFI Input Current -25 +0.01 +25 nA PFO OUTPUT VOLTAGE VCC-1.5 0.4 V ISOURCE = 800 µA V ISINK = 3.2 mA 3 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Stresses at or above those listed under Parameter Rating VCC −0.3 V to +6 V Absolute All Other Inputs −0.3V to permanent damage to the product. This is a VCC+0.3V stress rating only; functional operation of the Maximum Ratings may cause product at these or any other conditions Input Current VCC 20mA above those indicated in the operational GND 20mA section of this specification is not implied. Digital Output Current 20mA Power Dissipation, N-8 PDIP 727mW operating conditions for extended periods θJA Thermal Impedance 135℃ may affect product reliability. Power Dissipation, R-8 SOIC 470mW θJA Thermal Impedance 110℃/W Power Dissipation, RM-8 MSOP 900mW θJA Thermal Impedance 206℃/W Operation beyond the maximum Operating Temperature Range Industrial (Version A) -40℃ to +85℃ Lead Temperature (Soldering, 300℃ 10 sec) Vapor Phase (60 sec) 215℃ Infrared (15 sec) 220℃ Storage Temperature Range -65℃ to +150℃ ESD Rating >4.5kV 4 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. CBM705/CBM706 PDIP/SOIC Figure 4. CBM707/CBM708 PDIP/SOIC Figure 5. CBM708 MSOP 5 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION Pin Function Descriptions Pin Number Mnemonic CBM705 CBM707 CBM706 CBM708 Description CBM708 Manual Reset Input. When this pin is taken below 0.8V, a reset is MR 1 1 3 generated. MR can be driven from TTL, CMOS logic, or from a manual reset switch as it is internally debounced. An internal 250μA pull-up current holds the input high when floating. VCC 2 2 4 GND 3 3 5 5V Power Supply Input. Place a 0.1μF decoupling capacitor between the VCC and GND pins. 0V Ground Reference for All Signals. Power Fail Input. PFI is the noninverting input to the power fail PFI 4 4 6 comparator. When PFI is less than 1.25V, PFO goes low. If unused, PFI must be connected to GND. PFO 5 5 7 Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is less than 1.25V. Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period, the watchdog output WDI 6 Not Not applicable applicable (WDO ) goes low. The timer resets with each transition at the WDI input. Either a high to low or a low to high transition clears the counter. The internal timer is also cleared whenever reset is asserted. The watchdog timer is disabled when WDI is left floating or connected to a three-state buffer. NC Not applicable 6 8 No Connect. Logic Output. RESET goes low for 200ms when triggered. It can be triggered either by VCC being below the reset threshold or by a low signal on the manual reset input ( MR ). RESET remains low whenever VCC is RESET 7 7 1 below the reset threshold (4.65V in CBM705/CBM707, 4.40 V in CBM706/CBM708). It remains low for 200ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is connected to MR. Watchdog Output. WDO remains low until the watchdog timer is cleared. WDO 8 Not Not WDO also goes low during low line conditions. Whenever VCC is below the applicable applicable reset threshold, WDO goes low if the internal WDO remains low. As soon as VCC goes above the reset threshold, WDO goes high. RESET Not applicable 8 2 Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the inverse of RESET. 6 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION TYPICAL PERFORMANCE CHARACTERISTICS Figure 6. RESET Output Voltage vs. Supply Voltage Figure 8. PFI Comparator Assertion Response Time Figure 7. CBM707/CBM708 RESET Output Voltage vs. Figure 9. PFI Comparator Deassertion Response Time Supply Voltage 7 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION Figure 10. RESET, RESET Assertion Figure 12. CBM705/CBM707 RESET Response Time Figure 11. RESET, RESET Deassertion 8 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION CIRCUIT INFORMATION POWER FAIL RESET OUTPUT RESET is an active low output that provides a reset signal to the microprocessor whenever the VCC input is below the reset threshold. An internal timer holds RESET low for 200 ms after the voltage on VCC rises above the threshold. This functions as a power-on reset signal for the microprocessor. It allows time for both the power supply and the microprocessor to stabilize after power-up. The RESET output is guaranteed to remain valid (low) with VCC as low as 1V. This ensures that the microprocessor is held in a stable shutdown condition as the power supply voltage ramps up. In addition to RESET, an active high RESET output is also available on the CBM707/CBM708. This is the complement of RESET and is useful for processors requiring an active high reset signal. MANUAL RESET The manual reset input (MR ) allows other reset sources, such as a manual reset switch, to generate a processor reset. The input is effectively debounced by the timeout period (200 ms typically). The MR input is TTL-/CMOS-compatible, so it can also be driven by any logic reset output. Figure 13. RESET, MR, and WDO Timing 9 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION WATCHDOG TIMER (CBM705/CBM706) The watchdog timer circuit can monitor the activity of the micro-processor to check that it is not stalled in an indefinite loop. An output line on the processor toggles the watchdog input (WDI) line. If this line is not toggled within the timeout period (1.60 sec), then the watchdog output (WDO ) goes low. The WDO can be connected to a nonmaskable interrupt (NMI) on the processor; therefore, if the watchdog timer times out, an interrupt is gen-erated. The interrupt service routine then rectifies the problem. If a RESET signal is required when a timeout occurs, the WDO must connect to the manual reset input (MR). The watchdog timer is cleared by either a high to low or a low to high transition on WDI. It is also cleared by RESET going low; therefore, the watchdog timeout period begins after RESET goes high. When VCC falls below the reset threshold, WDO is forced low, whether or not the watchdog timer has timed out. Normally, this generates an interrupt, but it is overridden by RESET going low. The watchdog monitor can be deactivated by floating the WDI. The WDO can then be used as a low line output because it goes low only when VCC falls below the reset threshold. Figure 14. Watchdog Timing 10 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION POWER FAIL COMPARATOR The power fail comparator is an independent comparator that can monitor the input power supply. The comparator inverting input is internally connected to a 1.25V reference voltage. The noninverting input is available at the PFI input. This input can monitor the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25V, the comparator output (PFO) goes low, indicating a power failure. For early warning of power failure, the comparator monitors the preregulator input by choosing an appropriate resistive divider network. The PFO output can interrupt the processor so a shutdown procedure is implemented before power is lost. As the voltage on the PFI pin is limited to VCC + 0.3V, it is recommended to connect the PFI pin with a Schottky diode to the RESET pin as shown in Figure 15. This helps clamping the PFI pin voltage during device power up and operation. Figure 15. Power Fail Comparator 11 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION Adding Hysteresis to the Power Fail Comparator For increased noise immunity, hysteresis can be added to the power fail comparator. Because the comparator circuit is noninverting, hysteresis can be added by connecting a resistor between the PFO output and the PFI input as shown in Figure 16. Figure 16. Adding Hysteresis to the Power Fail Comparator When PFO is low, Resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, Resistor R3 sources current into the PFI summing junction. This results in differing trip levels for the comparator. Further noise immunity can be achieved by connecting a capacitor between PFI and GND. The equations calculate the hysteresis are as follows: VH = 1.25 1 + R2+R3 R2×R3 VL = 1.25 + R1( VMID = 1.25( 1.25 R2 R1+R2 R2 ) − R1] VCC −1.25 R3 ) 12 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION VALID RESET BELOW 1V VCC The CBM705/CBM706/CBM707/CBM708 are guaranteed to provide a valid reset level with VCC as low as 1 V (see the Typical Performance Characteristics section). As VCC drops below 1V, the internal transistor does not have sufficient drive to hold the voltage RESET at 0V. A pull-down resistor can connect externally, as shown in Figure 17, to hold the line low if required. Figure 17. RESET Valid Below 1V 13 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION APPLICATIONS INFORMATION A typical application circuit is shown in Figure 18. The un-regulated dc input supply is monitored using PFI via the resistive divider network. Resistor R1 and Resistor R2 must be selected so when the supply voltage drops below the desired level (such as 8V), the voltage on PFI drops below the 1.25V threshold, thereby generating an interrupt to the microprocessor. Monitoring the preregulator input provides additional time to execute an orderly shutdown procedure before power is lost. Figure 18. Typical Application Circuit Microprocessor activity is monitored using WDI. This is driven using an output line from the processor. The software routines toggle this line at least once every 1.60 seconds. If a problem occurs and this line is not toggled, WDO goes low and a nonmaskable interrupt is generated. This interrupt routine can clear the problem. If in the event of inactivity on the WDI line, a system reset is required, WDO must connect to MR as shown in Figure 19. Figure 19. RESET From WDO 14 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION MONITORING ADDITIONAL SUPPLY LEVELS It is possible to use the power fail comparator to monitor a second supply as shown in Figure 20. The two sensing resistors, R1 and R2, are selected so the voltage on PFI drops below 1.25V at the minimum acceptable input supply. PFO can connect to MR so a reset is generated when the supply drops out of tolerance. In this case, if either supply drops out of tolerance, a reset is generated. Figure 20. Monitoring 5 V and an Additional Supply, VX MICROPROCESSOR WITH BIDIRECTIONAL RESET To prevent contention for microprocessors with a bidirectional reset line, a current limiting resistor must be inserted between the CBM705/ CBM706/ CBM707/ CBM708 RESET output pin and the microprocessor RESET pin. This limits the current to a safe level if there are conflicting output reset levels. A suitable resistor value is 4.7kΩ. If the reset output is required for other uses, it must be buffered, as shown in Figure 21. Figure 21. Bidirectional Input/Output RESET 15 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION OUTLINE DIMENSIONS SOIC-8(SOP8) Symbol Dimensions In Millimeters Dimensions Inches Min Max Min Max A 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.007 0.010 D 4.800 5.000 0.189 0.197 E 5.800 6.200 0.228 0.244 E1 3.800 4.000 0.150 0.157 e 1.270 BSC 0.050 BSC L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8° 16 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION MSOP-8 Symbol Dimensions In Millimeters Dimensions Inches Min Max Min Max A 0.820 1.100 0.032 0.043 A1 0.020 0.150 0.001 0.006 A2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 D 2.900 3.100 0.114 0.122 E 2.900 3.100 0.114 0.122 E1 4.750 5.050 0.187 0.199 e 0.650 BSC 0.026 BSC L 0.400 0.800 0.016 0.031 θ 0° 6° 0° 6° 17 www.corebai.com CBM705/CBM706/CBM707/CBM708 OPERATION INSTRUCTION PACKAGE/ORDERING INFORMATION PRODUCT ORDERING PAKEAGE TRANSPOT MARKING MEDIA,QUANTILY SOIC-8(SOP8) CBM705A Tape and Reel,2500 -40℃~125℃ MSOP-8 705AM Tape and Reel,3000 CBM706AS8 -40℃~125℃ SOIC-8(SOP8) CBM706A Tape and Reel,2500 CBM706AMS8 -40℃~125℃ MSOP-8 706AM Tape and Reel,3000 CBM707AS8 -40℃~125℃ SOIC-8(SOP8) CBM707A Tape and Reel,2500 CBM707AMS8 -40℃~125℃ MSOP-8 707AM Tape and Reel,3000 CBM708AS8 -40℃~125℃ SOIC-8(SOP8) CBM708A Tape and Reel,2500 CBM708AMS8 -40℃~125℃ MSOP-8 708AM Tape and Reel,3000 TEMPRANGE PACKAGE CBM705AS8 -40℃~125℃ CBM705AMS8 NUMBER CBM705 CBM706 CBM707 CBM708 18 www.corebai.com