CBM53D14BMS

CBM53D04/CBM53D14/CBM53D24 Datasheet Features   General Description CBM53D04: 4 buffered 8-Bit DACs in The MSOP10L are quad 8-, 10- and 12-bit buffered voltage CBM53D14: 4 buffered 10-Bit DACs output DACs in MSOP10L packages that operate from a single 2.5V to 5.5V supply, in MSOP10L  CBM53D04/CBM53D14/CBM53D24 consuming only 500uA at 3V. They have on- CBM53D24: 4 buffered 12-Bit DACs chip rail-to-rail output amplifiers with slew in MSOP10L rate of 0.7V/us. A 3-wire serial interface  Low power operation: 500uA @ 3V,  600uA @ 5V  2.5V to 5.5V power supply  Power-down to 80nA @ 3V,200nA @ 5V  Double-buffered input logic  Output range:0V to VREF derived from one reference pin. The outputs  Power-on reset to 0V of all DACs can be updated simultaneous. It  On-chip, rail-to-rail output buffer incorporate a power-on reset circuit, and amplifiers ensure that the DAC outputs power up to 0V Temperature range -40℃ to +105℃ and remains there until a valid write takes  compatible Portable battery-powered instruments  Digital gain and offset adjustment  Programmable voltage and current standard SPI, QSPI, MICROWIRE, and DSP interface standards is used, which can operates at clock rates up to 30MHz. The references for the four DACs are place to the device. The parts contain a power- Applications  with down feature that reduces the current consumption to 200nA @ 5V (80nA @ 3V). sources  Programmable attenuators  Industrial process controls 1 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Functional Block Diagram Figure 1 Functional Block Diagram Typical Application Circuit Figure 2 CBM53D04/CBM53D14/CBM53D24 Typical Application Circuit 2 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Absolute Maximum Ratings Table 1 TA=25℃,unless otherwise noted. Parameter1 Sym Rating VDD to GND VDDabs -0.3V to+7V Digital Input Voltage to GND VDigabs -0.3V to VDD+0.3V Reference Input Voltage to GND Vrefabs -0.3V to VDD+0.3V VOUTA through VOUTD to GND Voutabs -0.3V to VDD+0.3V TP -40℃ to +105℃ Operating Temperature Range Industrial TS Storage Temperature Range Junction TemperatureTJ max -65℃ to +150℃ TJmax 150℃ Reflow Soldering Peak Temperature(Pb-free) 260℃ Peak Temperature(non Pb-free) 220℃ Time at Peak Temperature 10 sec to 40 sec Transient currents of up to 100mA do not cause SCR latch-up. Recommended Operation Conditions Table 2 Parameter Sym Power supply Rating Unit Min Max VDD 2.5 5.5 V Current dissipation IDD 400u 600u A Ambient Temperature Ta -40 105 ℃ 3 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Specifications Table 3 VDD=2.5V to 5.5V; VREF=2V; RL=2KΩ to GND ; CL=200pF to GND; Ta=25℃; unless otherwise noted. Parameter Sym Test Condition Min Typ Max Unit DC Performance1,2 CBM53D04 Resolution ResN 8 Bits Relative Accuracy INL ±0.15 LSB Differential Nonlinearity DNL ±0.02 LSB Monotonic Guaranteed CBM53D14 Resolution ResN 10 Bits Relative Accuracy INL ±0.5 LSB Differential Nonlinearity DNL ±0.05 LSB Monotonic Guaranteed CBM53D24 Resolution ResN 12 Bits Relative Accuracy INL ±2 LSB Differential Nonlinearity DNL ±0.2 LSB Offset Error ±0.4 %of FSR Gain Error ±0.15 %of FSR 20 mV △VDD=±10% -60 dB RL=2KΩ to GND or VDD 200 uV Lower dead band exists only if Lower Dead Band DC Power Supply Rejection Ratio3 DC Crosstalk3 Monotonic Guaranteed offset error is negative PSRR Reference Input3 VREF Input Range 0.25 VREF Input Impedance VDD V 45 KΩ -80 dB Minimum Output Voltage4 0 V Maximum Output Voltage4 VDD V DC Output Impedance 0.5 Ω Reference Feedthrough Frequency=10KHz Output Characteristics3 4 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Short Circuit Current 25 mA Power-Up Time 5 uS Logic Input3 Input Low Voltage VIL VDD=3V 0.6 V Input High Voltage VIH VDD=3V 2.1 V pF 3 Pin Capacitance Power Requirements Power supply VDD IDD (Normal Mode)4 IDD 2.5 5.5 V VDD=4.5V to 5.5V VIH=VDD and VIL=GND 600 uA VDD=2.5V to 3.6V VIH=VDD and VIL=GND 500 uA VDD=4.5V to 5.5V VIH=VDD and VIL=GND 0.2 uA VDD=2.5V to 3.6V VIH=VDD and VIL=GND 0.08 uA IDD (Power-Down Mode) 1 DC specifications tested with the outputs unloaded. 2 Linearity is tested using a reduced code range: CBM53D04 (Code 8 to Code 248); CBM53D14 (Code 28 to Code 995); CBM53D24 (Code 115 to Code 3981). 3 Guaranteed by design and characterization, not production tested. 4 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF=VDD and offset plus gain error must be positive. 5 IDD specification is valid for all DAC codes; interface inactive; all DACs active; load currents excluded. AC Characteristics Table 4 VDD=2.5V to 5.5V; VREF=2V; RL=2KΩ to GND ; CL=200pF to GND; Ta=25℃; unless otherwise noted. Parameter1 Sym Test Condition Min Typ Max Unit Output Voltage Setting Time 1/4 scale to 3/4 scale CBM53D04 change(0x40 to 0xC0) 7 uS 8 uS 9 uS 1/4 scale to 3/4 scale CBM53D14 change(0x100 to 0x300) 1/4 scale to 3/4 scale CBM53D24 change(0x400 to 0xC00) 5 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Slew Rate 0.7 V/uS 40 nV-sec Digital Feedthrough 1 nV-sec Digital Crosstalk 1 nV-sec DAC-to-DAC Crosstalk 3 nV-sec 200 kHz -70 dB Major-Code Transition 1 LSB change around major Glitch Energy carry Multiplying Bandwidth VREF=2V±0.1VP-P VREF=2.5V±0.1VP-P; Total Harmonic Distortion Frequency=10KHz 1 Guaranteed by design and characterization, not production tested. Timing Characteristics VDD = 2.5V to 5.5V; all specifications TMIN to TMAX, unless otherwise noted. Parameter1,2,3 Limit at TMIN, TMAX Unit Test Conditions/Comments VDD=2.5V to 3.6V VDD=3.6V to 5.5V t1 40 33 ns min SCLK cycle time t2 16 13 ns min SCLK high time t3 16 13 ns min SCLK low time t4 16 13 ns min t5 5 5 ns min Data setup time t6 4.5 4.5 ns min Data hold time t7 0 0 ns min t8 80 33 ns min SYNC to SCLK falling edge setup time SCLK falling edge to SYNC rising edge Minimum SYNC high time 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 3. 6 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Figure 3. Serial Interface Timing Diagram Pin Configurations Figure 4. MSOP10L Pin Configuration 7 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Pin Function Descriptions Table 5 Pin Name Pin No. Function VDD 1 Power VOUTA 2 O VOUTB 3 O VOUTC 4 O Refin 5 I VOUTD 6 O GND 7 Ground Description Power Supply Input. These parts can be operated from 2.5V to 5.5V and the supply can be decoupled to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Reference Input Pin for All Four DACs. It has an input range from 0.25V to VDD. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Input. Din 8 I This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The Din input buffer is powered down after each write cycle. Serial Clock Input. Data is clocked into the input shift register on the falling Sclk 9 I edge of the serial clock input. Data can be transferred at clock speeds up to 30MHz. The Sclk input buffer is powered down after each write cycle. 8 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Active Low Control Input. This is the frame synchronization signal for the input data. When goes low, it enables the input shift register and data is transferred in on the falling edges of the following Sync 10 I 16clocks. If SYNC is taken high before the 16th falling edge of Sclk, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. I：Input, O：Output Typical Performance Characteristic Figure 5. CBM53D14 Typical INL Plot 9 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Figure 6. CBM53D24 Typical INL Plot Figure 7. CBM53D14 Typical DNL Plot 10 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Figure 8. CBM53D24 Typical DNL Plot Figure 9. Vout Source and Sink Current Capability 11 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Figure 10. Half-scale setting (0.25 to 0.75 Scale Code Change) Figure 11. Exiting Power-down to Midscale 12 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Functional Description The CBM53D04/CBM53D14/CBM53D24 are quad, resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10 and 12 bits, respectively. Each contains four output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5V to 5.5V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/us. The four DACs share a single reference input pin. The devices have programmable power-down modes, in which all DACs can be turned off completely with a high impedance output. The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the Refin pin provides the reference voltage for the DAC. The input coding to the DAC is straight binary, the ideal output voltage is given by VOUT = VREF ×D … … … … … … … … … …Formula 1 2N Where D=decimal equivalent of the binary code that is loaded to the DAC register: 0–255 for CBM53D04 (8 bits) 0—1023 for CBM53D14(10 bits) 0—4095 for CBM53D24(12bits) N=DAC resolution. There is a single reference input pin for the four DACs. The reference input is not buffered. The user can have a reference voltage as low as 0.25V or as high as VDD because there is no restriction due to the headroom or footroom requirements of any reference amplifier. It is recommended to use a buffered reference in the external circuit. The input impedance is typical 45kΩ. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0V to VDD when the reference is VDD. It is capable of driving a load of 2kΩ to GND or VDD , in parallel with 500pF to GND or VDD. The slew rate is 0.7V/us with a half-scale settling time to ±0.5LSB(at 12 bits) of 8us. The CBM54D04/CBM53D14/CBM53D24 are provided with a power-on reset function, so that they power up in a defined state. The power-on state uses normal operation and an output voltage set to 0V. Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. The CBM54D04/CBM53D14/CBM53D24 are controlled over a versatile, 3-wire serial interface that operates at clock rates up to 30MHz and are compatible with SPI,QSPI,MICROWIRE, and DSP interface standards. 13 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet The 3-wire serial interface (a). CBM53D04 Input Shift Register Contents (b). CBM53D14 Input Shift Register Contents (c). CBM53D24 Input Shift Register Contents Figure42. CBM53D04/CBM53D14/CBM53D24 Input Shift Register Contents Input Shift Register The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, Sclk. The 16-bit word consists of four control bits followed by 10 or 12 bits of DAC data, depending on the device type. Data is loaded MSB first (Bit15) and the first two bits determine whether the data is for DAC A ,DAC B ,DAC C, or DAC D. Bit 13 and Bit 12 control the operating mode of the DAC. Bit 13 is PD, and determines whether the part is in normal or power-down mode. Bit 12 is LDAC, and controls when DAC registers and outputs are updated. Table 6 Address Bits A1 A0 DAC Addressed 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D 14 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Address and Control Bits PD: 0: All four DACs go into power-down mode, consuming only 200nA @ 5V. The DAC outputs enter a high impedance state. 1: Normal operation. LDAC 0: All four DAC registers and, therefore, all DAC outputs updated simultaneously on completion of the write sequence. 1: Only addressed input register is updated. There is no change in the content of the DAC registers. The CBM53D24 uses all 12 bits of DAC data; the CBM53D14 uses 10 bits and ignores the 2 LSB Bits. The CBM53D04 uses 8 bits and ignores the last four bits. The data format is straight binary, with all 0s corresponding to 0V output and all 1s corresponding to full-scale output (VREF-1LSB). The Sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while Sync is low. To start the serial data transfer, take Sync low. After Sync goes low, serial data shifts into the device's input shift register on the falling edges of Sclk for 16 clock pulses. Any data and clock pulses after the 16th falling edge of Sclk are ignored because the Sclk and Din input buffers are powered down. No further serial data transfer occurs until Sync is taken high and low again. Sync can be taken high after the falling edge of the 16th Sclk pulse. After the end of the serial data transfer, data automatically transfers from the input shift register to the input register of the selected DAC. If Sync is taken high before the 16th falling edge of Sclk, the data transfer is aborted and the DAC input registers are not updated. When data has been transferred into three of the DAC input registers, all DAC registers and all DAC outputs are simultaneously updated by setting LDAC low when writing to the remaining DAC input register. Low Power Serial Interface To reduce the power consumption of the device even further, the interface fully powers up only when the device is being written to, that is , on the falling edge of Sync. As soon as the 16-bit control word has been written to the part, the Sclk and Din input buffers are powered down. They power up again only following a falling edge of Sync. 15 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet Double-Buffered Interface The CBM53D04/CBM53D14/CBM53D24 DACs have double-buffered interfaces consisting of two banks of registers－input registers and DAC registers. The input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. Access to the DAC register is controlled by the LDAC bit. When the LDAC bit is set high, the DAC register is latched and hence the input register can change state without affecting the contents of the DAC register. However, when the LDAC bit is set low, all DAC registers are update after a complete write sequence. This is useful if the user requires simultaneous updating of all DAC outputs. The user can write to three of the input registers individually and then, by setting the LDAC bit low when writing to the remaining DAC input register, all outputs update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been update since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input register. In the case of the CBM53D04/CBM53D14/CBM53D24 the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. Power-Down Mode The CBM53D04/CBM53D14/CBM53D24 have low power consumption, dissipation only 1.5mW with a 3V supply and 3mW with a 5V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, selected by a 0 on Bit 13 (PD) of the control word. When the PD bit is set to 1, all DACs work normally with a typical power consumption of 600uA at 5V (500uA at 3V ). However, in power-down mode, the supply current falls to 200nA at 5V (80nA at 3V) when all DACs are powered down. Not only does the supply current drop, but also the output stage is internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is three-stated while the part is in power-down mode, and provides a defined input condition for whatever is connected to the output of the DAC amplifier. 16 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 5us. This is the time from the falling edge of the 16th Sclk pulse to when the output voltage deviates from its power down voltage. Typical Application Circuit The CBM53D04/CBM53D14/CBM53D24 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0V to VDD. More typically, these devices are used with a fixed, precision reference voltage. If an output range of 0V to VDD is required, the simplest solution is to connect the reference input to VDD. As this supply is not very accurate and can be noisy, the CBM53D04/CBM53D14/CBM53D24 can be powered from the reference voltage; for example, using a 5V reference. The current required is 600uA supply current and approximately 112uA into the reference input. This is with no load on the DAC outputs. When the DAC outputs are loaded, the reference also needs to supply the current to the loads. Decoding Multiple CBM53D04/CBM53D14/CBM53D24 The SYNC pin on the CBM53D04/CBM53D14/CBM53D24 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but SYNC can only be active to one of the devices at any one time, allowing access to only one DAC in this system. The 74HC139 can be used as a 2-to-4-line decoder to address any of the DACs in the system. To prevent timing errors, the enable input must be brought to its inactive state while the coded address inputs are changing state. Power Supply Bypassing and Grounding In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the CBM53D04/CBM53D14/CBM53D24 is mounted is designed so that the analog and digital sections are separated and confined to certain areas of the board. If the CBM53D04/CBM53D14/CBM53D24 are in a system where multiple devices require an AGNDto-DGND connection, the connection is made at one point only. The star ground point is established as close as possible to the device. 17 www.corebai.com CBM53D04/CBM53D14/CBM53D24 Datasheet The CBM53D04/CBM53D14/CBM53D24 has ample supply bypassing of 10uF in parallel with 0.1uF on the supply located as close to the package as possible, ideally right up against the device. The 10uF capacitors are the tantalum bead type. The 0.1uF capacitor has low effective series resistance (ESR) and effective series inductance (ESI). The power supply lines of the CBM53D04/CBM53D14/CBM53D24 use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks are shielded with digital ground to avoid radiating noise to other parts of the board, and are never run near the reference inputs .Avoid crossover of digital and analog signals. Traces on opposite sides of the board run at right angles to each other. This reduces the effects of feedthrough through the board. Outline Dimensions SYBMOL MILLIMETER MIN NOM MAX A - - 1.10 A1 0.05 - 0.15 A2 0.75 0.85 0.95 A3 0.30 0.35 0.40 b 0.19 - 0.28 b1 0.18 0.20 0.23 c 0.15 - 0.20 c1 0.14 0.152 0.16 D 2.90 3.00 3.10 E 4.70 4.90 5.10 E1 2.90 3.00 3.10 e L 0.50 BSC 0.40 L1 θ L/F 载体尺寸 （mil） Figure 5 MSOP10L Dimensions shown in millimeters - 0.70 0.95 BSC 0 - 8° 71×96 18 www.corebai.com