XD74LS00

XD74LS00 DIP14 / XL74LS00 SOP14 1 Features 2 Applications • • • • • • • 1 • • • • Package Options Include: – Plastic Small-Outline (D, NS, PS) – Shrink Small-Outline (DB) – Ceramic Flat (W) – Ceramic Chip Carriers (FK) – Standard Plastic (N) – Ceramic (J) Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package Inputs Are TTL Compliant; VIH = 2 V and VIL = 0.8 V Inputs Can Accept 3.3-V or 2.5-V Logic Inputs 5400, 54LS00, and 54S00 are Characterized For Operation Over the Full Military Temperature Range of –55ºC to 125ºC AV Receivers Portable Audio Docks Blu-Ray Players Home Theater MP3 Players or Recorders Personal Digital Assistants (PDAs) Logic Diagram, Each Gate (Positive Logic) A Y B 5 Pin Configuration and Functions 74LS00 D, DB, N, and NS Packages 14-Pin CDIP, CFP, SOIC, PDIP, SO, or SSOP Top View 1A 1 14 VCC 1B 2 13 4A 1Y 3 12 4B 2A 4 11 4Y 2B 5 10 3A 2Y 6 9 3B GND 7 8 3Y 74LS00 PS Package 18-Pin SO Top View 1A 1 14 4Y 1B 2 13 4B 1Y 3 12 4A VCC 4 11 GND 2Y 5 10 3B 2A 6 9 3A 2B 7 8 3Y Not to scale Not to scale 1 1 XD74LS00 DIP14 / XL74LS00 SOP14 Pin Functions PIN I/O DESCRIPTION CDIP, CFP, SOIC, PDIP, SO, SSOP SO 74LS00 CFP (5400) LCCC 1A 1 1 1 2 I Gate 1 input 1B 2 2 2 3 I Gate 1 input 1Y 3 3 3 4 O Gate 1 output 2A 4 6 6 6 I Gate 2 input 2B 5 7 7 8 I Gate 2 input 2Y 6 5 5 9 O Gate 2 output 3A 10 — 9 13 I Gate 3 input 3B 9 — 10 14 I Gate 3 input NAME Pin Functions (continued) PIN CDIP, CFP, SOIC, PDIP, SO, SSOP SO (74LS00) 3Y 8 4A 13 4B 4Y I/O DESCRIPTION CFP (5400) LCCC — 8 12 O Gate 3 output — 12 18 I Gate 4 input 12 — 13 19 I Gate 4 input 11 — 14 16 O Gate 4 output GND 7 4 11 10 — Ground NC — — — 1, 5, 7, 11, 15, 17 — No connect VCC 14 8 4 20 — Power supply NAME 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage, VCC (2) x400 and xS400 Input voltage 74LS00 V 7 Storage temperature, Tstg (2) UNIT 7 5.5 Junction temperature, TJ (1) MAX –65 V 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltage values are with respect to network ground terminal. 6.2 ESD Ratings: 74LS00 VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 ±2000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. ESD Tested on 74LS00 package. 2 XD74LS00 DIP14 / XL74LS00 SOP14 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current IOL Low-level output current MIN NOM MAX 54xx00 4.5 5 5.5 74xx00 4.75 5 5.25 2 UNIT V V x400, 7LS400, and x4S00 0.8 54LS00 0.7 5400, 54LS00, and 74LS00 –0.4 x4S00 –1 x400 16 5LS400 4 7LS400 8 x4S00 V mA mA 20 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) MIN TA Operating free-air temperature NOM MAX 54xx00 –55 125 74xx00 0 70 3 UNIT °C XD74LS00 DIP14 / XL74LS00 SOP14 6.4 Thermal Information 74LS00 THERMAL METRIC (1) (2) RθJA D (SOIC) DB (SSOP) N (PDIP) NS (SO) 14 PINS 14 PINS 14 PINS 14 PINS 90.9 102.8 54.8 89.7 °C/W 51.9 53.3 42.1 48.1 °C/W 48 53.4 34.8 50.1 °C/W Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance UNIT RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter 18.6 16.5 26.9 16.7 °C/W ψJB Junction-to-board characterization parameter 47.8 52.9 34.7 49.8 °C/W 6.5 Electrical Characteristics: x400 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –1.5 V VIK VCC = MIN and II = –12 mA VOH VCC = MIN, VIL = 0.8 V, and IOH = –0.4 mA VOL VCC = MIN, VIH = 2 V, and IOL = 16 mA II VCC = MAX and VI = 5.5 V IIH VCC = MAX and VI = 2.4 V 40 µA IIL VCC = MAX and VI = 0.4 V –1.6 mA IOS VCC = MAX ICCH VCC = MAX and VI = 0 V ICCL VCC = MAX and VI = 4.5 V 2.4 3.4 0.2 V 0.4 1 5400 –20 –55 7400 –18 –55 V mA mA 4 8 mA 12 22 mA TYP MAX UNIT –1.5 V 6.6 Electrical Characteristics: 74LS00 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIK VCC = MIN and II = –18 mA VOH VCC = MIN, VIL = MAX, and IOH = –0.4 mA VOL VCC = MIN and VIH = 2 V II VCC = MAX and VI = 7 V 0.1 mA IIH VCC = MAX and VI = 2.7 V 20 µA IIL VCC = MAX and VI = 0.4 V IOS VCC = MAX ICCH VCC = MAX and VI = 0 V ICCL VCC = MAX and VI = 4.5 V 2.5 3.4 V IOL = 4 mA 0.25 0.4 IOL = 8 mA (74LS00) 0.35 0.5 V –0.4 mA –100 mA 0.8 1.6 mA 2.4 4.4 mA –20 6.7 Electrical Characteristics: x4S00 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 2.5 3.4 MAX UNIT –1.2 V VIK VCC = MIN and II = –18 mA VOH VCC = MIN, VIL = 0.8 V, and IOH = –1 mA VOL VCC = MIN, VIH = 2 V, and IOL = 20 mA II VCC = MAX and VI = 5.5 V 1 IIH VCC = MAX and VI = 2.7 V 50 µA IIL VCC = MAX and VI = 0.5 V –2 mA 4 V 0.5 V mA XD74LS00 DIP14 / XL74LS00 SOP14 Electrical Characteristics: x4S00 (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP –40 MAX UNIT IOS VCC = MAX –100 mA ICCH VCC = MAX and VI = 0 V 10 16 mA ICCL VCC = MAX and VI = 4.5 V 20 36 mA 6.8 Switching Characteristics: x400 VCC = 5 V, TA = 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2. PARAMETER tPLH FROM (INPUT) TO (OUTPUT) A or B tPHL Y TEST CONDITIONS MIN RL = 400 Ω and CL = 15 pF TYP MAX 11 22 7 15 TYP MAX 9 15 10 15 UNIT ns 6.9 Switching Characteristics: x4LS00 VCC = 5 V, TA = 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2. PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) TEST CONDITIONS A or B Y RL = 2 kΩ and CL = 15 pF MIN UNIT ns 6.10 Switching Characteristics: x4S00 VCC = 5 V, TA = 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2. PARAMETER tPLH tPHL FROM (INPUT) A or B A or B TO (OUTPUT) Y Y TYP MAX RL = 280 Ω and CL = 15 pF TEST CONDITIONS 3 4.5 RL = 280 Ω and CL = 50 pF 4.5 RL = 280 Ω and CL = 15 pF 3 RL = 280 Ω and CL = 50 pF 5 6.11 Typical Characteristics CL = 15 pF Figure 1. TPHL (Across Devices) 5 MIN 5 UNIT ns XD74LS00 DIP14 / XL74LS00 SOP14 7 Parameter Measurement Information 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width VCC Test Point VCC RL (see Note B) From Output Under Test CL (see Note A) High-Level Pulse 1.5 V 1 kΩ Test Point S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL CL (see Note A) RL From Output Under Test VCC From Output Under Test Test Point 3V Timing Input 1.5 V 1.5 V 0V tw Low-Level Pulse 1.5 V tsu Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.5 V 0V In-Phase Output (see Note D) tPHL VOH 1.5 V Out-of-Phase Output (see Note D) 0V 1.5 V 1.5 V Waveform 1 (see Notes C and D) tPLZ VOH 1.5 V 1.5 V VOL Waveform 2 (see Notes C and D) ≈1.5 V 1.5 V VOL tPZH tPLH 1.5 V 0V tPZL VOL tPHL 1.5 V 3V Output Control (low-level enabling) 1.5 V tPLH 3V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th VOL + 0.5 V tPHZ VOH 1.5 V VOH − 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and t PLZ; S1 is open and S2 is closed for t PZH; S1 is closed and S2 is open for t PZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 6 XD74LS00 DIP14 / XL74LS00 SOP14 8 Detailed Description 8.1 Overview The 74LS00 devices are quadruple, 2-input NAND gates which perform the Boolean function Y = A .B or Y = A + B in positive logic. 8.2 Functional Block Diagram A Y B 8.3 Feature Description The operating voltage of 74LS00 is from 4.75-V to 5.25-V VCC. The operating voltage of 54xx00 is from 4.5V to 5.5-V VCC. The 54xx00 devices are rated from –55°C to 125°C whereas 74LS00 device are rated from 0°C to 70°C. 8.4 Device Functional Modes Table 1 lists the functions of the devices. Table 1. Functional Table (Each Gate) INPUTS OUTPUT A B Y H H L L X H X L H 7 XD74LS00 DIP14 / XL74LS00 SOP14 78 XD74LS00 DIP14 / XL74LS00 SOP14 79