XD74HC573

XD74HC573 DIP-20 XL74HC573 SOP-20 1 Features 3 Description • • The 74HC573 devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 • • • • • Wide Operating Voltage Range from 2 V to 6 V High-Current 3-State Outputs Drive Bus Lines Directly up to 15 LSTTL Loads Low Power Consumption: 80-µA Maximum ICC Typical tpd = 21 ns ±6-mA Output Drive at 5 V Low Input Current: 1 µA (Maximum) Bus-Structured Pinout While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. 2 Applications • • • Buffer Registers Bidirectional Bus Drivers Working Registers 4 Logic Diagram (Positive Logic) OE LE 1 11 C1 1D 2 19 1D To Seven Other Channels 1 1 1Q XD74HC573 DIP-20 XL74HC573 SOP-20 5 Pin Configuration and Functions DIP/SOP OE 1 20 VCC 1D 2 19 1Q 2D 3 18 2Q 3D 4 17 3Q 4D 5 16 4Q 5D 6 15 5Q 6D 7 14 6Q 7D 8 13 7Q 8D 9 12 8Q 10 11 LE GND Not to scale Pin Functions PIN NO. NAME I/O DESCRIPTION 1 OE I Output enable 2 1D I 1D input 3 2D I 2D input 4 3D I 3D input 5 4D I 4D input 6 5D I 5D input 7 6D I 6D input 8 7D I 7D input 9 8D I 8D input 10 GND — Ground 11 LE I Latch enable input 12 8Q O 8Q output 13 7Q O 7Q output 14 6Q O 6Q output 15 5Q O 5Q output 16 4Q O 4Q output 17 3Q O 3Q output 18 2Q O 2Q output 19 1Q O 1Q output 20 VCC — Power pin 2 XD74HC573 DIP-20 XL74HC573 SOP-20 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage (2) MIN MAX UNIT –0.5 7 V IIK Input clamp current VI < 0 or VI > VCC ±20 mA IOK Output clamp current (2) VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±35 mA Continuous current through VCC or GND ±70 mA TJ Junction temperature 150 °C Tstg Storage temperature 150 °C (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) UNIT V ±1000 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V MIN NOM MAX 2 5 6 Low-level input voltage 3.15 Input voltage VO Output voltage 0.5 VCC = 4.5 V 1.35 TA Input transition (rise and fall) time Operating free-air temperature 0 0 VCC V VCC V 1000 VCC = 4.5 V 500 VCC = 6 V 400 74HC573 3 V 1.8 VCC = 2 V tt V 4.2 VCC = 6 V VI V 1.5 VCC = 2 V VIL UNIT –40 85 ns °C XD74HC573 DIP-20 XL74HC573 SOP-20 6.4 Thermal Information 74HC573 THERMAL METRIC (1) DW (SOIC) N (PDIP) UNIT 20 PINS 20 PINS RθJA Junction-to-ambient thermal resistance 78.3 49.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 42.8 35.9 °C/W RθJB Junction-to-board thermal resistance 46.2 30 °C/W ψJT Junction-to-top characterization parameter 18 22.4 °C/W ψJB Junction-to-board characterization parameter 45.7 29.9 °C/W 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 µA VOH VI = VIH or VIL MIN TYP VCC = 2 V 1.9 1.998 VCC = 4.5 V 4.4 4.499 VCC = 6 V 5.9 5.999 TA = 25°C 3.98 4.3 74HC573 3.84 TA = 25°C 5.48 74HC573 5.34 MAX IOH = –6 mA, VCC = 4.5 V UNIT V 5.8 IOH = –7.8 mA, VCC = 6 V IOL = 20 µA VOL VI = VIH or VIL VCC = 2 V 0.002 0.1 VCC = 4.5 V 0.001 0.1 VCC = 6 V 0.001 0.1 TA = 25°C 0.17 0.26 IOL = 6 mA, VCC = 4.5 V V 74HC573 TA = 25°C 0.33 0.15 0.26 ±0.1 ±100 IOL = 7.8 mA, VCC = 6 V 74HC573 II VI = VCC or 0, VCC = 6 V IOZ VO = VCC or 0, VCC = 6 V TA = 25°C 74HC573 TA = 25°C ICC ±1000 ±0.01 µA 74HC573 ±5 TA = 25°C 8 74HC573 80 µA VCC = 2 V to 6 V Power dissipation capacitance per latch nA ±0.5 VI = VCC or 0, IO = 0, VCC = 6 V Ci Cpd 0.33 3 TA = 25°C, no load 50 4 10 pF pF XD74HC573 DIP-20 XL74HC573 SOP-20 6.6 Timing Requirements over operating free-air temperature range (unless otherwise noted) MIN TA = 25°C 80 74HC573 100 TA = 25°C 16 74HC573 20 TA = 25°C 14 74HC573 17 TA = 25°C 50 74HC573 63 TA = 25°C 10 NOM MAX UNIT VCC = 2 V tw Pulse duration, LE high VCC = 4.5 V ns VCC = 6 V VCC = 2 V tsu Setup time, data before LE↓ VCC = 4.5 V ns 74HC573 13 TA = 25°C 9 74HC573 11 TA = 25°C 20 74HC573 24 VCC = 6 V VCC = 2 V th Hold time, data after LE↓ VCC = 4.5 V 5 VCC = 6 V 5 ns 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted; see Figure 2) PARAMETER TEST CONDITIONS MIN TA = 25°C VCC = 2 V VCC = 4.5 V 77 175 VCC = 6 V 26 TA = 25°C VCC = 2 V 23 VCC = 4.5 V 87 74HC573 5 175 220 27 74HC573 TA = 25°C VCC = 6 V 30 38 74HC573 TA = 25°C 35 44 74HC573 tpd UNIT 220 74HC573 TA = 25°C CL = 50 pF, from LE (input) to any Q (output) MAX 74HC573 TA = 25°C CL = 50 pF, from D (input) to Q (output) TYP 35 44 23 30 38 ns XD74HC573 DIP-20 XL74HC573 SOP-20 Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted; see Figure 2) PARAMETER TEST CONDITIONS MIN TA = 25°C TYP MAX 68 150 UNIT VCC = 2 V 74HC573 TA = 25°C ten CL = 50 pF, from OE (input) to any Q (output) 190 24 30 VCC = 4.5 V ns 74HC573 TA = 25°C 38 21 26 47 150 VCC = 6 V 74HC573 TA = 25°C 32 VCC = 2 V 74HC573 TA = 25°C tdis CL = 50 pF, from OE (input) to any Q (output) 190 23 30 VCC = 4.5 V ns 74HC573 TA = 25°C 38 21 26 VCC = 6 V 74HC573 TA = 25°C 32 28 60 VCC = 2 V 74HC573 TA = 25°C tt CL = 50 pF to any Q (output) 75 8 12 VCC = 4.5 V ns 74HC573 TA = 25°C 15 6 10 VCC = 6 V 74HC573 TA = 25°C 13 95 200 VCC = 2 V 74HC573 TA = 25°C CL = 150 pF, from D (input) to Q (output) 250 33 40 VCC = 4.5 V 74HC573 TA = 25°C 50 21 34 103 225 VCC = 6 V 74HC573 tpd TA = 25°C 43 VCC = 2 V 74HC573 TA = 25°C CL = 150 pF, from LE (input) to any Q (output) 285 33 45 VCC = 4.5 V 74HC573 TA = 25°C 57 29 40 VCC = 6 V 74HC573 6 50 ns XD74HC573 DIP-20 XL74HC573 SOP-20 Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted; see Figure 2) PARAMETER TEST CONDITIONS MIN TA = 25°C VCC = 2 V CL = 150 pF, from OE (input) to any Q (output) VCC = 4.5 V 29 26 74HC573 VCC = 2 V 60 17 74HC573 14 74HC573 250 CL 50pF CL 150pF TPD Max(ns) 200 175 150 125 100 75 50 25 3 3.5 4 Vcc 4.5 5 5.5 6 D001 Figure 1. Maximum Propagation Delay Curves 7 42 36 45 6.8 Typical Characteristics 2.5 210 53 TA = 25°C 225 34 265 TA = 25°C VCC = 6 V ns 43 74HC573 VCC = 4.5 V 40 50 TA = 25°C 2 200 74HC573 VCC = 6 V CL = 150 pF to any Q (output) 85 UNIT 250 TA = 25°C tt MAX 74HC573 TA = 25°C ten TYP ns XD74HC573 DIP-20 XL74HC573 SOP-20 7 Parameter Measurement Information VCC PARAMETER S1 Test Point From Output Under Test ten RL tPZH RL CL 50 pF or 150 pF 1 kΩ tPZL tdis S2 tPLZ 1 kΩ 50 pF −− 50 pF or 150 pF tpd or tt LOAD CIRCUIT 50% Open Open Closed Closed Open Open Open 50% 0V 50% tsu 0V tw Data 50% Input 10% VCC Low-Level Pulse 50% 50% 50% 0V tPLH 50% 10% tPHL 90% 90% tr tPHL 90% VOH 50% 10% V OL tf tPLH 50% 10% 90% 90% VCC 50% 10% 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VCC 50% th tr 0V VOLTAGE WAVEFORMS PULSE DURATIONS Out-ofPhase Output Closed VCC Reference Input VCC High-Level Pulse In-Phase Output S2 Closed tPHZ CL (see Note A) Input S1 Open 50% 10% tf 90% VOH VOL tr Output Control (Low-Level Enabling) VCC 50% tPZL Output Waveform 1 (See Note B) 50% 0V tPLZ 10% tPZH Output Waveform 2 (See Note B) ≈VCC ≈VCC 50% tPHZ 50% 90% A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES F. VOL Figure 2. Load Circuit and Voltage Waveforms 8 XD74HC573 DIP-20 XL74HC573 SOP-20 8 Detailed Description 8.1 Overview The 74HC573 devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 8.2 Functional Block Diagram OE LE 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels Figure 3. Logic Diagram (Positive Logic) 8.3 Feature Description The 74HC573 is a high current 3-state output device which can drive bus lines directly or up to 15 LSTTL loads. It has low power consumption up to 80-µA maximum ICC. The high speed CMOS family has typical propagation delay of 21 ns with ±6-mA output drive at 5 V. The input leakage current is a very low 1-µA (maximum). 8.4 Device Functional Modes Table 1 lists the functional modes of the 74HC573 Table 1. Function Table (Each Latch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q0 H X X Hi-Z 9 XD74HC573 DIP-20 XL74HC573 SOP-20 SOP 910 XD74HC573 DIP-20 XL74HC573 SOP-20 DIP 911