XD74LS14

XD74LS14 DIP-14 XL74LS14 SOP-14 1 Features 3 Description • • • Each circuit in XD/XL74LS14 functions asan inverter. However, because of the Schmitt-Triggeraction, they have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean, jitter-free output signals. 1 Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity 2 Applications • • • • • • HVAC Gateways Residential Ductless Air Conditioning Outdoor Units Robotic Controls Industrial Stepper Motors Power Meter and Power Analyzers Digital Input Modules for Factory Automation 4 Logic Diagram (Positive Logic) A Y 1 1 XD74LS14 DIP-14 XL74LS14 SOP-14 5 Pin Configuration and Functions DIP/SOP Top View 1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y Pin Functions PIN NAME DIP/SOP I/O DESCRIPTION 1A 1 I Channel 1 input 1Y 2 O Channel 1 output 2A 3 I Channel 2 input 2Y 4 O Channel 2 output 3A 5 I Channel 3 input 3Y 6 O Channel 3 output 4A 9 I Channel 4 input 4Y 8 O Channel 4 output 5A 11 I Channel 5 input 5Y 10 O Channel 5 output 6A 13 I Channel 6 input 6Y 12 O Channel 6 output GND 7 — Ground NC — — No internal connection VCC 14 — Power supply 2 XD74LS14 DIP-14 XL74LS14 SOP-14 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 7 V Supply voltage, VCC (2) 5.5 XD/XL74LS14 Input voltage Junction temperature, TJ Storage temperature, Tstg (1) (2) V 7 –65 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltage values are with respect to network ground terminal. 6.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000 UNIT V 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage XD/XL74LS14 IOH High-level output current XD/XL74LS14 IOL Low-level output current XD/XL74LS14 MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 –0.8 –0.4 UNIT V mA 16 4 mA 8 TA Operating free-air temperature XD/XL74LS14 3 –55 125 0 70 °C XD74LS14 DIP-14 XL74LS14 SOP-14 6.4 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VT+ VCC = 5 V 74LS14 VT– VCC = 5 V Hysteresis (VT+ – VT–) VCC = 5 V VIK VOH MIN TYP (2) 1.5 1.7 2 1.4 1.6 1.9 0.6 0.9 1.1 0.5 0.8 1 0.4 0.8 –1.5 VCC = MIN, II = –18 mA, XD/XL74LS14 –1.5 VCC = MIN, VI = 0.6 V, IOH = –0.8 mA, XD/XL74LS14 2.4 3.4 VCC = MIN, VI = 0.5 V, IOH = –0.4 mA, XD/XL74LS14 2.4 3.4 VCC = MIN, VI = 1.9 V 0.4 IOL = 4 mA, XD/XL74LS14 0.25 0.4 IOL = 8 mA, XD/XL74LS14 0.35 0.5 VCC = 5 V, VI = VT+ XD/XL74LS14 IT– VCC = 5 V, VI = VT– XD/XL74LS14 IIH –0.56 1 0.1 VCC = MAX, VIH = 2.4 V, XD/XL74LS1414 40 VCC = MAX, VIH = 2.7 V, XD/XL74LS14 20 XD/XL74LS14 IOS (3) VCC = MAX XD/XL74LS14 ICCH VCC = MAX XD/XL74LS14 ICCL VCC = MAX XD/XL74LS14 V V mA VCC = MAX, VI = 7 V, XD/XL74LS14 VCC = MAX, VIL = 0.4 V V mA –0.14 –0.18 IIL (1) (2) (3) –0.43 VCC = MAX, VI = 5.5 V, XD/XL74LS14 II V V 0.2 IT+ UNIT V VCC = MIN, II = –12 mA, XD/XL74LS14 VCC = MIN, VI = 2 V, IOL = 16 mA, XD/XL74LS14 VOL MAX –0.8 –1.2 –0.4 –18 –55 –20 –100 22 36 8.6 16 39 60 12 21 mA µA mA mA mA mA For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V and TA = 25°C. Not more than one output should be shorted at a time. 6.5 Switching Characteristics VCC = 5 V, TA = 25°C, and over operating free-air temperature range (unless otherwise noted; see Figure 13) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS tPLH A Y RL = 400 Ω and CL = 15 pF, or RL = 2 kΩ and CL = 15 pF tPHL A Y RL = 400 Ω and CL = 15 pF, or RL = 2 kΩ and CL = 15 pF 4 MIN TYP MAX UNIT 15 22 ns 15 22 ns XD74LS14 DIP-14 XL74LS14 SOP-14 6.5.1 XD/XL74LS14 Circuits Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for XD/XL74LS14 only. 0.90 VCC = 5 V 1.69 VT– – Negative-Going Threshold Voltage – V V T+ – Positive-Going Threshold Voltage – V 1.70 1.68 1.67 1.66 1.65 1.64 1.63 1.62 1.61 VCC = 5 V 0.89 0.88 0.87 0.86 0.85 0.84 0.83 0.82 0.81 0.80 1.60 –75 –50 –25 0 25 50 75 100 –75 –50 125 TA – Free-Air Temperature –°C 0 25 50 75 100 –25 TA – Free-Air Temperature –°C 125 Figure 2. Negative-Going Threshold Voltage vs Free-Air Temperature Figure 1. Positive-Going Threshold Voltage vs Free-Air Temperature 850 Relative Frequency of Occurence V T+ – VT– – Hysteresis – V VCC = 5 V TA = 25°C VCC = 5 V 840 830 820 810 800 790 780 770 99% ARE ABOVE 735 mV 760 750 –75 –50 –25 0 25 50 75 100 720 125 740 TA – Free-Air Temperature –°C Figure 3 760 780 800 820 840 860 880 VT+ – VT– – Hysteresis – mV Hysteresis vs Free-Air Temperature Figure 4 Distribution of Units for Hysteresis 4 2.0 VCC = 5 V TA = 25°C TA = 25°C 1.8 VT– VT+ 3 Positive-Going Threshold Voltage, VT+ 1.4 VO – Output Voltage – V Threshold Voltage – V 1.6 1.2 Negative-Going Threshold Voltage, VT– 1.0 0.8 Hysteresis, VT+ – VT– 0.6 2 1 0.4 0.2 0 0 4.5 4.75 5 5.25 0 5.5 VCC – Supply Voltage – V Figure 5 0.4 0.8 1.2 1.6 2 VI – Input Voltage – V Threshold Voltages and Hysteresis vs Supply Voltage Figure 6 5 Output Voltage vs Input Voltage XD74LS14 DIP-14 XL74LS14 SOP-14 7 Parameter Measurement Information 7.1 Series XD/XL74LS14 Devices Test Point VCC VCC RL RL From Output Under Test CL From Output Under Test Test Point CL Figure 7 Load Circuit For 2-State Totem-Pole Outputs VCC Test Point Figure 8 Load Circuit For Open-Collector Outputs High-Level Pulse RL 1.5 V 1.5 V S1 tw From Output Under Test Low-Level Pulse CL 1 kΩ 1.5 V 1.5 V S2 Figure 9 Load Circuit For 3-State Outputs Figure 10 Voltage Waveforms Pulse Durations 3V Timing Input 3V Input 1.5 V 1.5 V 1.5 V 0V 0V th tsu Data Input tPLH 3V 1.5 V In-Phase Output 1.5 V 0V tPHL VOH 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLH VOH 1.5 V 1.5 V VOL Figure 11 Voltage Waveforms Setup and Hold Times Figure 12 Voltage Waveforms Propagation Delay Times 6 XD74LS14 DIP-14 XL74LS14 SOP-14 Series XD/XL74LS14 Devices (continued) 3V Output Control (low-level enabling) 1.5 V 1.5 V 0V tPZL tPLZ Waveform 1 ≈1.5 V 1.5 V VOL tPZH VOL + 0.5 V tPHZ VOH Waveform 2 1.5 V VOH – 0.5 V ≈1.5 V A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. The outputs are measured one at a time with one input transition per measurement. Figure 13 Voltage Waveforms Enable and Disable Times, 3-State Outputs 7 XD74LS14 DIP-14 XL74LS14 SOP-14 www.ti.com 7.2 Series XD/XL74LS14 Devices Test Point VCC VCC RL RL From Output Under Test CL From Output Under Test Test Point CL Figure 14 Load Circuit For 2-State Totem-Pole Outputs VCC Test Point Figure 15 Load Circuit For Open-Collector Outputs High-Level Pulse RL 1.3 V 1.3 V S1 tw From Output Under Test Low-Level Pulse CL 5 kΩ 1.3 V 1.3 V S2 Figure 16 Load Circuit For 3-State Outputs Figure 17 Voltage Waveforms Pulse Durations 3V Timing Input 3V Input 1.3 V 1.3 V 1.3 V 0V 0V th tsu Data Input tPLH 3V 1.3 V In-Phase Output 1.3 V tPHL VOH 1.3 V 1.3 V 0V VOL tPHL Out-of-Phase Output tPLH VOH 1.3 V 1.3 V VOL Figure 18 Voltage Waveforms Setup and Hold Times Figure 19 Voltage Waveforms Propagation Delay Times 8 XD74LS14 DIP-14 XL74LS14 SOP-14 Series XD/XL74LS14 Devices (continued) Output Control (low-level enabling) 3V 1.3 V 1.3 V 0V tPZL Waveform 1 tPLZ ≈1.5 V 1.3 V VOL tPZH VOL + 0.5 V tPHZ VOH Waveform 2 1.3 V VOH – 0.5 V ≈1.5 V A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 20 Voltage Waveforms Enable and Disable Times, 3-State Outputs 9 XD74LS14 DIP-14 XL74LS14 SOP-14 Typical Application (continued) Application Curve VCC VT+(max) Voltage VT+ Typical VT+ 8 VT+(min) VT (max) |W VCC VT (min) ln | 1 |W VCC tdelay (max) ln | 1 t delay (min) VC VOUT 0.0 t0 t0 + 2 t0 + 32 t0 + 22 t0 + 42 t0 + 52 Time Figure 21 Ideal Capacitor Voltage and Output Voltage With Positive Switching Threshold 10 XD74LS14 DIP-14 XL74LS14 SOP-14 8.1 System Examples Here are some examples of various applications using the XD/XL74LS14 device. TTL System VT+ VT– Input CMOS Sine-Wave Oscillator Output Figure 22 TTL System Interface For Slow Input Waveforms Figure 23 Pulse Shaper 0.1 Hz to 10 MHz 330Ω VT+ VT– Input Input Output Figure 24 Multivibrator Figure 25 Threshold Detector Open-Collector Output Input Input A Output Point A Output Figure 26 Pulse Stretcher 11 VT+ XD74LS14 DIP-14 XL74LS14 SOP-14 9 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. The VCC terminal must have a good bypass capacitor to prevent power disturbance. TI recommends using a 0.1-µF capacitor on the VCC terminal, and must be placed as close as possible to the pin for best results. 10 Layout 10.1 Layout Guidelines When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such inputs must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or VCC, whichever makes more sense or is more convenient. Floating outputs are generally acceptable, unless the part is a transceiver. 10.2 Layout Example Vcc Unused Input Input Output Unused Input Input Figure 27 Layout Diagram 12 Output XD74LS14 DIP-14 XL74LS14 SOP-14 DIP 13 12 XD74LS14 DIP-14 XL74LS14 SOP-14 SOP 14 12