XD74LS73

XD74LS73 DIP-14 Pin Arrangement 1CK 1CLR 1 2 1K 3 VCC 4 2CK 14 1J Q 13 1Q Q 12 1Q 11 GND Q 10 2K Q 9 2Q 8 2Q CLR J CK K K 5 CK 2CLR 2J 6 J CLR 7 (Top view) Function Table Inputs Outputs Clear L Clock X J X K X Q L Q H H H ↓ ↓ L H L L Q0 H Q0 L H H ↓ ↓ L H H H L H H X X QO H Toggle H; high level, L; low level, X; irrelevant, ↓; transition from high to low level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓. 1 QO XD74LS73 DIP-14 Block Diagram (1/2) Q Q Clear K J Clock Absolute Maximum Ratings Symbol Ratings Unit Supply voltage Input voltage Item VCC VIN 7 7 V V Power dissipation Storage temperature PT Tstg 400 –65 to +150 mW °C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Pulse width Setup time Hold time Symbol Min Typ Max Unit VCC IOH 4.75 — 5.00 — 5.25 –400 V µA IOL Topr — –20 — 25 8 75 mA °C fclock tw (Clock High) 0 20 — — 30 — MHz tw (Clear Low) tsu (“H” Data) 25 20↓ — — — — tsu (“L” Data) th 20↓ 0↓ — — — — Note: ↓; The arrow indicates the falling edge. 2 ns ns ns XD74LS73 DIP-14 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH min. 2.0 typ.* — max. — Unit V VIL — — 0.8 V VOH 2.7 — — V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA VOL — — — — 0.5 0.4 V IOL = 8 mA IOL = 4 mA — — — — 20 60 µA VCC = 5.25 V, VI = 2.7 V — — — — 80 –0.4 — — — — –0.8 –0.8 mA VCC = 5.25 V, VI = 0.4 V — — 0.1 0.3 Output voltage J, K Clear IIH Clock J, K Input current IIL Clear Clock J, K Clear Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V II — — mA VCC = 5.25 V, VI = 7 V Clock Short-circuit output current IOS — –20 — — 0.4 –100 mA VCC = 5.25 V Supply current** Input clamp voltage ICC VIK — — 4 — 6 –1.5 mA V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** With all outputs open, ICC is measured with the Q and Q outputs high in turn. At time of measurement, the clock input is founded. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Symbol Maximum clock frequency fmax tPLH Propagation delay time Inputs Clear Clock tPHL Outputs Q, Q min. typ. max. Unit Condition 30 — 45 15 — 20 MHz ns CL = 15 pF, RL = 2 kΩ — 15 20 ns Timing Definition tw 3V 1.3 V 1.3 V 1.3 V Clock tsu th tsu 0V th 3V 1.3 V 1.3 V 1.3 V J, K 0V "H" Data "L" Data 3 XD74LS73 DIP-14 Testing Method Test Circuit 1. ƒmax, tPLH, tPHL, (Clock→Q, Q) VCC Output Q Input 4.5V RL J P.G. Q CL CK Zout=50Ω Load circuit 1 Output Q K CLR Notes: Q Same as Load Circuit 1. 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). 2. tPHL (Clear→Q), tPLH (Clear→Q) VCC Output Q 4.5V Input RL J P.G. Q CL CK Zout=50Ω Input Output Q K CLR Q Same as Load Circuit 1. P.G. Zout=50Ω Notes: Load circuit 1 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). 4 XD74LS73 DIP-14 Waveforms 1 tTLH Clock 10% tTHL tw(L) 90% 90% 1.3 V 1.3 V tw(H) 3V 1.3 V 1.3 V 10% 0V tPLH tPHL VOH 1.3 V Q 1.3 V tPHL VOL tPLH Q VOH 1.3 V 1.3 V VOL Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax, tTLH = tTHL ≤ 2.5 ns Waveforms 2 tTHL Clear tTLH 90% 1.3V 10% 3V 90% 1.3V 10% 0V tw (CLR) tTLH tTHL 3V Clock 10% 90% 90% 1.3V 1.3V tw (CK) ≥ 20ns tPHL 10% 0V VOH Q 1.3V tPLH VOL VOH 1.3V Q Note: VOL Crear and clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, 5 XD74LS73 DIP-14 DIP14 56