XD74LS161

XD74LS161 DIP-16 This synchronous 4-bit binary counter features an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input should be avoided when the clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional getting. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produced a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low-level transitions at the enable P or T inputs should occur only when the clock input is high. Pin Arrangement Clear 1 CLR CK Ripple Carry 16 VCC 15 Ripple Carry Output Clock 2 A 3 A QA 14 QA B 4 B QB 13 QB C 5 C QC 12 QC D 6 D QD 11 QD Enable P 7 P T 10 Enable T GND 8 9 Load Data Inputs Outputs Load (Top view) 1 XD74LS161 DIP-16 Block Diagram Clock D Clear CK Load Enable Q Output QA Q CLR P T A D Q CK B Q CLR C D Q CK Q CLR D D Q CK Q CLR Data Inputs Output QB Output QC Output QD Ripple Carry Output 2 XD74LS161 DIP-16 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Operating temperature Topr –20 25 75 °C Clock frequency ƒclock 0 — 25 MHz Clock pulse width tw (clock) 25 — — ns Clear pulse width tw (clear) 20 — — ns 20 — — ns 20 — — ns Supply voltage Output current A, B, C, D Setup time Enable P, T tsu Load Hold time th 20 — — ns 3 — — ns Typical Clear, Preset, and Inhibit Sequence Clear Load A Data Inputs B C D Clock Enable P Enable T QA QB Outputs QC QD Carry 12 Clear 13 14 Preset (Load) 3 15 0 Count 1 2 Inhibit XD74LS161 DIP-16 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — — — — — — — — — — –20 — — — — — — — — — — 0.4 0.5 20 40 20 –0.4 –0.8 –0.4 0.1 0.2 0.1 –100 31 32 –1.5 Output voltage VOL Data, Enable P Load, Clock, Enable T Clear Data, Enable P Input Load, Clock, Enable T current Clear Data, Enable P Load, Clock, Enable T Clear Short-circuit output current Supply current** IIH IIL II IOS ICCH ICCL VIK — — — — 18 19 — V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, IOL = 8 mA VIL = 0.8 V µA VCC = 5.25 V, VI = 2.7 V mA VCC = 5.25 V, VI = 0.4 V mA VCC = 5.25 V, VI = 7 V mA mA mA V VCC = 5.25 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Input clamp voltage Notes: * VCC = 5 V, Ta = 25°C ** ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open. ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Inputs Clock Outputs QA to QD Clock Ripple Carry Clock (Load = “H”) QA to QD Clock (Load = “L”) QA to QD Enable T Ripple Carry Clear QA to QD 4 min. 25 — — — — — — — — — typ. 32 20 18 13 18 13 18 9 9 20 max. — 35 35 24 27 24 27 14 14 28 Unit MHz ns ns ns ns ns ns ns ns ns Condition CL = 15 pF, RL = 2 kΩ XD74LS161 DIP-16 Timing Method tw (CK) 3V Clock 1.3V 1.3V 1.3V 0V tsu th 3V Load 1.3V 1.3V tsu Data Outputs A to D 0V th 3V 1.3V 1.3V 0V tsu Enable P or T 1.3V th 1.3V 0V Testing Method Test Circuit VCC QA 4.5V Load CK Input See Testing Table P.G. Zout = 50Ω Load circuit 1 QA A B QB C QB D QC P QC QD QD T CLR Notes: RL CL Input P.G. Zout = 50Ω 3V 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). 5 Ripple Carry Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Ripple Carry Same as Load Circuit 1. XD74LS161 DIP-16 Testing Table Item From input to output ƒmax tPLH tPHL CK Ripply → Carry CK → Q CK → Q Enable → T CLR → Q Ripple Carry Inputs Clear Load 4.5V 4.5V Enable P T 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V GND 4.5V IN Clock Data IN A GND B GND C GND D GND 4.5V IN GND GND GND GND 4.5V GND 4.5V GND IN IN GND IN* GND IN* GND IN* GND IN* GND 4.5V IN IN* 4.5V 4.5V 4.5V 4.5V GND GND GND IN* 4.5V 4.5V 4.5V 4.5V Notes: *. For initialized Item From input to output ƒmax tPLH tPHL CK→Ripple Carry CK→Q CK→Q Enable T→Ripple Carry CLR→Q Outputs QA QB QC QD Ripple Carry OUT — OUT OUT — OUT OUT — OUT OUT — OUT OUT — OUT OUT — OUT OUT — OUT OUT — OUT OUT OUT — — OUT — 6 XD74LS161 DIP-16 Waveforms 1 ƒmax, tPLH, tPHL, (Clock→Q, Ripple Carry) tTLH Clock 10% tPLH QA tTHL 3V 90% 90% 1.3V 1.3V 10% (Measure at tn + 1) 1.3V tw (CK) 1.3V 0V tPHL (Measure at tn + 2) VOH 1.3V 1.3V tPHL tPLH (Measure at tn + 2) (Measure at tn + 4) QB 1.3V VOL VOH 1.3V VOL tPHL tPLH (Measure at tn + 4) (Measure at tn + 8) QC 1.3V VOH 1.3V VOL tPHL (Measure at tn + 16) QD tPLH (Measure at tn + 8) 1.3V VOH 1.3V VOL tPLH (Measure at tn + 15) Ripple Carry tPHL (Measure at tn + 16) VOH 1.3V 1.3V VOL Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50% and : ƒmax tTLH = tTHL ≤ 2.5 ns. tn is reference bit time when all outputs are low. 7 XD74LS161 DIP-16 Waveforms 2 tPLH, tPHL, (Clock→Q) tTLH tTHL 90% Clock 3V 90% 1.3V 10% tTLH 1.3V 10% 0V tTHL 90% Data Inputs A, B, C or D 3V 90% 10% 10% 0V tPLH tPHL VOH Outputs QA, QB, QC or QD 1.3V 1.3V VOL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, Clock input: PRR = 1 MHz, duty cycle 50%, Data input: PRR = 500 kHz, duty cycle 50% Waveforms 3 tPLH, tPHL, (Enable T→Ripple Carry) tTLH tTHL 90 % 1.3 V Enable T 3V 90 % 1.3 V 10 % 10 % tPLH 0V tPHL VOH Carry Output Note: 1.3 V 1.3 V VOH Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz Waveforms 4 tPHL, (Clear→Q) Clear tTHL tTLH 90% 1.3V 90% 1.3V 10% 10% tw (CLR) ≥ 20ns 3V 0V VOH QA to QD 1.3V VOL tPHL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns 8 XD74LS161 DIP-16 DIP 89