XD3140 DIP8 / XL3140 SOP8
4.5MHz, BiMOS Operational Amplifier with
MOSFET Input/Bipolar Output
Features
• MOSFET Input Stage
- Very High Input Impedance (ZIN) -1.5TΩ (Typ)
- Very Low Input Current (Il) -10pA (Typ) at ±15V
- Wide Common Mode Input Voltage Range (VlCR) - Can be
Swung 0.5V Below Negative Supply Voltage Rail
- Output Swing Complements Input Common Mode
Range
The 3140 are integrated circuit operational
amplifiers that combine the advantages of high voltage
PMOS transistors with high voltage bipolar transistors on a
single monolithic chip.
The 3140 BiMOS operational amplifiers
feature gate protected MOSFET (PMOS) transistors in the
input circuit to provide very high input impedance, very low
input current, and high speed performance. The 3140
operate at supply voltage from 4V to 36V
(either single or dual supply). These operational amplifiers
are internally phase compensated to achieve stable
operation in unity gain follower operation, and additionally,
have access terminal for a supplementary external capacitor
if additional frequency roll-off is desired. Terminals are also
provided for use in applications requiring input offset voltage
nulling. The use of PMOS field effect transistors in the input
stage results in common mode input voltage capability down
to 0.5V below the negative supply terminal, an important
attribute for single supply applications. The output stage
uses bipolar transistors and includes built-in protection
against damage from load terminal short circuiting to either
supply rail or to ground.
• Directly Replaces Industry Type 741 in Most Applications
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ground-Referenced Single Supply Amplifiers in
Automobile and Portable Instrumentation
• Sample and Hold Amplifiers
• Long Duration Timers/Multivibrators
(µseconds-Minutes-Hours)
• Photocurrent Instrumentation
• Peak Detectors
• Active Filters
• Comparators
• Interface in 5V TTL Systems and Other Low
Supply Voltage Systems
The 3140 are intended for operation at supply
voltages up to 36V (±18V).
• All Standard Operational Amplifier Applications
• Function Generators
• Tone Controls
3140 DIP/SOP
TOP VIEW
• Power Supplies
• Portable Instruments
OFFSET
NULL
1
8
STROBE
INV. INPUT
2
7
V+
6
OUTPUT
5
OFFSET
NULL
• Intrusion Alarm Systems
NON-INV.
INPUT
3
V-
4
+
1
XD3140 DIP8 / XL3140 SOP8
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) To (V- -0.5V)
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration∞ (Note 2) . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . .
115
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
165
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications
VSUPPLY = ±15V, TA = 25oC
TYPICAL VALUES
PARAMETER
SYMBOL
Input Offset Voltage Adjustment Resistor
TEST CONDITIONS
UNITS
3140
Typical Value of Resistor
Between Terminals 4 and 5 or 4 and 1 to
Adjust Max VIO
4.7
18
kΩ
Input Resistance
RI
1.5
1.5
TΩ
Input Capacitance
CI
4
4
pF
Output Resistance
RO
60
60
Ω
Equivalent Wideband Input Noise Voltage
(See Figure 27)
eN
BW = 140kHz, RS = 1MΩ
48
48
µV
Equivalent Input Noise Voltage (See Figure 35)
eN
RS = 100Ω
f = 1kHz
40
40
nV/√Hz
f = 10kHz
12
12
nV/√Hz
IOM+
Source
40
40
mA
IOM-
Sink
18
18
mA
Short Circuit Current to Opposite Supply
Gain-Bandwidth Product, (See Figures 6, 30)
fT
4.5
4.5
MHz
Slew Rate, (See Figure 31)
SR
9
9
V/µs
220
220
µA
Rise Time
0.08
0.08
µs
Overshoot
10
10
%
To 1mV
4.5
4.5
µs
To 10mV
1.4
1.4
µs
Sink Current From Terminal 8 To Terminal 4 to
Swing Output Low
Transient Response (See Figure 28)
tr
OS
Settling Time at 10VP-P, (See Figure 5)
Electrical Specifications
tS
RL = 2kΩ
CL = 100pF
RL = 2kΩ
CL = 100pF
Voltage Follower
For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified
3140
PARAMETER
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Offset Voltage
|VIO|
-
5
15
-
2
5
mV
Input Offset Current
|IIO|
-
0.5
30
-
0.5
20
pA
II
-
10
50
-
10
40
pA
Input Current
2
XD3140 DIP8 / XL3140 SOP8
For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified (Continued)
Electrical Specifications
3140
PARAMETER
Large Signal Voltage Gain (Note 3)
(See Figures 6, 29)
Common Mode Rejection Ratio
(See Figure 34)
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
AOL
20
100
-
20
100
-
kV/V
86
100
-
86
100
-
dB
-
32
320
-
32
320
µV/V
70
90
-
70
90
-
dB
CMRR
Common Mode Input Voltage Range (See Figure 8)
VICR
-15
-15.5 to +12.5
11
-15
-15.5 to +12.5
12
V
Power-Supply Rejection Ratio,
∆VIO/∆VS (See Figure 36)
PSRR
-
100
150
-
100
150
µV/V
76
80
-
76
80
-
dB
Max Output Voltage (Note 4)
(See Figures 2, 8)
VOM+
+12
13
-
+12
13
-
V
VOM-
-14
-14.4
-
-14
-14.4
-
V
Supply Current (See Figure 32)
I+
-
4
6
-
4
6
mA
Device Dissipation
PD
-
120
180
-
120
180
mW
∆VIO/∆T
-
8
-
-
6
-
µV/oC
Input Offset Voltage Temperature Drift
NOTES:
3. At VO = 26VP-P , +12V, -14V and RL = 2kΩ.
4. At RL = 2kΩ.
Electrical Specifications
For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC
TYPICAL VALUES
PARAMETER
3140
SYMBOL
UNITS
Input Offset Voltage
|VIO|
5
2
mV
Input Offset Current
|IIO|
0.1
0.1
pA
Input Current
II
2
2
pA
Input Resistance
RI
1
1
TΩ
AOL
100
100
kV/V
100
100
dB
32
32
µV/V
90
90
dB
-0.5
-0.5
V
2.6
2.6
V
PSRR
∆VIO/∆VS
100
100
µV/V
80
80
dB
VOM+
3
3
V
Large Signal Voltage Gain (See Figures 6, 29)
Common Mode Rejection Ratio
CMRR
Common Mode Input Voltage Range (See Figure 8)
VICR
Power Supply Rejection Ratio
Maximum Output Voltage (See Figures 2, 8)
VOM-
0.13
0.13
V
Source
IOM+
10
10
mA
Sink
I
OM-
1
1
mA
Slew Rate (See Figure 31)
SR
7
7
V/µs
Gain-Bandwidth Product (See Figure 30)
fT
3.7
3.7
MHz
Supply Current (See Figure 32)
I+
1.6
1.6
mA
Device Dissipation
PD
8
8
mW
200
200
µA
Maximum Output Current:
Sink Current from Terminal 8 to Terminal 4 to Swing Output Low
3
XD3140 DIP8 / XL3140 SOP8
Block Diagram
2mA
4mA
7 V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
200µA
+
1.6mA
3
-
2µA
A≈
10,000
A ≈ 10
INPUT
200µA
2mA
A≈1
6 OUTPUT
2
C1
12pF
5
1
OFFSET
NULL
4 VSTROBE
8
Schematic Diagram
BIAS CIRCUIT
INPUT STAGE
SECOND STAGE
OUTPUT STAGE
DYNAMIC CURRENT SINK
7 V+
D1
D7
Q1
Q3
Q2
D8
R10
1K
Q4
Q5
Q6
Q20
R9
50Ω
Q19 R11
20Ω
Q7
R12
12K
R14
20K
Q21
Q17
R1
8K
R13
5K
R8
Q8
1K Q
18
6 OUTPUT
D2
D3
D4
D5
INVERTING
INPUT
2
NON-INVERTING
INPUT
3
-
Q9
+
Q10
C1
R2
500Ω
R3
500Ω
12pF
Q14
Q11
R4
500Ω
Q12
R5
500Ω
5
NOTE:
Q16
D6
R6
50Ω
1
OFFSET NULL
Q15
Q13
R7
30Ω
8
4
STROBE
V-
All resistance values are in ohms.
4
XD3140 DIP8 / XL3140 SOP8
Output Circuit Considerations
level shifting circuitry usually associated with the 741 series
of operational amplifiers.
Excellent interfacing with TTL circuitry is easily achieved with
a single 6.2V zener diode connected to Terminal 8 as shown
in Figure 1. This connection assures that the maximum
output signal swing will not go more positive than the zener
voltage minus two base-to-emitter voltage drops within the
3140 . These voltages are independent of the operating
supply voltage.
Figure 4 shows some typical configurations. Note that a
series resistor, RL, is used in both cases to limit the drive
available to the driven device. Moreover, it is recommended
that a series diode and shunt diode be used at the thyristor
input to prevent large negative transient surges that can
appear at the gate of thyristors, from damaging the
integrated circuit.
V+
5V TO 36V
8
2
Offset Voltage Nulling
LOGIC
SUPPLY
5V
7
6.2V
6
3140
TYPICAL
TTL GATE
≈ 5V
3
The input offset voltage can be nulled by connecting a 10kΩ
potentiometer between Terminals 1 and 5 and returning its
wiper arm to terminal 4, see Figure 3A. This technique,
however, gives more adjustment range than required and
therefore, a considerable portion of the potentiometer
rotation is not fully utilized. Typical values of series resistors
(R) that may be placed at either end of the potentiometer,
see Figure 3B, to optimize its utilization range are given in
the Electrical Specifications table.
4
OUTPUT STAGE TRANSISTOR (Q15, Q16)
SATURATION VOLTAGE (mV)
FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO
TERMINALS 8 AND 4 TO LIMIT 3140 OUTPUT
SWING TO TTL LEVELS
1000
100
An alternate system is shown in Figure 3C. This circuit uses
only one additional resistor of approximately the value
shown in the table. For potentiometers, in which the
resistance does not drop to 0Ω at either end of rotation, a
value of resistance 10% lower than the values shown in the
table should be used.
SUPPLY VOLTAGE (V-) = 0V
TA = 25oC
SUPPLY VOLTAGE (V+) = +5V
+15V
+30V
Low Voltage Operation
Operation at total supply voltages as low as 4V is possible
with the 3140. A current regulator based upon the PMOS
threshold voltage maintains reasonable constant operating
current and hence consistent performance down to these
lower voltages.
10
1
0.01
0.1
1.0
LOAD (SINKING) CURRENT (mA)
10
The low voltage limitation occurs when the upper extreme of the
input common mode voltage range extends down to the voltage
at Terminal 4. This limit is reached at a total supply voltage just
below 4V. The output voltage range also begins to extend down
to the negative supply rail, but is slightly higher than that of the
input. Figure 8 shows these characteristics and shows that with
2V dual supplies, the lower extreme of the input common mode
voltage range is below ground potential.
FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15
AND Q16) vs LOAD CURRENT
Figure 2 shows output current sinking capabilities of the
3140 at various supply volt ages. Output voltage swing to
the negative supply rail permits this device to operate both
power transistors and thyristors directly without the need for
V+
V+
2
2
V+
7
2
7
6
3140
3140
4
4
3
5
5
R
1
4
5
1
R
1
10kΩ
10kΩ
6
3140
6
3
3
7
10kΩ
R
V-
FIGURE 3A. BASIC
V-
V-
FIGURE 3B. IMPROVED RESOLUTION
FIGURE 3C. SIMPLER IMPROVED RESOLUTION
FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS
5
XD3140 DIP8 / XL3140 SOP8
RS
V+
LOAD
30V
NO LOAD
2
MT2
7
120VAC
+HV
7
LOAD
6
3140
RL
2
3
4
6
3140
MT1
RL
3
4
FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE 3140 SERIES
FOLLOWER
+15V
7
0.1µF
3
SIMULATED
LOAD
10kΩ
6
3140
2kΩ
100pF
2
4
0.1µF
-15V
2kΩ
LOAD RESISTANCE (RL) = 2kΩ
LOAD CAPACITANCE (CL) = 100pF
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
0.05µF
10
1mV
1mV
INVERTING
5kΩ
8
INPUT VOLTAGE (V)
6
10mV
10mV
+15V
4
7
2
0
-10
0.1
6
3140
200Ω
-4
100pF
3
-6
1mV
10mV
2kΩ
4
1mV
0.1µF
4.99kΩ
10mV
1.0
SETTLING TIME (µs)
SIMULATED
LOAD
5kΩ
INVERTING
-2
-8
0.1µF
2
FOLLOWER
5.11kΩ
-15V
SETTLING POINT
10
D1
D2
1N914
FIGURE 5A. WAVEFORM
1N914
FIGURE 5B. TEST CIRCUITS
FIGURE 5. SETTLING TIME vs INPUT VOLTAGE
Bandwidth and Slew Rate
The exceptionally fast settling time characteristics are largely
due to the high combination of high gain and wide bandwidth
of the 3140; as shown in Figure 6.
For those cases where bandwidth reduction is desired, for
example, broadband noise reduction, an external capacitor
connected between Terminals 1 and 8 can reduce the open
loop -3dB bandwidth. The slew rate will, however, also be
proportionally reduced by using this additional capacitor.
Thus, a 20% reduction in bandwidth by this technique will
also reduce the slew rate by about 20%.
Input Circuit Considerations
As mentioned previously, the amplifier inputs can be driven
below the Terminal 4 potential, but a series current limiting
resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input
protection circuitry.
Figure 5 shows the typical settling time required to reach
1mV or 10mV of the final value for various levels of large
signal inputs for the voltage follower and inverting unity gain
amplifiers.
Moreover, some current limiting resistance should be
provided between the inverting input and the output when
6
XD3140 DIP8 / XL3140 SOP8
the 3140 is used as a unity gain voltage follower. This
resistance prevents the possibility of extremely large input
signal transients from forcing a signal through the input
protection network and directly driving the internal constant
current source which could result in positive feedback via the
output terminal. A 3.9kΩ resistor is sufficient.
input offset voltage) due to the application of large
differential input voltages that are sustained over long
periods at elevated temperatures.
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts of
the opposite polarity reverse the offset. Figure 9 shows the
typical offset voltage change as a function of various stress
voltages at the maximum rating of 125oC (for metal can); at
lower temperatures (metal can and plastic), for example, at
85oC, this change in voltage is considerably less. In typical
linear applications, where the differential voltage is small and
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
amplifier employing a bipolar transistor input stage.
The typical input current is on the order of 10pA when the
inputs are centered at nominal device dissipation. As the
output supplies load current, device dissipation will increase,
raising the chip temperature and resulting in increased input
current. Figure 7 shows typical input terminal current versus
ambient temperature for the 3140.
100
φOL
RL = 2kΩ,
CL = 0pF
-90
-105
-120
-135
80
-150
10K
INPUT CURRENT (pA)
-75
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
OPEN LOOP PHASE
(DEGREES)
OPEN LOOP VOLTAGE GAIN (dB)
It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in
60
RL = 2kΩ,
CL = 100pF
40
SUPPLY VOLTAGE: VS = ±15V
1K
100
10
20
0
101
102
103
104
105
106
FREQUENCY (Hz)
107
1
-60
108
RL = ∞
0
+VICR AT TA = 125oC
+VICR AT TA = 25oC
+VICR AT TA = -55oC
-0.5
-1.0
+VOUT AT TA = 125oC
+VOUT AT TA = 25oC
+VOUT AT TA = -55oC
-1.5
-2.0
-2.5
-3.0
0
5
10
15
SUPPLY VOLTAGE (V+, V-)
20
-20
0
20
40
60
80
TEMPERATURE (oC)
100
120
140
FIGURE 7. INPUT CURRENT vs TEMPERATURE
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM TERMINAL 4 (V-)
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM TERMINAL 7 (V+)
FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs
FREQUENCY
-40
25
1.5
-VICR AT TA = 125oC
1.0
-VICR AT TA = 25oC
0.5
0
-0.5
-1.0
-1.5
0
FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON
MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
7
-VICR AT TA = -55oC
-VOUT FOR
TA = -55oC to 125oC
5
10
15
SUPPLY VOLTAGE (V+, V-)
FIGURE 9.
20
25
XD3140 DIP8 / XL3140 SOP8
CENTERING
-15V 10kΩ
7.5kΩ
+15V
360Ω
3
7
+
15kΩ
-
2
4
5
2MΩ
51
pF
7-60
pF
-15V
+15V
39kΩ
120Ω
-15V
6
-
2
FREQUENCY
ADJUSTMENT
10kΩ
5.1kΩ
EXTERNAL
OUTPUT
7
-
6
3080
+
3
2.7kΩ
4
0.1
µF
-15V
2kΩ
10kΩ
62kΩ
2
11kΩ
11kΩ
10kΩ
4
HIGH
FREQ.
SHAPE
+15V
5
+
3140
3
100kΩ
FROM BUFFER METER
DRIVER (OPTIONAL)
0.1
µF
7
6
3080
360Ω
SYMMETRY
-15V
+15V
HIGH
FREQUENCY
LEVEL
910kΩ
7-60pF
EXTERNAL
OUTPUT
-15V
13kΩ
TO OUTPUT
AMPLIFIER
TO
SINE WAVE
SHAPER
1N914
OUTPUT
AMPLIFIER
+15V
THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT USED
FIGURE 10A. CIRCUIT
FREQUENCY
ADJUSTMENT
Top Trace: Output at junction of 2.7Ω and 51Ω resistors;
5V/Div., 500ms/Div.
Center Trace: External output of triangular function generator;
2V/Div., 500ms/Div.
+15V
METER DRIVER
AND BUFFER
AMPLIFIER
Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div.
FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING
POWER
SUPPLY ±15V
M
-15V
FUNCTION
GENERATOR
WIDEBAND
LINE DRIVER
SINE WAVE
SHAPER
51Ω
SWEEP
GENERATOR
FINE
RATE
GATE DC LEVEL
SWEEP ADJUST
OFF INT.
COARSE
RATE
1V/Div., 1s/Div.
V-
EXT.
EXTERNAL
INPUT
SWEEP
LENGTH
Three tone test signals, highest frequency ≥0.5MHz. Note the slight
asymmetry at the three second/cycle signal. This asymmetry is due to
slightly different positive and negative integration from the 3080
and from the PC board and component leakages at the 100pA level.
V-
FIGURE 10C. FUNCTION GENERATOR WITH FIXED
FREQUENCIES
FIGURE 10D. INTERCONNECTIONS
FIGURE 10. FUNCTION GENERATOR
8
XD3140 DIP8 / XL3140 SOP8
500kΩ
FREQUENCY
ADJUSTMENT
10kΩ
FREQUENCY
CALIBRATION
MAXIMUM
620kΩ
7
51kΩ
3
+
6
3140
SWEEP IN
3MΩ
-
2
0.1µF
3
4
4.7kΩ
5.1kΩ
5
4
+15V
2kΩ
12kΩ
FREQUENCY 2.4kΩ
CALIBRATION
MINIMUM
2.5
kΩ
510Ω
6
5
9
3.6kΩ 13
8
D6
D3
12
METER
POSITION
ADJUSTMENT
D4
9.1kΩ
R1
10kΩ
14
2kΩ
6
7
EXTERNAL
OUTPUT
D1
-15V
2
D2
1
3
4
D5
3019
DIODE ARRAY
3/ OF 3086
5
-15V
FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER
FIGURE 12. SINE WAVE SHAPER
750kΩ
“LOG”
SAWTOOTH 18MΩ
1N914
100kΩ
100kΩ FINE
RATE
1MΩ
22MΩ
SAWTOOTH
SYMMETRY
1N914
0.47µF
0.047µF
8.2kΩ
+15V SAWTOOTH AND
RAMP LOW LEVEL
SET (-14.5V)
COARSE
RATE
4700pF
50kΩ
75kΩ
470pF
2
-
3
+
7
+15V
0.1
µF
“LOG”+15V
4
50kΩ
LOG
RATE
ADJUST
-15V
43kΩ
10kΩ
10kΩ
7
-
3
6
3140
100kΩ
TO OUTPUT 2
AMPLIFIER
30kΩ
0.1
µF
+15V
36kΩ
TRIANGLE
6
3140
51kΩ
SAWTOOTH
+
10kΩ
4
-15V
EXTERNAL OUTPUT
TO FUNCTION GENERATOR “SWEEP IN”
SWEEP WIDTH
-15V
3
6
3140
2
LOGVIO
+15V
7
+
5
1
51kΩ
4
6.8kΩ
91kΩ
10kΩ
TRIANGLE
25kΩ
3.9Ω
-15V
5
1
4
TRANSISTORS
FROM CA3086
ARRAY
2
100Ω
390Ω
3
FIGURE 13. SWEEPING GENERATOR
9
TO
WIDEBAND
OUTPUT
AMPLIFIER
10kΩ
1MΩ
100
kΩ
10
SUBSTRATE
OF CA3019
7
-15V
R3 10kΩ
+15V
9
8
4
0.1µF
1kΩ
200µA
M METER
510Ω
6
-
620Ω
11
5.6kΩ
7.5kΩ
7
+
3140
2
METER
SENSITIVITY
ADJUSTMENT
0.1µF
-15V
+15V
TO CA3080A
OF FUNCTION 3080
GENERATOR
(FIGURE 10)
SAWTOOTH
“LOG”
GATE
PULSE
OUTPUT
430Ω
R2
1kΩ
XD3140 DIP8 / XL3140 SOP8
This circuit can be adjusted most easily with a distortion
analyzer, but a good first approximation can be made by
comparing the output signal with that of a sine wave
generator. The initial slope is adjusted with the potentiometer
R1, followed by an adjustment of R2. The final slope is
established by adjusting R3, thereby adding additional
segments that are contributed by these diodes. Because
there is some interaction among these controls, repetition of
the adjustment procedure may be necessary.
REFERENCE
VOLTAGE
VOLTAGE
ADJUSTMENT
3
+
7
6
3140
INPUT
2
REGULATED
OUTPUT
4
Sweeping Generator
FIGURE 15. BASIC SINGLE SUPPLY VOLTAGE REGULATOR
SHOWING VOLTAGE FOLLOWER CONFIGURATION
Figure 13 shows a sweeping generator. Three 3140 are
used in this circuit. One 3140 is used as an integrator, a
second device is used as a hysteresis switch that determines
the starting and stopping points of the sweep. A third
3140 is used as a logarithmic shaping network for the log
function. Rates and slopes, as well as sawtooth, triangle,
and logarithmic sweeps are generated by this circuit.
Essentially, the regulators, shown in Figures 16 and 17, are
connected as non inverting power operational amplifiers with a
gain of 3.2. An 8V reference input yields a maximum output
voltage slightly greater than 25V. As a voltage follower, when
the reference input goes to 0V the output will be 0V. Because
the offset voltage is also multiplied by the 3.2 gain factor, a
potentiometer is needed to null the offset voltage.
Wideband Output Amplifier
Figure 14 shows a high slew rate, wideband amplifier
suitable for use as a 50Ω transmission line driver. This
circuit, when used in conjunction with the function generator
and sine wave shaper circuits shown in Figures 10 and 12
provides 18VP-P output open circuited, or 9VP-P output
when terminated in 50Ω. The slew rate required of this
amplifier is 28V/µs (18VP-P x π x 0.5MHz).
Series pass transistors with high ICBO levels will also
prevent the output voltage from reaching zero because there
is a finite voltage drop (VCESAT) across the output of the
3140 (see Figure 2). This saturation voltage level may
indeed set the lowest voltage obtainable.
The high impedance presented by Terminal 8 is
advantageous in effecting current limiting. Thus, only a small
signal transistor is required for the current-limit sensing
amplifier. Resistive decoupling is provided for this transistor
to minimize damage to it or the 3140 in the event of
unusual input or output transients on the supply rail.
+15V
+
SIGNAL
LEVEL
ADJUSTMENT
2.5kΩ
3
7
+
2
-
4
+
+15V
3kΩ
-15V
200Ω
2.4pF
2pF
1.8kΩ
2N3053
1N914
2.7Ω
1N914
2.7Ω
51Ω
OUT
2W
Figures 16 and 17, show circuits in which a D2201 high speed
diode is used for the current sensor. This diode was chosen
for its slightly higher forward voltage drop characteristic, thus
giving greater sensitivity. It must be emphasized that heat
sinking of this diode is essential to minimize variation of the
current trip point due to internal heating of the diode. That is,
1A at 1V forward drop represents one watt which can result in
significant regenerative changes in the current trip point as the
diode temperature rises. Placing the small signal reference
amplifier in the proximity of the current sensing diode also
helps minimize the variability in the trip level due to the
negative temperature coefficient of the diode. In spite of those
limitations, the current limiting point can easily be adjusted
over the range from 10mA to 1A with a single adjustment
potentiometer. If the temperature stability of the current
limiting system is a serious consideration, the more usual
current sampling resistor type of circuitry should be employed.
8
1
OUTPUT
DC LEVEL
ADJUSTMENT
2.2
kΩ
6
3140
200Ω
50µF
25V
50µF
25V
2.2
kΩ
2N4037
-15V
NOMINAL BANDWIDTH = 10MHz
tr = 35ns
FIGURE 14. WIDEBAND OUTPUT AMPLIFIER
Power Supplies
High input impedance, common mode capability down to the
negative supply and high output drive current capability are
key factors in the design of wide range output voltage
supplies that use a single input voltage to provide a
regulated output voltage that can be adjusted from
essentially 0V to 24V.
A power Darlington transistor (in a metal can with heatsink),
is used as the series pass element for the conventional
current limiting system, Figure 16, because high power
Darlington dissipation will be encountered at low output
voltage and high currents.
Unlike many regulator systems using comparators having a
bipolar transistor input stage, a high impedance reference
voltage divider from a single supply can be used in
connection with the 3140 (see Figure 15).
10
XD3140 DIP8 / XL3140 SOP8
A small heat sink VERSAWATT transistor is used as the
series pass element in the fold back current system, Figure
17, since dissipation levels will only approach 10W. In this
system, the D2201 diode is used for current sampling.
Foldback is provided by the 3kΩ and 100kΩ divider network
connected to the base of the current sensing transistor.
regulation also remains constant. Line regulation is 0.1% per
volt. Hum and noise voltage is less than 200µV as read with a
meter having a 10MHz bandwidth.
Figure 18A shows the turn ON and turn OFF characteristics
of both regulators. The slow turn on rise is due to the slow
rate of rise of the reference voltage. Figure 18B shows the
transient response of the regulator with the switching of a
20Ω load at 20V output.
Both regulators provide better than 0.02% load regulation.
Because there is constant loop gain at all voltage settings, the
+30V
3
2N6385
CURRENT
POWER DARLINGTON LIMITING
ADJUST
D2201
2
OUTPUT
0.1 ⇒ 24V
AT 1A
+30V
1kΩ 200Ω
75Ω
1kΩ
1kΩ
1
1kΩ
100Ω
8
56pF
8
2.7kΩ 10µF
1kΩ
5
-
2.2kΩ
+
2.7kΩ 10µF
4
-
10 11
1 2
9
3
8 7
5
6
4
5µF 50kΩ
14
180kΩ
1kΩ
3140
6
82kΩ
5
-
1
100kΩ
82kΩ
3
4
INPUT
INPUT
+
56pF
2
3
1
100kΩ
1kΩ
7
180kΩ
2
3140
3kΩ
2N2102
3
1kΩ
7
+
100kΩ
100kΩ
2N2102
1
1
2
3kΩ
6
OUTPUT ⇒ 0V TO 25V
25V AT 1A
“FOLDS BACK”
TO 40mA
“FOLDBACK” CURRENT
LIMITER
2N5294
D2201
2
3
VOLTAGE
ADJUST
100kΩ
+
-
+
2.2kΩ
250µF
12
0.01µF
-
10 11
1 2
9
3
8 7
5
6
4
5µF 50kΩ
14
VOLTAGE
ADJUST
100kΩ
+
-
250µF
12
0.01µF
13
13
3086
3086
1kΩ
1kΩ
62kΩ
62kΩ
HUM AND NOISE OUTPUT
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