XD4538

XD4538 DIP16 Block Diagram General Description The XD4538 is a dual, precision monostable multivibrator with independent trigger and reset controls. The device is retriggerable and resettable, and the control inputs are internally latched. Two trigger inputs are provided to allow either rising or falling edge triggering. The reset inputs are active LOW and prevent triggering while active. Precise control of output pulse-width has been achieved using linear CMOS techniques. The pulse duration and accuracy are determined by external components RX and CX. The device does not allow the timing capacitor to discharge through the timing pin on power-down condition. For this reason, no external protection resistor is required in series with the timing pin. Input protection from static discharge is provided on all pins. Features ■ Wide supply voltage range: 3.0V to 15V ■ High noise immunity: 0.45 VCC (typ.) ■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS Connection Diagram RX and CX are External Components VDD = Pin 16 VSS = Pin 8 Logic Diagram Top View Truth Table Inputs Outputs Clear A B Q Q L X X L H X H X L X X L H L ↓ H ↑ H H = HIGH Level L = LOW Level ↑ = Transition from LOW-to-HIGH ↓ = Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant H   L H  1 XD4538 DIP16 Theory of Operation Trigger Operation with circuit operation following. before an input trigger occurs, the monostable is in the quiescent state with the Q output low, and the timing capacitor CX completely charged to VDD. When the trigger input A goes from VSS to VDD (while inputs B and CD are held to VDD) a valid trigger is recognized, which turns on comparator C1 and N-Channel transistor N1(1). At the same time the output latch is set. With transistor N1 on, the capacitor CX rapidly discharges toward VSS until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CX begins to charge through the timing resistor, RX, toward VDD. When the voltage across CX equals VREF2, comparator C2 changes state causing the output latch to reset (Q goes low) while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from VDD to VSS (while input A is at VSS and input CD is at VDD)(2). It should be noted that in the quiescent state CX is fully charged to VDD , causing the current through resistor RX to be zero. Both comparators are “off” with the total device current due only to reverse junction leakages. An added feature of the XD4538 is that the output latch is set viathe input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CX, RX, or the duty cycle of the input waveform. Retrigger Operation The XD4538 is retriggered if a valid trigger occurs (3) followed by another valid trigger(4) before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at pin 2 or 14 has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated(4), the voltage at T2 will again drop to VREF1 before progressing along the RC charging curve toward VDD. The Q output will remain high until time T, after the last valid retrigger. Reset Operation The XD4538 may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on CD sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor Q1(5). When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the CD input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the CD input, the output pulse T can be made significantly shorter than the minimum pulse width specification. 2 XD4538 DIP16 3 XD4538 DIP16 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) (Note 2) −0.5 to +18 VDC DC Supply Voltage (VDD ) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5V to VDD + 0.5 VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW −55°C to +125°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Lead Temperature (TL) Note 2: VSS = 0V unless otherwise specified. 260°C (Soldering, 10 seconds) 0 to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3 to 15 VDC Input Voltage (VIN) DC Electrical Characteristics (Note 2) Symbol IDD VOL Parameter −55°C Conditions Min VIH IOL IOH IIN Typ +125°C Max Min Max VDD = 5V VIH = VDD 20 0.005 5 150 Device Current VDD = 10V VIL = VSS 40 0.010 10 300 VDD = 15V All Outputs Open 80 0.015 20 600 LOW Level VDD = 5V |IO| < 1 µA 0.05 0 0.05 0.05 Output Voltage VDD = 10V VIH = VDD, VIL = VSS 0.05 0 0.05 0.05 0.05 0 0.05 0.05 HIGH Level VDD = 5V |IO| < 1 µA 4.95 4.95 5 Output Voltage VDD = 10V VIH = VDD, VIL = VSS 9.95 9.95 10 9.95 14.95 14.95 15 14.95 VDD = 15V VIL +25°C Min Quiescent VDD = 15V VOH Max Units µA V 4.95 V LOW Level |IO| < 1 µA Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 HIGH Level |IO| < 1 µA Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 LOW Level VDD = 5V, VO = 0.4V VIH = VDD 0.64 0.51 0.88 0.36 Output Current VDD = 10V, VO = 0.5V VIL = VSS 1.6 1.3 2.25 0.9 (Note 3) VD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 −0.6 −0.51 −0.88 −0.36 −1.6 −1.3 −2.25 −0.9 −4.2 −3.4 −8.8 −2.4 V V mA HIGH Level VDD = 5V, VO = 4.6V Output Current VDD = 10V, VO = 9.5V (Note 3) VD = 15V, VO = 13.5V Input Current, VDD = 15V, VIN = 0V or 15V ±0.02 ±10−5 ±0.05 ±0.5 µA VDD = 15V, VIN = 0V or 15V ±0.1 ±10−5 ±0.1 ±1.0 µA VIL = VSS mA Pin 2 or 14 IIN Input Current Other Inputs Note 3: IOH and IOL are tested one output at a time. 4 XD4538 DIP16 AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, and tr = tf = 20 ns unless otherwise specified Symbol tTLH, tTHL tPLH, tPHL Parameter Output Transition Time Propagation Delay Time Conditions Min Typ Max 100 200 VDD = 10V 50 100 VDD = 15V 40 80 VDD = 5V 300 600 VDD = 10V 150 300 VDD = 15V 100 220 VDD = 5V 250 500 VDD = 10V 125 250 VDD = 15V 95 190 VDD = 5V Units ns Trigger Operation— A or B to Q or Q ns Reset Operation— CD to Q or Q tWL, tWH tRR Minimum Input Pulse Width VDD = 5V 35 70 A, B, or CD VDD = 10V 30 60 VDD = 15V 25 50 Minimum Retrigger Time VDD = 5V 0 VDD = 15V PWOUT Input Capacitance Output Pulse Width (Q or Q) ns 0 VDD = 10V CIN ns 0 ns 0 Pin 2 or 14 10 Other Inputs 5 7.5 244 RX = 100 kΩ VDD = 5V 208 226 CX = 0.002 µF VDD = 10V 211 230 248 VDD = 15V 216 235 254 RX = 100 kΩ VDD = 5V 8.83 9.60 10.37 CX = 0.1 µF VDD = 10V 9.02 9.80 10.59 VDD = 15V 9.20 10.00 10.80 RX = 100 kΩ VDD = 5V 0.87 0.95 1.03 CX = 10.0 µF VDD = 10V 0.89 0.97 1.05 VDD = 15V 0.91 0.99 1.07 Pulse Width Match between RX = 100 kΩ VDD = 5V ±1 Circuits in the Same Package CX = 0.1 µF VDD = 10V ±1 VDD = 15V ±1 CX = 0.1 µF, RX = 100 kΩ pF µs ms s % Operating Conditions RX External Timing Resistance CX External Timing Capacitance 5.0 (Note 5) kΩ 0 No Limit pF Note 4: AC parameters are guaranteed by DC correlated testing. Note 5: The maximum usable resistance RX is a function of the leakage of the Capacitor CX, leakage of the XD4538, and leakage due to board layout, surface resistance, etc. 5 XD4538 DIP16 Typical Applications 6 XD4538 DIP16 Test Circuits and Waveforms Test Circuits and Waveforms (Continued) *CL = 50 pF Input Connections Characteristics tPLH, tPHL, tTLH, tTHL CD A B VDD PG1 VDD VDD VSS PG2 PG3 PG1 PG2 PWOUT, tWH, tWL tPLH, tPHL, tTLH, tTHL PWOUT, tWH, tWL tPLH(R), tPHL(R), tWH, tWL RX = RX′ = 100 kΩ CX = CX′ = 100 pF C1 = C2 = 0.1 µF Duty Cycle = 50% *Includes capacitance of probes, wiring, and fixture parasitic 7 XD4538 DIP16 7 8