XD4066

XD4066 DIP-14 1. General description TheXD4066 provides four single-pole, si ngle-throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. The XD4066 is pin compatible with the XD4016 but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range. 2. Features and benefits      Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Specified from 40 C to +85 C and 40 C to +125 C 3. Applications  Analog multiplexing and demultiplexing  Digital multiplexing and demultiplexing  Signal gating 4 Functional diagram < ( < ( < ( < ( Fig 1.   =   Q<  = Q(    = 9'' 9''    =  966 Functional diagram Fig 2. 1 Logic diagram (one switch) Q= XD4066 DIP-14 Quad single-pole single-throw analog switch 5 Pinning information Fig 3. Pin configuration Table 2. Pin description Symbol <   9'' =   ( =   ( <  (  (   = 966   < XD4066  <  = Pin Description 1Y, 2Y, 3Y, 4Y 1, 4, 8, 11 independent input or output 1Z, 2Z, 3Z, 4Z 2, 3, 9, 10 independent input or output 1E, 2E, 3E, 4E 13, 5, 6, 12 enable input (active HIGH) VSS 7 ground (0 V) VDD 14 supply voltage 2 XD4066 DIP-14 Quad single-pole single-throw analog switch 6 Functional description Table 3. Function table[1] Input nE Switch H ON L OFF [1] H = HIGH voltage level; L = LOW voltage level. 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage Conditions VI < 0.5 V or VI > VDD + 0.5 V Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V II/O input/output current - 10 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation - 500 mW - 100 mW [1] Tamb = 40 C to +125 C [2] SO14 P power dissipation per switch [1] To avoid drawing VDD current out of terminal nZ, when switch current flows into terminals nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VDD current will flow out of terminals nY, in this case there is no limit for the voltage drop across the switch, but the voltages at nY and nZ may not exceed VDD or VSS. [2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 3 XD4066 DIP-14 9 Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Min VIH VIL HIGH-level input voltage LOW-level input voltage IO < 1 A IO < 1 A II input leakage current IS(OFF) OFF-state leakage current IDD supply current all valid input combinations CI input capacitance per channel; see Figure 4 nE input Max Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 15 V - 0.1 - 0.1 - 1.0 - 1.0 A 15 V - - - 200 - - - - nA 5V - 1.0 - 1.0 - 7.5 - 7.5 A 10 V - 2.0 - 2.0 - 15.0 - 15.0 A 15 V - 4.0 - 4.0 - 30.0 - 30.0 A - - - - 7.5 - - - - pF 9'' Q( 9,/ Q= 9, Fig 4. Tamb = 85 C Tamb = 125 C Unit Q< 966 Test circuit for measuring OFF-state leakage current 4 ,6 92 XD4066 DIP-14 Quad single-pole single-throw analog switch Table 7. ON resistance Tamb = 25 C; ISW = 200 A; VSS = 0 V. Symbol Parameter Conditions VDD Typ Max Unit RON(peak) ON resistance (peak) VI = 0 V to VDD; see Figure 5 and Figure 6 5V 350 2500  10 V 80 245  15 V 60 175  5V 115 340  10 V 50 160  RON(rail) ON resistance (rail) VI = 0 V; see Figure 5 and Figure 6 VI = VDD; see Figure 5 and Figure 6 RON ON resistance mismatch between channels VI = 0 V to VDD; see Figure 5 15 V 40 115  5V 120 365  10 V 65 200  15 V 50 155  5V 25 -  10 V 10 -  15 V 5 -   521 ȍ   96:  9'' Q( 9,+ Q< 9,  Q= 966   ,6:      9,9 ISW = 200 A. RON = VSW / ISW. (1) VDD = 5 V (2) VDD = 10 V (3) VDD = 15 V Fig 5. Test circuit for measuring RON Fig 6. 5 Typical RON as a function of input voltage XD4066 DIP-14 Quad single-pole single-throw analog switch 10. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 C; VSS = 0 V; for test circuit see Figure 9. Symbol Parameter Conditions tPHL HIGH to LOW propagation delay nY, nZ to nZ, nY; see Figure 7 nY, nZ to nZ, nY; see Figure 7 tPHZ tPZH tPLZ tPZL HIGH to OFF-state propagation delay nE to nY, nZ; see Figure 8 OFF-state to HIGH propagation delay nE to nY, nZ; see Figure 8 LOW to OFF-state propagation delay nE to nY, nZ; see Figure 8 OFF-state to LOW propagation delay nE to nY, nZ; see Figure 8 VDD Typ Max Unit 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 80 160 ns 10 V 65 130 ns 15 V 60 120 ns 5V 40 80 ns 10 V 20 40 ns 15 V 15 30 ns 5V 80 160 ns 10 V 70 140 ns 15 V 70 140 ns 5V 45 90 ns 10 V 20 40 ns 15 V 15 30 ns Table 9. Dynamic power dissipation PD PD can be calculated from the formulas shown; VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (W) where: 5V PD = 2500  fi + (fo  CL)  VDD 10 V PD = 11500  fi + (fo  CL)  VDD2 fo = output frequency in MHz; 15 V PD = 29000  fi + (fo  CL)  CL = output load capacitance in pF; 2 VDD2 fi = input frequency in MHz; VDD = supply voltage in V; (CL  fo) = sum of the outputs. 6 XD4066 DIP-14 Quad single-pole single-throw analog switch 10.1 Waveforms and test circuit 9, 90 90 W3/+ W3+/ LQSXWQ