XD14538

XD14538 DIP16 The XD14538 is a dual, retriggerable, resettable monostable multivibrator. It may be triggered from either edge of an input pulse, and produces an accurate output pulse over a wide range of widths, the duration and accuracy of which are determined by the external timing components, CX and RX. Output Pulse Width T = RX @ CX (secs) RX = W CX = Farads Features • • • • • Unlimited Rise and Fall Time Allowed on the A Trigger Input Pulse Width Range = 10 ms to 10 s Latched Trigger Inputs Separate Latched Reset Inputs 3.0 Vdc to 18 Vdc Operational Limits • Triggerable from Positive (A Input) or Negative−Going Edge (B−Input) • Capable of Driving Two Low−Power TTL Loads or One Low−Power • • • • MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Parameter Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Operating Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Vin, Vout Iin, Iout DC Supply Voltage Range Value Input or Output Voltage Range (DC or Transient) Schottky TTL Load Over the Rated Temperature Range Pin−for−pin Compatible with XD14538 Use the XD14538 for Pulse Widths Less Than 10 ms with Supplies Up to 6 V NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 1 XD14538 PIN ASSIGNMENT BLOCK DIAGRAM CX VSS 1 16 VDD CX/RXA 2 15 VSS RESET A 3 14 CX/RXB AA 4 13 RESET B BA 5 12 AB QA 6 11 BB QA 7 10 QB VSS 8 9 QB 1 4 5 1 ms 10 ms 100 ms 1 ms 10 ms VDD 2 A B Q1 6 Q1 RESET 7 3 CX ONE−SHOT SELECTION GUIDE 100 ns 14528B 14536B 14538B RX 100 ms 15 1s 12 10 s 23 HR 5 MIN. 14541B 4538A* 11 RX VDD 14 A Q2 B Q2 RESET 10 9 13 RX AND CX ARE EXTERNAL COMPONENTS. VDD = PIN 16 VSS = PIN 8, PIN 1, PIN 15 *LIMITED OPERATING VOLTAGE (2 - 6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE 2 XD14538 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol VDD Vdc − 55_C 25_C 125_C Min Max Min Typ (Note 2) Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 − − − − – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 − − − − – 1.7 – 0.36 – 0.9 – 2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current, Pin 2 or 14 Iin 15 − ± 0.05 − ± 0.00001 ± 0.05 − ± 0.5 mAdc Input Current, Other Inputs Iin 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 mAdc Input Capacitance, Pin 2 or 14 Cin − − − − 25 − − − pF Input Capacitance, Other Inputs (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) Q = Low, Q = High IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc Quiescent Current, Active State (Both) (Per Package) Q = High, Q = Low IDD 5.0 10 15 − − − 2.0 2.0 2.0 − − − 0.04 0.08 0.13 0.20 0.45 0.70 − − − 2.0 2.0 2.0 mAdc IT 5.0 10 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink Total Supply Current at an external load capacitance (CL) and at external timing network (RX, CX) (Note 3) IOH Vdc Vdc mAdc IT = (3.5 x 10–2) RXCXf + 4CXf + 1 x 10–5 CLf IT = (8.0 x 10–2) RXCXf + 9CXf + 2 x 10–5 CLf IT = (1.25 x 10–1) RXCXf + 12CXf + 3 x 10–5 CLf where: IT in mA (one monostable switching only), where: CX in mF, CL in pF, RX in k ohms, and where: f in Hz is the input frequency. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 3 mAdc XD14538 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/pF) CL + 20 ns tTLH Output Fall Time tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTHL Propagation Delay Time A or B to Q or Q tPLH, tPHL = (0.90 ns/pF) CL + 255 ns tPLH, tPHL = (0.36 ns/pF) CL + 132 ns tPLH, tPHL = (0.26 ns/pF) CL + 87 ns tPLH, tPHL All Types VDD Vdc Min Typ (Note 5) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns ns 5.0 10 15 − − − 300 150 100 600 300 220 5.0 10 15 − − − 250 125 95 500 250 190 5 10 15 − − − − − − 15 5 4 ms B Input 5 10 15 − − − 300 1.2 0.4 1.0 0.1 0.05 ms A Input 5 10 15 Reset to Q or Q tPLH, tPHL = (0.90 ns/pF) CL + 205 ns tPLH, tPHL = (0.36 ns/pF) CL + 107 ns tPLH, tPHL = (0.26 ns/pF) CL + 82 ns Input Rise and Fall Times Reset Input Pulse Width A, B, or Reset ns tr, tf − No Limit tWH, tWL 5.0 10 15 170 90 80 85 45 40 − − − ns Retrigger Time trr 5.0 10 15 0 0 0 − − − − − − ns Output Pulse Width — Q or Q Refer to Figures 8 and 9 CX = 0.002 mF, RX = 100 kW T ms 5.0 10 15 198 200 202 210 212 214 230 232 234 CX = 0.1 mF, RX = 100 kW 5.0 10 15 9.3 9.4 9.5 9.86 10 10.14 10.5 10.6 10.7 ms CX = 10 mF, RX = 100 kW 5.0 10 15 0.91 0.92 0.93 0.965 0.98 0.99 1.03 1.04 1.06 s 5.0 10 15 − − − ± 1.0 ± 1.0 ± 1.0 ± 5.0 ± 5.0 ± 5.0 % Pulse Width Match between circuits in the same package. CX = 0.1 mF, RX = 100 kW 100 [(T1 – T2)/T1] 4. The formulas given are for the typical characteristics only at 25_C. 5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ OPERATING CONDITIONS External Timing Resistance RX − 5.0 − (Note 6) kW External Timing Capacitance CX − 0 − No Limit (Note 7) mF 6. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the XD14538 , and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MW.. 7. If CX > 15 mF, use discharge protection diode per Fig. 11. 4 XD14538 VDD VDD P1 RX 2 (14) CX + C1 - Vref1 1 (15) ENABLE + C2 - Vref2 ENABLE R Q OUTPUT LATCH S Q N1 A VSS 4 (12) 6(10) 7(9) CONTROL 5 (11) B RESET QR S 3 (13) NOTE: Pins 1, 8 and 15 must be externally grounded QR R RESET LATCH Figure 1. Logic Diagram (1/2 of DevIce Shown) VDD 500 pF 0.1 mF CERAMIC ID RX′ RX VSS CX ′ CX Vin VSS CX/RX A B Q RESET Q A′ Q′ B′ Q′ 20 ns CL 20 ns VDD 90% CL CL 10% Vin 0V CL RESET′ VSS Figure 2. Power Dissipation Test Circuit and Waveforms VDD INPUT CONNECTIONS RX′ RX VSS PULSE GENERATOR PULSE GENERATOR PULSE GENERATOR A Characteristics *CL = 50 pF CX ′ CX VSS CX/RX B Q RESET Q A′ Q′ B′ CL CL CL Q′ CL RESET′ VSS Reset A B tPLH, tPHL, tTLH, tTHL, T, tWH, tWL VDD PG1 VDD tPLH, tPHL, tTLH, tTHL, T, tWH, tWL VDD VSS PG2 tPLH(R), tPHL(R), tWH, tWL PG3 PG1 PG2 *Includes capacitance of probes, wiring, and fixture parasitic. NOTE: Switching test waveforms for PG1, PG2, PG3 are shown In Figure 4. Figure 3. Switching Test Circuit 5 PG1 = PG2 = PG3 = XD14538 90% 10% tTHL 50% A tTLH tWH 50% tTHL B VDD tTLH 90% 10% 50% VDD tWL tTHL RESET tPHL 90% 10% tPLH 50% tTHL tPLH T 50% Q tPHL Q 50% tTHL tPLH 90% 10% 50% trr tPHL 50% tTLH tPHL tWL tTLH 90% 10% 50% VDD 50% 50% 50% TA = 25°C RX = 100 kW CX = 0.1 mF NORMALIZED PULSE WIDTH CHANGE WITH RESPECT TO VALUE AT VDD = 10 V (%) RELATIVE FREQUENCY OF OCCURRENCE Figure 4. Switching Test Waveforms 0% POINT PULSE WIDTH VDD = 5.0 V, T = 9.8 ms VDD = 10 V, T = 10 ms VDD = 15 V, T = 10.2 ms 1.0 0.8 0.6 0.4 0.2 0 -4 -2 0 2 4 T, OUTPUT PULSE WIDTH (%) RX = 100 kW CX = 0.1 mF 2 1 0 1 2 5 Figure 5. Typical Normalized Distribution of Units for Output Pulse Width 6 7 8 9 10 11 12 VDD, SUPPLY VOLTAGE (VOLTS) FUNCTION TABLE TOTAL SUPPLY CURRENT ( μA) Inputs RX = 100 kW, CL = 50 pF ONE MONOSTABLE SWITCHING ONLY VDD = 15 V 5.0 V 10 10 V 1.0 0.1 0.001 14 Figure 6. Typical Pulse Width Variation as a Function of Supply Voltage VDD 1000 100 13 0.1 1.0 10 100 OUTPUT DUTY CYCLE (%) Figure 7. Typical Total Supply Current versus Output Duty Cycle 6 Reset A H H L H H H H H L Outputs B Q Q H L Not Triggered Not Triggered L, H, L H L, H, Not Triggered Not Triggered X X X X L H Not Triggered 15 RX = 100 kW CX = 0.1 mF VDD = 15 V 2 1 VDD = 10 V 0 VDD = 5 V -1 TYPICAL NORMALIZED ERROR WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%) TYPICAL NORMALIZED ERROR WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%) XD14538 RX = 100 kW CX = .002 mF 3.0 2.0 1.0 0 -1.0 -2 VDD = 15 V VDD = 10 V -2.0 VDD = 5.0 V -3.0 -60 -40 -20 0 20 40 60 80 100 TA, AMBIENT TEMPERATURE (°C) 120 140 -60 -40 Figure 8. Typical Error of Pulse Width Equation versus Temperature -20 0 20 40 60 80 100 TA, AMBIENT TEMPERATURE (°C) Figure 9. Typical Error of Pulse Width Equation versus Temperature THEORY OF OPERATION 1 3 4 A 2 B 5 RESET Vref2 Vref2 CX/RX Vref1 Vref2 Vref2 Vref1 Vref1 Vref1 Q T 120 140 T T 1 Positive edge trigger 4 Positive edge re−trigger (pulse lengthening) 2 Negative edge trigger 5 Positive edge re−trigger (pulse lengthening) 3 Positive edge trigger Figure 10. Timing Operation 7 XD14538 TRIGGER OPERATION on Reset sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor P1 ➄. When the voltage on the capacitor reaches Vref 2, the reset latch will clear, and will then be ready to accept another pulse. It the Reset input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Reset input, the output pulse T can be made significantly shorter than the minimum pulse width specification. The block diagram of the XD14538 is shown in Figure 1, with circuit operation following. As shown in Figure 1 and 10, before an input trigger occurs, the monostable is in the quiescent state with the Q output low, and the timing capacitor CX completely charged to VDD. When the trigger input A goes from VSS to VDD (while inputs B and Reset are held to VDD) a valid trigger is recognized, which turns on comparator C1 and N−channel transistor N1 ➀. At the same time the output latch is set. With transistor N1 on, the capacitor CX rapidly discharges toward VSS until Vref1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CX begins to charge through the timing resistor, RX, toward VDD. When the voltage across CX equals Vref 2, comparator C2 changes state, causing the output latch to reset (Q goes low) while at the same time disabling comparator C2 ➁. This ends at the timing cycle with the monostable in the quiescent state, waiting for the next trigger. In the quiescent state, CX is fully charged to VDD causing the current through resistor RX to be zero. Both comparators are “off” with total device current due only to reverse junction leakages. An added feature of the XD14538 is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CX, RX, or the duty cycle of the input waveform. POWER−DOWN CONSIDERATIONS Large capacitance values can cause problems due to the large amount of energy stored. When a system containing the XD14538 is powered down, the capacitor voltage may discharge from VDD through the standard protection diodes at pin 2 or 14. Current through the protection diodes should be limited to 10 mA and therefore the discharge time of the VDD supply must not be faster than (VDD). (C) / (10 mA). For example, if VDD = 10 V and CX = 10 mF, the VDD supply should discharge no faster than (10 V) x (10 mF) / (10 mA) = 10 ms. This is normally not a problem since power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VDD to zero volts occurs, the XD14538 can sustain damage. To avoid this possibility use an external clamping diode, DX, connected as shown in Fig. 11. Dx RETRIGGER OPERATION Cx Rx VDD VSS The XD14538 is retriggered if a valid trigger occurs ➂ followed by another valid trigger ➃ before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at pin 2 or 14 has begun to rise from Vref 1, but has not yet reached Vref 2, will cause an increase in output pulse width T. When a valid retrigger is initiated ➃, the voltage at CX/RX will again drop to Vref 1 before progressing along the RC charging curve toward VDD. The Q output will remain high until time T, after the last valid retrigger. VDD Q Q RESET Figure 11. Use of a Diode to Limit Power Down Current Surge RESET OPERATION TheXD14538 may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse 8 XD14538 TYPICAL APPLICATIONS CX RX RISING-EDGE TRIGGER CX RX VDD A Q B Q VDD RISING-EDGE A TRIGGER B Q Q B = VDD RESET = VDD CX A = VSS RESET = VDD CX RX VDD VDD Q B FALLING-EDGE TRIGGER RX Q A B Q Q FALLING-EDGE TRIGGER RESET = VDD RESET = VDD Figure 12. Retriggerable Monostables Circuitry Figure 13. Non−Retriggerable Monostables Circuitry NC A B Q NC Q NC CD VDD VDD Figure 14. Connection of Unused Sections 9 XD14538 10