XD14518

XD14518 DIP16 Dual Up Counters 14518 PIN ASSIGNMENT The XD14518 dual BCD counter counter are constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4−stage counters. The counter stages are type D flip−flops, with interchangeable Clock and Enable lines for incrementing on either the positive−going or negative−going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line.In addition, the XD14518 will count out of all undefined states withintwo clock periods. These complementary MOS up counters find primary use in multi−stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity. • • • 1 16 VDD EA 2 15 RB Q0A 3 14 Q3B Q1A 4 13 Q2B Q2A 5 12 Q1B Q3A 6 11 Q0B RA 7 10 EB VSS 8 9 CB BLOCK DIAGRAM Features • • • • CA Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Internally Synchronous for High Internal and External Speeds Logic Edge−Clocked Design — Incremented on Positive Transition of Clock or Negative Transition on Enable Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range These Devices are Pb−Free and are RoHS Compliant NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable CLOCK 1 Q0 C 2 ENABLE R Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 2.) 500 mW TA Operating Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C VDD Vin, Vout Iin, Iout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) 3 4 Q3 5 6 Q0 11 Q1 Q2 Q3 12 7 CLOCK 9 C 10 ENABLE R 13 14 15 VDD = PIN 16 VSS = PIN 8 MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol Q1 Q2 TRUTH TABLE Clock Enable Reset Action 1 0 Increment Counter 0 Increment Counter 0 No Change 0 No Change 0 X X 0 0 No Change Lead Temperature 260 °C 1 0 No Change (8−Second Soldering) X X 1 Q0 thru Q3 = 0 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended X = Don’t Care Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. TL 1 14518 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol − 55_C 25_C 125_C VDD Vdc Min Max Min Typ (3.) Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 μAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 μAdc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Source Sink Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IOH Vdc Vdc mAdc IT = (0.6 μA/kHz) f + IDD IT = (1.2 μA/kHz) f + IDD IT = (1.7 μA/kHz) f + IDD 3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in μA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. 2 μAdc 14518 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C) All Types Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q/Enable to Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns tPLH, tPHL Reset to Q tPHL = (1.7 ns/pF) CL + 265 ns tPHL = (0.66 ns/pF) CL + 117 ns tPHL = (0.66 ns/pF) CL + 95 ns tPHL VDD Min Typ (7.) Max 5.0 10 15 — — — 100 50 40 200 100 80 Unit ns ns 5.0 10 15 — — — 280 115 80 560 230 160 5.0 10 15 — — — 330 130 90 650 230 170 tw(H) tw(L) 5.0 10 15 200 100 70 100 50 35 — — — ns fcl 5.0 10 15 — — — 2.5 6.0 8.0 1.5 3.0 4.0 MHz tTHL, tTLH 5.0 10 15 — — — — — — 15 5 4 μs Enable Pulse Width tWH(E) 5.0 10 15 440 200 140 220 100 70 — — — ns Reset Pulse Width tWH(R) 5.0 10 15 280 120 90 125 55 40 — — — ns trem 5.0 10 15 –5 15 20 – 45 – 15 –5 — — — ns Clock Pulse Width Clock Pulse Frequency Clock or Enable Rise and Fall Time Reset Removal Time ns 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. VDD 500 μF PULSE GENERATOR ID 0.01 μF CERAMIC C Q0 Q1 Q2 E Q3 R CL CL CL VSS 20 ns 20 ns 50% 90% 10% VARIABLE WIDTH VSS Power Dissipation Test Circuit and Waveform 3 CL 14518 20 ns VDD PULSE GENERATOR C 20 ns 90% 50% 10% CLOCK INPUT Q0 tWH Q1 E R Q2 Q3 CL CL VSS CL 50% 10% Q tf Switching Time Test Circuit and Waveforms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 0 1 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 CLOCK ENABLE RESET 2 3 4 5 Q0 Q1 Q2 Q3 Q0 14518 tPHL 90% tr 14518 VSS tWL tPLH CL VDD Q1 Q2 Q3 Timing Diagram 4 4 14518 Q0 D C R Q1 Q D Q C R Q2 Q D Q C R Q3 Q D Q C Q R Q RESET ENABLE CLOCK Decade Counter (XD14518) Logic Diagram (1/2 of Device Shown) Q0 D C R Q1 Q D Q C R Q2 Q D Q C RESET ENABLE CLOCK Binary Counter (XD14518) Logic Diagram (1/2 of Device Shown) 5 R Q3 Q D Q C Q R Q 14518 DIP 6