XD13085 DIP8 / XL13085 SOP8
Features
The XD13085 +5.0V, ±15kV ESD-protected, RS-485/
RS-422 transceiver features one driver and one receiver.
The device includes fail-safe circuitry, guaranteeing
a logic-high receiver output when receiver inputs are
open or shorted. The receiver outputs a logic-high if all
transmitters on a terminated bus are disabled (high
impedance). The XD13085 includes a hot-swap
capability to eliminate false transitions on the bus during
power-up or hot insertion.
S +5.0V Operation
The XD13085 features reduced slew-rate drivers
that minimize EMI and reduce reflections caused by
improperly terminated cables, allowing error-free data
transmission up to 500kbps.
S Low-Current Shutdown Mode
The XD13085 is ideal for half-duplex communications
and it draws 1.2mA of supply current when unloaded
or when fully loaded with the drivers disabled. The
XD13085 has a 1/8-unit load receiver input imped ance, allowing up to 256 transceivers on the bus.
General Description
S Extended ESD Protection for RS-485/RS-422 I/O
Pins ±15kV Human Body Model
S True Fail-Safe Receiver While Maintaining
EIA/TIA-485 Compatibility
S Hot-Swap Input Structures on DE and RE
S Enhanced Slew-Rate Limiting Facilitates ErrorFree Data Transmission
S Allow Up to 256 Transceivers on the Bus
S Available in Industry-Standard 8-Pin SO and PDIP
Packages
The XD13085 is available in an 8-pin SO and PDIP
packages.
Ordering Information
Applications
Utility Meters
Lighting Systems
PART
TEMP RANGE
PIN-PACKAGE
13085
-40NC to +85NC
8 SO
Industrial Control
Telecom
Security Systems
Instrumentation
Profibus
Typical Operating Circuit
0.1µF
RO
RE
DE
DI
1
+
R
8
2
7
3
6
4
D
5
XD13085
DE
VCC
D
B
A
Rt
DI
B
Rt
A
GND
RO
R
RE
TYPICAL HALF-DUPLEX OPERATING CIRCUIT
1
XD13085 DIP8 / XL13085 SOP8
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
Supply Voltage (VCC)............................................................ +6V
Control Input Voltage (RE, DE)................................-0.3V to +6V
Driver Input Voltage (DI)..........................................-0.3V to +6V
Driver Output Voltage (A, B).....................................-8V to +13V
Receiver Input Voltage (A, B)...................................-8V to +13V
Receiver Output Voltage (RO).................. -0.3V to (VCC + 0.3V)
Driver Output Current..................................................... ±250mA
Continuous Power Dissipation (TA = +70°C)
SO (derate 5.9mW/°C above +70°C)...........................471mW
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +5.0V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V and TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
5.5
V
RL = 100I (RS-422), Figure 1
3
VCC
RL = 54I (RS-485), Figure 1
2
VCC
DRIVER
VCC Supply-Voltage Range
VCC
Differential Driver Output
VOD
Change in Magnitude of
Differential Output Voltage
Driver Common-Mode Output
Voltage
Change in Magnitude of
Common-Mode Voltage
DVOD
VOC
DVOC
VCC
RL = 100I or 54I, Figure 1 (Note 2)
0.2
V
3
V
0.2
V
RL = 100I or 54I, Figure 1 (Note 2)
VIH
DE, DI, RE
Input-Low Voltage
VIL
DE, DI, RE
Input Current
Input Impedance First Transition
at Power-Up
VHYS
DE, DI, RE
IIN1
DE, DI, RE
RPWUP
Input Impedance on First
Transition after POR Delay
Rft
Driver Short-Circuit Output
Current
IOSD
Driver Short-Circuit Foldback
Output Current
IOSDF
VCC/2
RL = 100I or 54I, Figure 1
Input-High Voltage
Input Hysteresis
3
V
0.8
100
V
mV
Q1
FA
3.65
8.8
kI
7
60
kΩ
0 P VOUT P +12V (Note 3)
40
250
-7V P VOUT P VCC (Note 3)
-250
-40
VDE, VRE = VRE = 2V
VDE = VRE = 2V
(VCC - 1V) P VOUT P +12V (Note 3)
-7V P VOUT P +1V (Note 3)
20
-20
Thermal-Shutdown Threshold
TTS
175
Thermal-Shutdown Hysteresis
TTSH
15
Input Current (A and B)
V
No load
IA, B
VDE = 0V,
VCC = 0V or VCC
VTH
-7V P VCM P +12V
VIN = +12V
VIN = -7V
mA
mA
NC
NC
125
-100
FA
RECEIVER
Receiver Differential Threshold
Voltage
Receiver Input Hysteresis
2
DVTH
VA + VB = 0V
-200
-125
15
-50
mV
mV
XD13085 DIP8 / XL13085 SOP8
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V and TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
VCC 0.6
MAX
UNITS
RO Output-High Voltage
VOH
IO = -1mA
V
RO Output-Low Voltage
VOL
IO = 1mA
0.4
V
Three-State Output Current at
Receiver
IOZR
0 P VO P VCC
P1
FA
Receiver Input Resistance
RIN
-7V P VCM P +12V
Receiver Output Short-Circuit
Current
IOSR
0V P VRO P VCC
96
kI
P 110
mA
SUPPLY CURRENT
Supply Current
Supply Current in Shutdown
Mode
ICC
ISHDN
No load, VRE = 0V, DE = VCC
1.2
1.8
No load, RE = VCC, DE = VCC
No load, VRE = 0V, VDE = 0V
1.2
1.8
1.2
1.8
RE = VCC, VDE = 0V
2.8
10
Human Body Model
Q15
Contact Discharge
IEC 61000-4-2, level 4
Q8
Air-Gap Discharge
IEC 61000-4-2
Q15
mA
FA
ESD PROTECTION
ESD Protection for A and B
kV
DRIVER SWITCHING CHARACTERISTICS WITH INTERNAL SRL (500kbps)
(VCC = +5.0V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V and TA = +25NC.) (Note 1)
PARAMETER
Driver Propagation Delay
Driver Differential Output Rise or
Fall Time
Differential Driver Output Skew
|tDPLH - tDPHL|
SYMBOL
tDPLH
tDPHL
CONDITIONS
CL = 50pF, RL = 54I, Figures 2 and 3
t R , tF
CL = 50pF, RL = 54I, Figures 2 and 3
tDSKEW
CL = 50pF, RL = 54I, Figures 2 and 3
Maximum Data Rate
MIN
TYP
MAX
UNITS
200
1000
200
1000
250
900
ns
140
ns
500
ns
kbps
Driver Enable to Output High
tDZH
Figure 4
2500
ns
Driver Enable to Output Low
tDZL
Figure 5
2500
ns
Driver Disable Time from Low
tDLZ
Figure 5
100
ns
Driver Disable Time from High
tDHZ
Figure 4
100
ns
Driver Enable from Shutdown to
Output High
tDZH(SHDN) Figure 4
5500
ns
Driver Enable from Shutdown to
Output Low
tDZL(SHDN) Figure 5
5500
ns
700
ns
Time to Shutdown
tSHDN
50
340
3
XD13085 DIP8 / XL13085 SOP8
RECEIVER SWITCHING CHARACTERISTICS WITH INTERNAL SRL (500kbps)
(VCC = +5.0V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V and TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
tRPLH
Receiver Propagation Delay
tRPHL
Receiver Output Skew
|tRPLH - tRPHL|
tRSKEW
CONDITIONS
MIN
TYP
MAX
UNITS
200
CL = 15pF, Figures 6 and 7
ns
200
CL = 15pF, Figures 6 and 7
30
Maximum Data Rate
500
ns
kbps
Receiver Enable to Output Low
tRZL
Figure 8
50
ns
Receiver Enable to Output High
tRZH
Figure 8
50
ns
Receiver Disable Time from Low
tRLZ
Figure 8
50
ns
Receiver Disable Time from High
tRHZ
Figure 8
50
ns
Receiver Enable from Shutdown
to Output High
tRZH(SHDN) Figure 8
5500
ns
Receiver Enable from Shutdown
to Output Low
tRZL(SHDN) Figure 8
5500
ns
700
ns
Time to Shutdown
tSHDN
50
340
Note 1: All currents into the device are positive. All currents out of the device are negative. All voltages are referred to device
ground, unless otherwise noted.
Note 2: ΔVOD and ΔVOC are the changes in VOD and VOC, respectively, when the DI input changes state.
Note 3: The short-circuit output current applies to peak current just prior to foldback current limiting. The short-circuit foldback
output current applies during current limiting to allow a recovery from bus contention.
Test Circuits and Waveforms
B
VCC
DI
RL/2
0
VCC/2
tDPLH
VOD
RL/2
Y
VO
1/2 VO
VO
VDIFF 0
-VO
Figure 1. Driver DC Test Load
VCC
10%
VDIFF = V (B) - V (A)
90%
tSKEW = | tDPLH - tDPHL |
Figure 3. Driver Propagation Delays
B
VOD
A
Figure 2. Driver Timing Test Circuit
RL
CL
90%
tF
tR
DE
DI
1/2 VO
Z
VOC
A
4
tDPHL
10%
XD13085 DIP8 / XL13085 SOP8
Test Circuits and Waveforms (continued)
S1
D
0 OR VCC
OUT
RL = 500Ω
CL
50pF
GENERATOR
50Ω
VCC
DE
VCC/2
tDZH, tDZH(SHDN)
0
0.25V
OUT
VOH
VOM = (0 + VOH)/2
0
tDHZ
Figure 4. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN))
VCC
RL = 500Ω
S1
0 OR VCC
D
OUT
CL
50pF
GENERATOR
50Ω
VCC
DE
VCC/2
tDZL, tDZL(SHDN)
0
tDLZ
VCC
VOM = (VOL + VCC)/2
OUT
VOL
0.25V
Figure 5. Driver Enable and Disable Times (tDZL, tDLZ, tDLZ(SHDN))
5
XD13085 DIP8 / XL13085 SOP8
Test Circuits and Waveforms (continued)
RECEIVER
OUTPUT
B
VID
ATE
R
A
+1V
B
-1V
tRPLH
VOH
A
RO
tRPHL
VCC/2
VOL
THE RISE TIME AND FALL TIME OF INPUTS A AND B < 4ns
Figure 6. Receiver Propagation Delay Test Circuit
Figure 7. Receiver Propagation Delays
S1
+1.5V
S3
VCC
1kΩ
-1.5V
VID
CL
15pF
GENERATOR
S2
50Ω
S1 OPEN
S2 CLOSED
VS3 = +1.5V
S1 CLOSED
S2 OPEN
VS3 = -1.5V
VCC
VCC
VCC/2
RE
RE
0
0
tRZH, tRZH(SHDN)
tRZL, tRZL(SHDN)
VOH
RO
VCC
VOH / 2
(VOL + VCC)/2
RO
0
S1 OPEN
S2 CLOSED
VS3 = +1.5V
RE
50%
VOL
S1 CLOSED
S2 OPEN
VS3 = -1.5V
VCC
VCC/2
tRHZ
50%
0
VCC
VCC/2
RE
0
tRLZ
0.25V
10%
VCC
VOH
RO
0
Figure 8. Receiver Enable and Disable Times
6
RO
10%
0.25V
VOL
XD13085 DIP8 / XL13085 SOP8
Typical Operating Characteristics
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)
1.30
1.20
DE = VCC
1.10
DE = 0
1.00
0.80
40
30
20
XD13085 3
50
40
30
20
10
0
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
1
2
3
4
0
5
0
1
2
3
4
5
OUTPUT HIGH VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
RECEIVER OUTPUT-HIGH VOLTAGE
vs. TEMPERATURE
RECEIVER OUTPUT-LOW VOLTAGE
vs. TEMPERATURE
DRIVER DIFFERENTIAL OUTPUT CURRENT
vs. DIFFERENTIAL OUTPUT VOLTAGE
4.8
4.6
4.4
4.2
0.6
0.5
0.4
0.3
0.2
0.1
4.0
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
XD13085 6
160
DIFFERENTIAL OUTPUT CURRENT (mA)
5.0
IO = 1mA
0.7
OUTPUT LOW VOLTAGE (V)
5.2
0.8
XD13085 4
IO = -1mA
XD13085 5
TEMPERATURE (°C)
5.4
140
120
100
80
60
40
20
0
-40 -25 -10
0
5 20 35 50 65 80 95 110 125
1
2
3
4
5
TEMPERATURE (°C)
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER DIFFERENTIAL OUTPUT
VOLTAGE vs. TEMPERATURE
OUTPUT CURRENT vs. TRANSMITTER
OUTPUT-HIGH VOLTAGE
OUTPUT CURRENT vs. TRANSMITTER
OUTPUT-LOW VOLTAGE
4.4
200
200
180
180
160
3.6
3.2
2.8
2.4
2.0
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
160
4.0
140
120
100
80
60
5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
140
120
100
80
60
40
40
20
20
0
-40 -25 -10
XD13085 9
RL = 54Ω
XD13085 7
4.8
XD13085 8
OUTPUT HIGH VOLTAGE (V)
60
10
0.90
DIFFERENTIAL OUTPUT VOLTAGE (V)
70
OUTPUT CURRENT (mA)
1.40
50
OUTPUT CURRENT (mA)
SUPPLY CURRENT (mA)
1.50
60
XD13085 2
NO LOAD
XD13085 1
1.60
OUTPUT CURRENT
vs. RECEIVER OUTPUT-LOW VOLTAGE
OUTPUT CURRENT
vs. RECEIVER OUTPUT-HIGH VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
0
-7 -6 -5 -4 -3 -2 -1 0
1
2
OUTPUT HIGH VOLTAGE (V)
3
4
5
0
2
4
6
8
10
12
OUTPUT-LOW VOLTAGE (V)
7
XD13085 DIP8 / XL13085 SOP8
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)
8
7
6
5
4
3
2
1
0
-40 -25 -10
5 20 35 50 65 80 95 110 125
tDPHL
500
tDPLH
450
400
350
300
XD13085 2
XD13085 1
550
180
RECEIVER PROPAGATION DELAY (ns)
DRIVER PROPAGATION DELAY (ns)
9
SHUTDOWN CURRENT (µA)
600
XD13085 0
10
RECEIVER PROPAGATION DELAY
vs. TEMPERATURE (500kbps)
DRIVER PROPAGATION DELAY
vs. TEMPERATURE (500kbps)
SHUTDOWN CURRENT
vs. TEMPERATURE
160
140
120
100
tDPLH
80
60
tDPHL
40
20
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
TEMPERATURE (°C)
RECEIVER PROPAGATION DELAY
(500kbps)
TEMPERATURE (°C)
DRIVER PROPAGATION DELAY (500kbps)
XD13085 13
XL13085 14
RL = 100
RL = 100
DI
2V/div
VA - VB
5V/div
RO
2V/div
200ns/div
8
5 20 35 50 65 80 95 110 125
VY - VZ
5V/div
400ns/div
XD13085 DIP8 / XL13085 SOP8
Pin Configuration
+
RO 1
R
RE 2
DE 3
DI 4
D
8
VCC
7
B
6
A
5
GND
SO
Pin Description
PIN
NAME
FUNCTION
1
RO
Receiver Output. When RE is low and if (A - B) R -50mV, RO is high; if (A - B) P -200mV, RO is low.
2
RE
Receiver Output Enable. Drive RE low to enable RO; RO is high impedance when RE is high. Drive
RE high and DE low to enter low-power shutdown mode. RE is a hot-swap input (see the Hot-Swap
Capability section for details).
3
DE
Driver Output Enable. Drive DE high to enable driver outputs. These outputs are high impedance
when DE is low. Drive RE high and DE low to enter low-power shutdown mode. DE is a hot-swap
input (see the Hot-Swap Capability section for details).
4
DI
Driver Input. With DE high, a low on DI forces noninverting output low and inverting output high.
Similarly, a high on DI forces noninverting output high and inverting output low.
5
GND
6
A
Noninverting Receiver Input and Noninverting Driver Output
7
B
Inverting Receiver Input and Inverting Driver Output
8
VCC
Ground
Positive Supply VCC = +5.0V Q10%. Bypass VCC to GND with a 0.1FF capacitor.
Function Tables
TRANSMITTING
INPUTS
RECEIVING
OUTPUTS
INPUTS
OUTPUTS
RE
X
DE
DI
B
A
A-B
RO
1
0
1
RE
0
DE
1
X
R -50mV
1
X
1
0
1
0
0
X
P -200mV
0
0
0
X
High-Z
High-Z
0
X
Open/shorted
1
1
0
X
1
1
X
High-Z
1
0
X
Shutdown
Shutdown
9
XD13085 DIP8 / XL13085 SOP8
Detailed Description
The XD13085 high-speed transceiver for RS-485/
RS-422 communication contains one driver and one
receiver. This device features fail-safe circuitry, which
guarantees a logic-high receiver output when the receiver inputs are open or shorted, or when they are connected to a terminated transmission line with all drivers
disabled (see the Fail-Safe section). The XD13085
also features a hot-swap capability allowing line insertion without erroneous data transfer (see the Hot-Swap
Capability section). The XD13085 features reduced
slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing
error-free data transmission up to 500kbps.
The XD13085 is a half-duplex transceiver and operates from a single +5.0V supply. Drivers are output
short-circuit current limited. Thermal-shutdown circuitry
protects drivers against excessive power dissipation.
When activated, the thermal-shutdown circuitry places
the driver outputs into a high-impedance state.
Fail-Safe
The XD13085 guarantees a logic-high receiver output
when the receiver inputs are shorted or open, or when
they are connected to a terminated transmission line with
all drivers disabled. This is done by setting the receiver
input threshold between -50mV and -200mV. If the differential receiver input voltage (A - B) is greater than or
equal to -50mV, RO is logic-high. If (A - B) is less than
or equal to -200mV, RO is logic-low. In the case of a terminated bus with all transmitters disabled, the receiver’s
differential input voltage is pulled to 0V by the termination. With the receiver threshold of the XD13085,
this results in a logic-high with a 50mV minimum noise
margin. Unlike previous fail-safe devices, the -50mV to
-200mV threshold complies with the ±200mV EIA/TIA485 standard.
Additionally, parasitic circuit board capacitance could
cause coupling of VCC or GND to the enable inputs.
Without the hot-swap capability, these factors could
improperly enable the transceiver’s driver or receiver.
When VCC rises, an internal pulldown circuit holds DE
low and RE high. After the initial power-up sequence,
the pulldown circuit becomes transparent, resetting the
hot-swap tolerable input.
Hot-Swap Input Circuitry
The enable inputs feature hot-swap capability. At the
input there are two nMOS devices, M1 and M2 (Figure 9).
When VCC ramps from zero, an internal 7μs timer turns
on M2 and sets the SR latch, which also turns on M1.
Transistors M2, a 500μA current sink, and M1, a 100μA
current sink, pull DE to GND through a 5kΩ resistor.
M2 is designed to pull DE to the disabled state against
an external parasitic capacitance up to 100pF that can
drive DE high. After 7μs, the timer deactivates M2 while
M1 remains on, holding DE low against three-state leakages that can drive DE high. M1 remains on until an
external source overcomes the required input current.
At this time, the SR latch resets and M1 turns off. When
M1 turns off, DE reverts to a standard, high-impedance
VCC
10µs
TIMER
SR LATCH
TIMER
Hot-Swap Capability
Hot-Swap Inputs
When circuit boards are inserted into a hot or powered
backplane, differential disturbances to the data bus
can lead to data errors. Upon initial circuit board insertion, the data communication processor undergoes
its own power-up sequence. During this period, the
processor’s logic-output drivers are high impedance
and are unable to drive the DE and RE inputs of these
devices to a defined logic level. Leakage currents up
to ±10μA from the high-impedance state of the processor’s logic drivers could cause standard CMOS enable
inputs of a transceiver to drift to an incorrect logic level.
10
5kΩ
DE
(HOT SWAP)
DE
100µA
500µA
M1
M2
Figure 9. Simplified Structure of the Driver Enable Pin (DE)
XD13085 DIP8 / XL13085 SOP8
For RE there is a complementary circuit employing two
pMOS devices pulling RE to VCC.
±30kV ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The driver output and receiver input of the XD13085
have extra protection against static electricity. Maxim’s
engineers have developed state-of-the-art structures to
protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states:
normal operation, shutdown, and powered down. After
an ESD event, the XD13085 keeps working without
latchup or damage.
ESD protection can be tested in various ways. The transmitter output and receiver input of the XD13085 are
characterized for protection to the following limits:
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. However, it does not
specifically refer to integrated circuits. The XD13085
helps you design equipment to meet IEC 61000-4-2, without the need for additional ESD-protection components.
The major difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2 because series resistance
is lower in the IEC 61000-4-2 model. Hence, the ESD
withstand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human
Body Model. Figure 10c shows the IEC 61000-4-2
model, and Figure 10d shows the current waveform for
IEC 61000-4-2 ESD Contact Discharge test.
• ±8kV using the Contact Discharge method specified
in IEC 61000-4-2
• ±15kV using the Air-Gap Discharge method specified
in IEC 61000-4-2
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
RC
1MΩ
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
RD
1500Ω
Machine Model
The machine model for ESD tests all pins using a 200pF
storage capacitor and zero discharge resistance. The
objective is to emulate the stress caused when I/O pins
are contacted by handling equipment during test and
assembly. Of course, all pins require this protection, not
just RS-485 inputs and outputs.
IP 100%
90%
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
• ±15kV using the Human Body Model
Human Body Model
Figure 10a shows the Human Body Model, and Figure 10b
shows the current waveform it generates when discharged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩ resistor.
CMOS input. Whenever VCC drops below 1V, the hotswap input is reset.
Ir
AMPS
DEVICE
UNDER
TEST
36.8%
10%
0
0
Figure 10a. Human Body ESD Test Model
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 10b. Human Body Current Waveform
11
XD13085 DIP8 / XL13085 SOP8
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
Cs
150pF
RD
330Ω
I
100%
90%
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
IPEAK
RC
50MΩ TO 100MΩ
DEVICE
UNDER
TEST
10%
tr = 0.7ns TO 1ns
t
30ns
60ns
Figure 10c. IEC 61000-4-2 ESD Test Model
Applications Information
The standard RS-485 receiver input impedance is 12kΩ
(1-unit load), and the standard driver can drive up
to 32-unit loads. The XD13085 has a 1/8-unit load
receiver input impedance (96kΩ), allowing up to 256
transceivers to be connected in parallel on one communication line. Any combination of the XD13085, as well
as other RS-485 transceivers with a total of 32-unit loads
or fewer, can be connected to the line.
Reduced EMI and Reflections
The XD13085 features reduced slew-rate drivers that
minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 500kbps.
Low-Power Shutdown Mode
Low-power shutdown mode is initiated by bringing both
RE high and DE low. In shutdown, the devices typically
draw only 2.8μA of supply current.
RE and DE can be driven simultaneously; the devices
are guaranteed not to enter shutdown if RE is high and
DE is low for less than 50ns. If the inputs are in this state
for at least 700ns, the devices are guaranteed to enter
shutdown.
12
Figure 10d. IEC 61000-4-2 ESD Generator Current Waveform
Enable times tZH and tZL (see the Switching
Characteristics section) assume the devices were not in
a low-power shutdown state. Enable times tZH(SHDN) and
tZL(SHDN) assume the devices were in shutdown state.
It takes drivers and receivers longer to become enabled
from low-power shutdown mode (tZH(SHDN), tZL(SHDN))
than from driver/receiver-disable mode (tZH, tZL).
Driver Output Protection
Two mechanisms prevent excessive output current and
power dissipation caused by faults or by bus contention. The first, a foldback current limit on the output
stage, provides immediate protection against short circuits over the whole common-mode voltage range (see
the Typical Operating Characteristics). The second, a
thermal-shutdown circuit, forces the driver outputs into
a high-impedance state if the die temperature exceeds
+175°C (typ).
Line Length
The RS-485/RS-422 standard covers line lengths up to
4000ft. For line lengths greater than 4000ft, it may be
necessary to implement a line repeater.
XD13085 DIP8 / XL13085 SOP8
13
DIP8
XD13085 DIP8 / XL13085 SOP8
14
SOP8
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