XD14553

XD14553 DIP16 The XD14553 3 −digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An on−chip oscillator provides the low−frequency scanning clock which drives the multiplexer output selector. This device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications. Features • • • • • • • • • Parameter Symbol Value Unit DC Supply Voltage Range VDD −0.5 to +18.0 V Input or Output Voltage Range (DC or Transient) Vin, Vout −0.5 to VDD + 0.5 V Input Current (DC or Transient) per Pin Iin ±10 mA Output Current (DC or Transient) per Pin Iout +20 mA Power Dissipation, per Package (Note 1) PD 500 mW Ambient Temperature Range TA −55 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Lead Temperature (8−Second Soldering) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. TTL Compatible Outputs On−Chip Oscillator Cascadable Clock Disable Input Pulse Shaping Permits Very Slow Rise Times on Input Clock Output Latches Master Reset These Devices are Pb−Free and are RoHS Compliant NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable 4 MAXIMUM RATINGS (Voltages Referenced to VSS) TRUTH TABLE 3 Inputs CIA 12 CLOCK 10 LE 11 DIS 13 MR CIB Q0 9 Q1 7 Q2 6 Q3 O.F. 5 DS1 DS2 2 1 DS3 15 Master Reset Clock 0 0 0 0 0 0 0 0 1 14 VDD = PIN 16 VSS = PIN 8 X = Don’t Care Figure 1. Block Diagram 1 X 1 1 0 X X X Disable LE Outputs 0 0 1 0 0 X 0 0 X No Change Advance No Change Advance No Change No Change Latched Latched Q0 = Q1 = Q2 = Q3 = 0 X X X X 1 0 XD14553 DIP16 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C 25_C VDD Symbol Vdc Min Max Min Typ (Note 2) Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 10 15 – 0.25 – 0.62 – 1.8 − − − – 0.2 – 0.5 – 1.5 – 0.36 – 0.9 – 3.5 − − − −0.14 −0.35 −1.1 − − − 5.0 10 15 – 0.64 – 1.6 – 4.2 − − − – 0.51 – 1.3 – 3.4 – 0.88 – 2.25 – 8.8 − − − – 0.36 – 0.9 – 2.4 − − − mAdc 5.0 10 15 0.5 1.1 1.8 − − − 0.4 0.9 1.5 0.88 2.25 8.8 − − − 0.28 0.65 1.20 − − − mAdc 5.0 10 15 3.0 6.0 18 − − − 2.5 5.0 15 4.0 8.0 20 − − − 1.6 3.5 10 − − − mAdc Characteristic Output Voltage Vin = VDD or 0 Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) 125_C Output Drive Current (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Source − Pin 3 (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Source − Other Outputs (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink − Pin 3 (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink − Other Outputs IOH IOL Vdc Vdc mAdc Input Current Iin 15 − ± 0.1 − ±0.00001 ± 0.1 − ± 1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) MR = VDD IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.010 0.020 0.030 5.0 10 20 − − − 150 300 600 mAdc IT 5.0 10 15 Total Supply Current (Note 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT = (0.35 mA/kHz) f + IDD IT = (0.85 mA/kHz) f + IDD IT = (1.50 mA/kHz) f + IDD mAdc 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004. 2 XD14553 DIP16 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) VDD Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 tPLH, tPHL 5.0 10 15 − − − 900 500 200 1800 1000 400 ns 2a tPHL 5.0 10 15 − − − 600 400 200 1200 800 400 ns Reset to BCD Out 2b tPHL 5.0 10 15 − − − 900 500 300 1800 1000 600 ns Clock to Latch Enable Setup Time Master Reset to Latch Enable Setup Time 2b tsu 5.0 10 15 600 400 200 300 200 100 − − − ns Removal Time Latch Enable to Clock 2b trem 5.0 10 15 – 80 – 10 0 – 200 – 70 – 50 − − − ns Clock Pulse Width 2a tWH(cl) 5.0 10 15 550 200 150 275 100 75 − − − ns Reset Pulse Width 2b tWH(R) 5.0 10 15 1200 600 450 600 300 225 − − − ns Reset Removal Time − trem 5.0 10 15 – 80 0 20 – 180 – 50 – 30 − − − ns Input Clock Frequency 2a fcl 5.0 10 15 − − − 1.5 5.0 7.0 0.9 2.5 3.5 MHz Input Clock Rise Time 2b tTLH 5.0 10 15 Disable, MR, Latch Enable Rise and Fall Times − tTLH, tTHL 5.0 10 15 − − − − − − 15 5.0 4.0 ms Scan Oscillator Frequency (C1 measured in mF) 1 fosc 5.0 10 15 − − − 1.5/C1 4.2/C1 7.0/C1 − − − Hz Characteristic Figure Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 2a tTLH, tTHL Clock to BCD Out 2a Clock to Overflow No Limit ns ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3 Unit 899 900 901 990 991 992 993 994 995 996 997 998 999 1000 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 XD14553 DIP16 UNITS CLOCK UNITS Q0 UNITS Q1 UNITS Q2 UNITS Q3 TENS CLOCK TENS Q0 TENS Q3 HUNDREDS CLOCK UP AT 980 UP AT 80 HUNDREDS Q0 HUNDREDS Q3 DISABLE UP AT 800 (DISABLES CLOCK WHEN HIGH) OVERFLOW MASTER RESET SCAN OSCILLATOR DIGIT SELECT 1 UNITS TENS DIGIT SELECT 2 DIGIT SELECT 3 HUNDREDS Figure 2. 3−Digit Counter Timing Diagram (Reference Figure 4) VDD Q3 Q2 Q1 Q0 O.F. DS1 DS2 DS3 C LE DIS MR 8 20 ns CL CL CL CL BCD OUT CL 20 ns 90% CLOCK 10% tPLH 1000 16 999 (a) PULSE GENERATOR tWL(cl) 50% 10% tTLH 90% 1/fcl tPHL 50% tTHL tPHL 50% OVERFLOW VSS tTLH (b) GENERATOR 1 CLOCK VDD C GENERATOR 2 LE GENERATOR 3 MR DIS Q3 Q2 Q1 Q0 O.F. DS1 DS2 DS3 50% 90% 10% tsu trem CL LATCH ENABLE CL CL 50% tPHL, tPLH CL CL BCD OUT tsu 50% tPHL VSS 50% MASTER RESET Figure 3. Switching Time Test Circuits and Waveforms 4 tWH(R) XD14553 DIP16 OPERATING CHARACTERISTICS The XD14553 three−digit counter, shown in Figure 4, consists of three negative edge−triggered BCD counters which are cascaded in a synchronous fashion. A quad latch at the output of each of the three BCD counters permits storage of any given count. The three sets of BCD outputs (active high), after going through the latches, are time division multiplexed, providing one BCD number or digit at a time. Digit select outputs (active low) are provided for display control. All outputs are TTL compatible. An on−chip oscillator provides the low frequency scanning clock which drives the multiplexer output selector. The frequency of the oscillator can be controlled externally by a capacitor between pins 3 and 4, or it can be overridden and driven with an external clock at pin 4. Multiple devices can be cascaded using the overflow output, which provides one pulse for every 1000 counts. The Master Reset input, when taken high, initializes the three BCD counters and the multiplexer scanning circuit. While Master Reset is high the digit scanner is set to digit one; but all three−digit select outputs are disabled to prolong display life, and the scan oscillator is inhibited. The Disable input, when high, prevents the input clock from reaching the counters, while still retaining the last count. A pulse shaping circuit at the clock input permits the counters to continue operating on input pulses with very slow rise times. Information present in the counters when the latch input goes high, will be stored in the latches and will be retained while the latch input is high, independent of other inputs. Information can be recovered from the latches after the counters have been reset if Latch Enable remains high during the entire reset cycle. C1A 4 SCAN R OSCILLATOR 3 C1B LATCH ENABLE 10 CLOCK 12 PULSE SHAPER C1 PULSE GENERATOR R SCANNER Q0 Q1 Q2 R ÷ 10 Q3 UNITS C QUAD LATCH 9 11 DISABLE (ACTIVE HIGH) MULTIPLEXER 7 Q0 Q1 Q2 R ÷ 10 Q3 TENS C Q1 QUAD LATCH BCD OUTPUTS (ACTIVE HIGH) 6 Q0 Q1 Q2 R ÷ 10 Q3 HUNDREDS C 13 MR (ACTIVE HIGH) Q0 5 QUAD LATCH 2 1 15 DS1 DS2 DS3 (LSD) DIGIT SELECT (MSD) (ACTIVE LOW) 14 OVERFLOW Figure 4. Expanded Block Diagram 5 Q2 Q3 CLOCK INPUT VDD STROBE RESET 11 12 XD14553 13 MR C1B C1A Figure 5. Six−Digit Display 6 LSD 5 A 3 B 2 C 4 D XD14553 6 Ph 1 LD 7 BI 9 a b 10 11 c 12 d 13 e 15 f 14 g O.F. Q3 Q2 Q1 Q0 DS3 DS2 DS1 5 6 7 9 15 1 2 DIS CLK 10 LE 14 3 4 0.001 μF XD14553 MR 13 C1 B C1 A DISPLAYS ARE LOW CURRENT LEDs (I peak < 10 mA PER SEGMENT) VDD C B A MSD D XD14553 6 Ph 1 LD 7 BI 4 2 3 5 O.F. Q3 Q2 Q1 Q0 DS3 DS2 DS1 5 6 7 9 15 1 2 DIS CLK VDD 11 12 LE 10 9 10 b 11 c 12 d 13 e 15 f g 14 a 14 4 3 XD14553 DIP16 XD14553 DIP16 DIP 67