XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
Power Factor Controllers
The XD34262/XD33262 are active power factor controllers
specifically designed for use as a preconverter in electronic ballast
and in off−line power converter applications. These integrated
circuits feature an internal startup timer for stand−alone applications,
a one quadrant multiplier for near unity power factor, zero current
detector to ensure critical conduction operation, transconductance
error amplifier, quickstart circuit for enhanced startup, trimmed
internal bandgap reference, current sensing comparator, and a totem
pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of an overvoltage
comparator to eliminate runaway output voltage due to load removal,
input undervoltage lockout with hysteresis, cycle−by−cycle current
limiting, multiplier output clamp that limits maximum peak switch
current, an RS latch for single pulse metering, and a drive output high
state clamp for MOSFET gate protection. These devices are
available in dual−in−line and surface mount plastic packages.
Zero Current Detector
5
Zero Current
Detect Input
Features
• Overvoltage Comparator Eliminates Runaway
•
•
•
•
•
•
•
•
Output Voltage
Internal Startup Timer
One Quadrant Multiplier
Zero Current Detector
Trimmed 2% Internal Bandgap Reference
Totem Pole Output with High State Clamp
Undervoltage Lockout with 6.0 V of Hysteresis
Low Startup and Operating Current
These are Pb−Free and Halide−Free Devices
PIN CONNECTIONS
Voltage Feedback
Input
Compensation
Multiplier Input
Current Sense
Input
1
8 VCC
2
7 Drive Output
6 GND
5 Zero Current
Detect Input
3
4
(Top View)
2.5V
Reference
Undervoltage
Lockout
VCC
8
Drive Output
7
Multiplier,
Latch,
PWM,
Timer,
&
Logic
Overvoltage
Comparator
+
Error Amp
Multiplier
Input 3
4
Current Sense
Input
1.08 Vref
+
Vref
Multiplier
Voltage
Feedback
1 Input
Quickstart
GND
6
Compensation
2
Figure 1. Simplified Block Diagram
1
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
(ICC + IZ)
30
mA
Output Current, Source or Sink (Note 1)
IO
500
mA
Current Sense, Multiplier, and Voltage Feedback Inputs
Vin
−1.0 to +10
V
Zero Current Detect Input
High State Forward Current
Low State Reverse Current
Iin
Total Power Supply and Zener Current
Power Dissipation and Thermal Characteristics
P Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance, Junction−to−Air
D Suffix, Plastic Package, Case 751
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance, Junction−to−Air
mA
50
−10
PD
RqJA
800
100
mW
°C/W
PD
RqJA
450
178
mW
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature (Note 4)
XD34262
XD33262
TA
Storage Temperature
Tstg
− 65 to +150
°C
HBM
MM
CDM
2000
200
2000
V
V
V
ESD Protection (Note 2)
Human Body Model ESD
Machine Model ESD
Charged Device Model ESD
0 to + 85
− 40 to +105
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum package power dissipation limits must be observed.
2. ESD protection per JEDEC JESD22−A114−F for HBM, per JEDEC JESD22−A115−A for MM, and per JEDEC JESD22−C101D for CDM.
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS (VCC = 12 V (Note 3), for typical values TA = 25°C, for min/max values TA is the operating
ambient temperature range that applies (Note 4), unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
2.465
2.44
2.5
−
2.535
2.54
Regline
−
1.0
10
mV
Input Bias Current (VFB = 0 V)
IIB
−
− 0.1
− 0.5
mA
Transconductance (TA = 25°C)
gm
80
100
130
mmho
Output Current
Source (VFB = 2.3 V)
Sink (VFB = 2.7 V)
IO
−
−
10
10
−
−
VOH(ea)
VOL(ea)
5.8
−
6.4
1.7
−
2.4
VFB(OV)
1.065 VFB
1.08 VFB
1.095 VFB
V
IIB
−
− 0.1
− 0.5
mA
Vth(M)
1.05 VOL(EA)
1.2 VOL(EA)
−
V
ERROR AMPLIFIER
Voltage Feedback Input Threshold
TA = 25°C
TA = Tlow to Thigh (VCC = 12 V to 28 V)
VFB
Line Regulation (VCC = 12 V to 28 V, TA = 25°C)
Output Voltage Swing
High State (VFB = 2.3 V)
Low State (VFB = 2.7 V)
V
mA
V
OVERVOLTAGE COMPARATOR
Voltage Feedback Input Threshold
MULTIPLIER
Input Bias Current, Pin 3 (VFB = 0 V)
Input Threshold, Pin 2
3. Adjust VCC above the startup threshold before setting to 12 V.
4. Tlow = 0°C for XD34262
T high = +85°C for XD34262
= −40°C for XD33262
= +105°C for XD33262.
2
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V (Note 6), for typical values TA = 25°C, for min/max values TA is the
operating ambient temperature range that applies (Note 7), unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
VPin 3
VPin 2
0 to 2.5
Vth(M) to
(Vth(M) + 1.0)
0 to 3.5
Vth(M) to
(Vth(M) + 1.5)
−
−
K
0.43
0.65
0.87
1/V
Input Threshold Voltage (Vin Increasing)
Vth
1.33
1.6
1.87
V
Hysteresis (Vin Decreasing)
VH
100
200
300
mV
Input Clamp Voltage
High State (IDET = + 3.0 mA)
Low State (IDET = − 3.0 mA)
VIH
VIL
6.1
0.3
6.7
0.7
−
1.0
Input Bias Current (VPin 4 = 0 V)
IIB
−
− 0.15
−1.0
mA
Input Offset Voltage (VPin 2 = 1.1 V, VPin 3 = 0 V)
VIO
−
9.0
25
mV
Vth(max)
1.3
1.5
1.8
V
tPHL(in/out)
−
200
400
ns
VOL
−
−
9.8
7.8
0.3
2.4
10.3
8.4
0.8
3.3
−
−
14
16
18
MULTIPLIER
Dynamic Input Voltage Range
Multiplier Input (Pin 3)
Compensation (Pin 2)
V
Multiplier Gain (VPin 3 = 0.5 V, VPin 2 = Vth(M) + 1.0 V) (Note 8)
ZERO CURRENT DETECTOR
V
CURRENT SENSE COMPARATOR
Maximum Current Sense Input Threshold (Note 9)
Delay to Output
DRIVE OUTPUT
Output Voltage (VCC = 12 V)
Low State
(ISink = 20 mA)
Low State
(ISink = 200 mA)
High State (ISource = 20 mA)
High State (ISource = 200 mA)
V
VOH
Output Voltage (VCC = 30 V)
High State (ISource = 20 mA, CL = 15 pF)
VO(max)
Output Voltage Rise Time (CL = 1.0 nF)
tr
−
50
120
ns
Output Voltage Fall Time (CL = 1.0 nF)
tf
−
50
120
ns
VO(UVLO)
−
0.1
0.5
V
tDLY
200
620
−
ms
Vth(on)
11.5
13
14.5
V
VShutdown
7.0
8.0
9.0
V
VH
3.8
5.0
6.2
V
−
−
−
0.25
6.5
9.0
0.4
12
20
30
36
−
Output Voltage with UVLO Activated
(VCC = 7.0 V, ISink = 1.0 mA)
V
RESTART TIMER
Restart Time Delay
UNDERVOLTAGE LOCKOUT
Startup Threshold (VCC Increasing)
Minimum Operating Voltage After Turn−On (VCC Decreasing)
Hysteresis
TOTAL DEVICE
Power Supply Current
Startup (VCC = 7.0 V)
Operating
Dynamic Operating (50 kHz, CL = 1.0 nF)
ICC
Power Supply Zener Voltage (ICC = 25 mA)
VZ
5. Maximum package power dissipation limits must be observed.
6. Adjust VCC above the startup threshold before setting to 12 V.
7. Tlow = 0°C for XD34262
T high = +85°C for XD34262
= −40°C for XD33262
= +105°C for XD33262.
Pin 4 Threshold
8. K +
VPin 3 (VPin2 * Vth(M))
9. This parameter is measured with VFB = 0 V, and VPin 3 = 3.0 V.
3
mA
V
VCS, CURRENT SENSE PIN 4 THRESHOLD (V)
1.6
VCC = 12 V
TA = 25°C
1.4
1.2
VPin 2 = 3.75 V
VPin 2 = 3.5 V
1.0
VPin 2 = 2.75 V
VPin 2 = 3.25 V
0.8
VPin 2 = 2.5 V
VPin 2 = 3.0 V
0.6
VPin 2 = 2.25 V
0.4
0.2
VPin 2 = 2.0 V
0
-0.2
0.6
1.4
2.2
3.0
3.8
0.08
VPin 2 = 3.75 V
VPin 2 = 3.5 V
VPin 2 = 3.25 V
0.06 VPin 2 = 3.0 V
0.05 VPin 2 = 2.75 V
0.07
0.02
0
-4.0
-8.0
-12
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
DVFB(OV), OVERVOLTAGE INPUT THRESHOLD (%VFB)
DVFB, VOLTAGE FEEDBACK THRESHOLD CHANGE (mV)
VCC = 12 V
Pins 1 to 2
25
0
-0.12
0.24
VCC = 12 V
109
108
107
106
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 5. Overvoltage Comparator Input
Threshold versus Temperature
0
Transconductance
80
VCC = 12 V
VO = 2.5 V to 3.5 V
RL = 100 k to 3.0 V
CL = 2.0 pF
TA = 25°C
4.00 V
30
60
60
90
40
120
20
150
0
3.0 k
10 k
30 k
100 k 300 k
f, FREQUENCY (Hz)
1.0 M
180
3.0 M
Figure 6. Error Amp Transconductance and
Phase versus Frequency
VCC = 12 V
RL = 100 k
CL = 2.0 pF
TA = 25°C
3.25 V
0
Phase
q, EXCESS PHASE (DEGREES)
120
gm, TRANSCONDUCTANCE (mmho)
-0.06
0
0.06
0.12
0.18
VM, MULTIPLIER PIN 3 INPUT VOLTAGE (V)
110
Figure 4. Voltage Feedback Input Threshold
Change versus Temperature
100
VPin 2 = 2.0 V
0.01
Figure 3. Current Sense Input Threshold
versus Multiplier Input, Expanded View
4.0
0
VPin 2 = 2.25 V
0.03
Figure 2. Current Sense Input Threshold
versus Multiplier Input
-25
VPin 2 = 2.5 V
0.04
VM, MULTIPLIER PIN 3 INPUT VOLTAGE (V)
-16
-55
VCC = 12 V
TA = 25°C
V/DIV
VCS, CURRENT SENSE PIN 4 THRESHOLD (V)
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
2.50 V
5.0 ms/DIV
Figure 7. Error Amp Transient Response
4
1.76
800
1.72
700
Voltage
Current
600
1.68
1.64
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
500
125
100
800
VCC = 12 V
700
600
500
400
-55
Figure 8. Quickstart Charge Current
versus Temperature
Vsat, OUTPUT SATURATION VOLTAGE (V)
1.5
1.4
Lower Threshold
(Vin, Decreasing)
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
125
0
VCC
VCC = 12 V
80 ms Pulsed Load
120 Hz Rate
-2.0
Source Saturation
(Load to Ground)
-4.0
-6.0
4.0
Sink Saturation
(Load to VCC)
2.0
0
GND
0
80
160
240
320
IO, OUTPUT LOAD CURRENT (mA)
Figure 11. Output Saturation Voltage
versus Load Current
VO , OUTPUT VOLTAGE
Figure 10. Zero Current Detector Input
Threshold Voltage versus Temperature
I CC , SUPPLY CURRENT
VCC = 12 V
CL = 1.0 nF
TA = 25°C
90%
100
10%
100 ns/DIV
Figure 12. Drive Output Waveform
VCC = 12 V
CL = 15 pF
TA = 25°C
100 mA/DIV
Vth, THRESHOLD VOLTAGE (V)
VCC = 12 V
1.6
1.3
-55
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
Figure 9. Restart Timer Delay
versus Temperature
1.7
Upper Threshold
(Vin, Increasing)
-25
100 ns/DIV
Figure 13. Drive Output Cross Conduction
5
5.0 V/DIV
Vchg, QUICKSTART CHARGE VOLTAGE (V)
VCC = 12 V
tDLY, RESTART TIME DELAY (ms)
900
1.80
Ichg, QUICKSTART CHARGE CURRENT (mA)
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
14
VCC , SUPPLY VOLTAGE (V)
I CC , SUPPLY CURRENT (mA)
16
12
8.0
VFB = 0 V
Current Sense = 0 V
Multiplier = 0 V
CL = 1.0 nF
f = 50 kHz
TA = 25°C
4.0
0
0
10
20
30
VCC, SUPPLY VOLTAGE (V)
13
Startup Threshold
(VCC Increasing)
12
11
10
9.0
Minimum Operating Threshold
(VCC Decreasing)
8.0
7.0
-55
40
Figure 14. Supply Current
versus Supply Voltage
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 15. Undervoltage Lockout Thresholds
versus Temperature
FUNCTIONAL DESCRIPTION
Introduction
frequency switching converter for the power processing,
with the boost converter being the most popular topology,
Figure 18. Since active input circuits operate at a frequency
much higher than that of the ac line, they are smaller,
lighter in weight, and more efficient than a passive circuit
that yields similar results. With proper control of the
preconverter, almost any complex load can be made to
appear resistive to the ac line, thus significantly reducing
the harmonic current content.
With the goal of exceeding the requirements of
legislation on line−current harmonic content, there is an
ever increasing demand for an economical method of
obtaining a unity power factor. This data sheet describes a
monolithic control IC that was specifically designed for
power factor control with minimal external components. It
offers the designer a simple, cost−effective solution to
obtain the benefits of active power factor correction.
Most electronic ballasts and switching power supplies
use a bridge rectifier and a bulk storage capacitor to derive
raw dc voltage from the utility ac line, Figure 16.
Rectifiers
Vpk
Rectified
DC
Converter
AC
Line
0
+
Bulk
Storage
Capacitor
Line Sag
Load
AC Line
Voltage
Figure 16. Uncorrected Power Factor Circuit
0
This simple rectifying circuit draws power from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. This occurs near the line voltage peak and results
in a high charge current spike, Figure 17. Since power is
only taken near the line voltage peaks, the resulting spikes
of current are extremely nonsinusoidal with a high content
of harmonics. This results in a poor power factor condition
where the apparent input power is much higher than the real
power. Power factor ratios of 0.5 to 0.7 are common.
Power factor correction can be achieved with the use of
either a passive or an active input circuit. Passive circuits
usually contain a combination of large capacitors,
inductors, and rectifiers that operate at the ac line
frequency. Active circuits incorporate some form of a high
AC Line
Current
Figure 17. Uncorrected Power Factor
Input Waveforms
The XD34262, XD33262 are high performance, critical
conduction, current−mode power factor controllers
specifically designed for use in off−line active
preconverters. These devices provide the necessary
features required to significantly enhance poor power
factor loads by keeping the ac line current sinusoidal and
in phase with the line voltage.
6
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
Operating Description
3842 series. Referring to the block diagrams in
Figures 20, 21, and 22 note that a multiplier has been added
to the current sense loop and that this device does not
contain an oscillator. The reasons for these differences will
become apparent in the following discussion. A description
of each of the functional blocks is given below.
The XD34262, XD33262 contain many of the building
blocks and protection features that are employed in modern
high performance current mode power supply controllers.
There are, however, two areas where there is a major
difference when compared to popular devices such as the
Rectifiers
PFC Preconverter
AC
Line
+
High
Frequency
Bypass
Capacitor
Converter
+
XD34362
Bulk
Storage
Capacitor
Load
Figure 18. Active Power Factor Correction Preconverter
Error Amplifier
can occur during initial startup, sudden load removal, or
during output arcing and is the result of the low bandwidth
that must be used in the Error Amplifier control loop. The
Overvoltage Comparator monitors the peak output voltage
of the converter, and when exceeded, immediately
terminates MOSFET switching. The comparator threshold
is internally set to 1.08 Vref. In order to prevent false
tripping during normal operation, the value of the output
filter capacitor C3 must be large enough to keep the
peak−to−peak ripple less than 16% of the average dc
output. The Overvoltage Comparator input to Drive Output
turn−off propagation delay is typically 400 ns. A
comparison of startup overshoot without and with the
Overvoltage Comparator circuit is shown in Figure 24.
An Error Amplifier with access to the inverting input and
output is provided. The amplifier is a transconductance
type, meaning that it has high output impedance with
controlled voltage−to−current gain. The amplifier features
a typical gm of 100 mmhos (Figure 6). The noninverting
input is internally biased at 2.5 V ± 2.0% and is not pinned
out. The output voltage of the power factor converter is
typically divided down and monitored by the inverting
input. The maximum input bias current is − 0.5 mA, which
can cause an output voltage error that is equal to the product
of the input bias current and the value of the upper divider
resistor R2. The Error Amp output is internally connected
to the Multiplier and is pinned out (Pin 2) for external loop
compensation. Typically, the bandwidth is set below 20 Hz,
so that the amplifier’s output voltage is relatively constant
over a given ac line cycle. In effect, the error amp monitors
the average output voltage of the converter over several
line cycles. The Error Amp output stage was designed to
have a relatively constant transconductance over
temperature. This allows the designer to define the
compensated bandwidth over the intended operating
temperature range. The output stage can sink and source
10 mA of current and is capable of swinging from 1.7 V to
6.4 V, assuring that the Multiplier can be driven over its
entire dynamic range.
A key feature to using a transconductance type amplifier,
is that the input is allowed to move independently with
respect to the output, since the compensation capacitor is
connected to ground. This allows dual usage of of the
Voltage Feedback Input pin by the Error Amplifier and by
the Overvoltage Comparator.
Multiplier
A single quadrant, two input multiplier is the critical
element that enables this device to control power factor.
The ac full wave rectified haversines are monitored at Pin 3
with respect to ground while the Error Amp output at Pin 2
is monitored with respect to the Voltage Feedback Input
threshold. The Multiplier is designed to have an extremely
linear transfer curve over a wide dynamic range, 0 V to
3.2 V for Pin 3, and 2.0 V to 3.75 V for Pin 2, Figures 2 and
3. The Multiplier output controls the Current Sense
Comparator threshold as the ac voltage traverses
sinusoidally from zero to peak line, Figure 18. This has the
effect of forcing the MOSFET on−time to track the input
line voltage, resulting in a fixed Drive Output on−time, thus
making the preconverter load appear to be resistive to the
ac line. An approximation of the Current Sense
Comparator threshold can be calculated from the following
equation. This equation is accurate only under the given
test condition stated in the electrical table.
Overvoltage Comparator
An Overvoltage Comparator is incorporated to eliminate
the possibility of runaway output voltage. This condition
VCS, Pin 4 Threshold ≈ 0.65 (VPin 2 − Vth(M)) VPin 3
7
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
Current Sense Comparator and RS Latch
A significant reduction in line current distortion can be
attained by forcing the preconverter to switch as the ac line
voltage crosses through zero. The forced switching is
achieved by adding a controlled amount of offset to the
Multiplier and Current Sense Comparator circuits. The
equation shown below accounts for the built−in offsets and
is accurate to within ten percent. Let Vth(M) = 1.991 V
The Current Sense Comparator RS Latch configuration
used ensures that only a single pulse appears at the Drive
Output during a given cycle. The inductor current is
converted to a voltage by inserting a ground−referenced
sense resistor R7 in series with the source of output switch
Q1. This voltage is monitored by the Current Sense Input
and compared to a level derived from the Multiplier output.
The peak inductor current under normal operating
conditions is controlled by the threshold voltage of Pin 4
where:
VCS, Pin 4 Threshold = 0.544 (VPin 2 − Vth(M)) VPin 3
+ 0.0417 (VPin 2 − Vth(M))
Zero Current Detector
The XD34262 operates as a critical conduction current
mode controller, whereby output switch conduction is
initiated by the Zero Current Detector and terminated when
the peak inductor current reaches the threshold level
established by the Multiplier output. The Zero Current
Detector initiates the next on−time by setting the RS Latch
at the instant the inductor current reaches zero. This critical
conduction mode of operation has two significant benefits.
First, since the MOSFET cannot turn−on until the inductor
current reaches zero, the output rectifier reverse recovery
time becomes less critical, allowing the use of an
inexpensive rectifier. Second, since there are no deadtime
gaps between cycles, the ac line current is continuous, thus
limiting the peak switch to twice the average input current.
The Zero Current Detector indirectly senses the inductor
current by monitoring when the auxiliary winding voltage
falls below 1.4 V. To prevent false tripping, 200 mV of
hysteresis is provided. Figure 10 shows that the thresholds
are well−defined over temperature. The Zero Current
Detector input is internally protected by two clamps. The
upper 6.7 V clamp prevents input overvoltage breakdown
while the lower 0.7 V clamp prevents substrate injection.
Current limit protection of the lower clamp transistor is
provided in the event that the input pin is accidentally
shorted to ground. The Zero Current Detector input to
Drive Output turn−on propagation delay is typically 320 ns.
IL(pk ) =
Pin 4 Threshold
R7
Abnormal operating conditions occur during
preconverter startup at extremely high line or if output
voltage sensing is lost. Under these conditions, the
Multiplier output and Current Sense threshold will be
internally clamped to 1.5 V. Therefore, the maximum peak
switch current is limited to:
Ipk(max) =
1.5 V
R7
An internal RC filter has been included to attenuate any
high frequency noise that may be present on the current
waveform. This filter helps reduce the ac line current
distortion especially near the zero crossings. With the
component values shown in Figure 21, the Current Sense
Comparator threshold, at the peak of the haversine varies
from 1.1 V at 90 Vac to 100 mV at 268 Vac. The Current
Sense Input to Drive Output turn−off propagation delay is
typically less than 200 ns.
Timer
A watchdog timer function was added to the IC to
eliminate the need for an external oscillator when used in
stand−alone applications. The Timer provides a means to
automatically start or restart the preconverter if the Drive
Output has been off for more than 620 ms after the inductor
current reaches zero. The restart time delay versus
temperature is shown in Figure 9.
Peak
Undervoltage Lockout and Quickstart
Inductor Current
An Undervoltage Lockout comparator has been
incorporated to guarantee that the IC is fully functional
before enabling the output stage. The positive power
supply terminal (VCC) is monitored by the UVLO
comparator with the upper threshold set at 13 V and the
lower threshold at 8.0 V. In the stand−by mode, with VCC
at 7.0 V, the required supply current is less than 0.4 mA.
This large hysteresis and low startup current allow the
implementation of efficient bootstrap startup techniques,
making these devices ideally suited for wide input range
off−line preconverter applications. An internal 36 V
clamp has been added from VCC to ground to protect the IC
and capacitor C4 from an overvoltage condition. This
feature is desirable if external circuitry is used to delay the
startup of the preconverter. The supply current, startup, and
operating voltage characteristics are shown in Figures 14
and 15.
Average
0
On
MOSFET
Q1
Off
Figure 19. Inductor Current and MOSFET
Gate Voltage Waveforms
8
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
MOSFETs. The Drive Output is capable of up to ±500 mA
peak current with a typical rise and fall time of 50 ns with
a 1.0 nF load. Additional internal circuitry has been added
to keep the Drive Output in a sinking mode whenever the
Undervoltage Lockout is active. This characteristic
eliminates the need for an external gate pulldown resistor.
The totem−pole output has been optimized to minimize
cross−conduction current during high speed operation. The
addition of two 10 W resistors, one in series with the source
output transistor and one in series with the sink output
transistor, helps to reduce the cross−conduction current and
radiated noise by limiting the output rise and fall time. A
16 V clamp has been incorporated into the output stage to
limit the high state VOH. This prevents rupture of the
MOSFET gate when VCC exceeds 20 V.
A Quickstart circuit has been incorporated to optimize
converter startup. During initial startup, compensation
capacitor C1 will be discharged, holding the error amp
output below the Multiplier threshold. This will prevent
Drive Output switching and delay bootstrapping of
capacitor C4 by diode D6. If Pin 2 does not reach the
multiplier threshold before C4 discharges below the lower
UVLO threshold, the converter will “hiccup” and
experience a significant startup delay. The Quickstart
circuit is designed to precharge C1 to 1.7 V, Figure 8. This
level is slightly below the Pin 2 Multiplier threshold,
allowing immediate Drive Output switching and bootstrap
operation when C4 crosses the upper UVLO threshold.
Drive Output
The XD34262/XD33262 contain a single totem −pole
output stage specifically designed for direct drive of power
APPLICATIONS INFORMATION
The application circuits shown in Figures 20, 21 and 22
reveal that few external components are required for a
complete power factor preconverter. Each circuit is a peak
detecting current−mode boost converter that operates in
critical conduction mode with a fixed on−time and variable
off−time. A major benefit of critical conduction operation
is that the current loop is inherently stable, thus eliminating
the need for ramp compensation. The application in
Figure 20 operates over an input voltage range of 90 Vac to
138 Vac and provides an output power of 80 W (230 V at
350 mA) with an associated power factor of approximately
0.998 at nominal line. Figures 21 and 22 are universal input
preconverter examples that operate over a continuous input
voltage range of 90 Vac to 268 Vac. Figure 21 provides an
output power of 175 W (400 V at 440 mA) while Figure 22
provides 450 W (400 V at 1.125 A). Both circuits have an
observed worst−case power factor of approximately 0.989.
The input current and voltage waveforms of Figure 21 are
shown in Figure 23 with operation at 115 Vac and 230 Vac.
The data for each of the applications was generated with the
test set−up shown in Figure 25.
9
XL33262 SOP8 XD33262 DIP8
XL34262 SOP8 XD34262 DIP8
Table 1. Design Equations
Calculation
Formula
Calculate the maximum required output power.
Notes
Required Converter Output Power
PO = VO IO
Calculated at the minimum required ac line voltage
for output regulation. Let the efficiency h = 0.92 for
low line operation.
Peak Inductor Current
Let the switching cycle t = 40 ms for universal input
(85 to 265 Vac) operation and 20 ms for fixed input
(92 to 138 Vac, or 184 to 276 Vac) operation.
In theory the on−time ton is constant. In practice ton
tends to increase at the ac line zero crossings due
to the charge on capacitor C5. Let Vac = Vac(LL) for initial
ton and toff calculations.
Inductance
2
IL(pk) =
t
LP =
ǒ
Ǔ
VO
h Vac(LL)2
− Vac(LL)
2
2 VO PO
Switch On−Time
2 PO LP
ton =
The off−time toff is greatest at the peak of the ac line
voltage and approaches zero at the ac line zero
crossings. Theta (q) represents the angle of the ac
line voltage.
Switch Off−Time
The minimum switching frequency occurs at the peak
of the ac line voltage. As the ac line voltage traverses
from peak to zero, toff approaches zero producing an
increase in switching frequency.
Switching Frequency
f=
Set the current sense threshold VCS to 1.0 V for
universal input (85 Vac to 265 Vac) operation and
to 0.5 V for fixed input (92 Vac to 138 Vac, or
184 Vac to 276 Vac) operation. Note that VCS must
be
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